xref: /openbmc/u-boot/arch/powerpc/lib/ppccache.S (revision 6d97dc10)
1/*
2 * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9
10#include <config.h>
11#include <ppc_asm.tmpl>
12#include <ppc_defs.h>
13
14#include <asm/cache.h>
15
16/*------------------------------------------------------------------------------- */
17/* Function:	 ppcDcbf */
18/* Description:	 Data Cache block flush */
19/* Input:	 r3 = effective address */
20/* Output:	 none. */
21/*------------------------------------------------------------------------------- */
22	.globl	ppcDcbf
23ppcDcbf:
24	dcbf	r0,r3
25	blr
26
27/*------------------------------------------------------------------------------- */
28/* Function:	 ppcDcbi */
29/* Description:	 Data Cache block Invalidate */
30/* Input:	 r3 = effective address */
31/* Output:	 none. */
32/*------------------------------------------------------------------------------- */
33	.globl	ppcDcbi
34ppcDcbi:
35	dcbi	r0,r3
36	blr
37
38/*--------------------------------------------------------------------------
39 * Function:	 ppcDcbz
40 * Description:	 Data Cache block zero.
41 * Input:	 r3 = effective address
42 * Output:	 none.
43 *-------------------------------------------------------------------------- */
44
45	.globl	ppcDcbz
46ppcDcbz:
47	dcbz	r0,r3
48	blr
49
50/*------------------------------------------------------------------------------- */
51/* Function:	 ppcSync */
52/* Description:	 Processor Synchronize */
53/* Input:	 none. */
54/* Output:	 none. */
55/*------------------------------------------------------------------------------- */
56	.globl	ppcSync
57ppcSync:
58	sync
59	blr
60
61/*
62 * Write any modified data cache blocks out to memory and invalidate them.
63 * Does not invalidate the corresponding instruction cache blocks.
64 *
65 * flush_dcache_range(unsigned long start, unsigned long stop)
66 */
67_GLOBAL(flush_dcache_range)
68	li	r5,L1_CACHE_BYTES-1
69	andc	r3,r3,r5
70	subf	r4,r3,r4
71	add	r4,r4,r5
72	srwi.	r4,r4,L1_CACHE_SHIFT
73	beqlr
74	mtctr	r4
75
761:	dcbf	0,r3
77	addi	r3,r3,L1_CACHE_BYTES
78	bdnz	1b
79	sync				/* wait for dcbst's to get to ram */
80	blr
81
82/*
83 * Like above, but invalidate the D-cache.  This is used by the 8xx
84 * to invalidate the cache so the PPC core doesn't get stale data
85 * from the CPM (no cache snooping here :-).
86 *
87 * invalidate_dcache_range(unsigned long start, unsigned long stop)
88 */
89_GLOBAL(invalidate_dcache_range)
90	li	r5,L1_CACHE_BYTES-1
91	andc	r3,r3,r5
92	subf	r4,r3,r4
93	add	r4,r4,r5
94	srwi.	r4,r4,L1_CACHE_SHIFT
95	beqlr
96	mtctr	r4
97
98	sync
991:	dcbi	0,r3
100	addi	r3,r3,L1_CACHE_BYTES
101	bdnz	1b
102	sync				/* wait for dcbi's to get to ram */
103	blr
104
105