1 /* 2 * (C) Copyright 2002 3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #include <common.h> 26 #include <asm/processor.h> 27 #include <asm/mmu.h> 28 #include <asm/io.h> 29 #include <linux/compiler.h> 30 31 #ifdef CONFIG_ADDR_MAP 32 #include <addr_map.h> 33 #endif 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) 38 { 39 __maybe_unused int batn = -1; 40 41 sync(); 42 43 switch (bat) { 44 case DBAT0: 45 mtspr (DBAT0L, lower); 46 mtspr (DBAT0U, upper); 47 batn = 0; 48 break; 49 case IBAT0: 50 mtspr (IBAT0L, lower); 51 mtspr (IBAT0U, upper); 52 break; 53 case DBAT1: 54 mtspr (DBAT1L, lower); 55 mtspr (DBAT1U, upper); 56 batn = 1; 57 break; 58 case IBAT1: 59 mtspr (IBAT1L, lower); 60 mtspr (IBAT1U, upper); 61 break; 62 case DBAT2: 63 mtspr (DBAT2L, lower); 64 mtspr (DBAT2U, upper); 65 batn = 2; 66 break; 67 case IBAT2: 68 mtspr (IBAT2L, lower); 69 mtspr (IBAT2U, upper); 70 break; 71 case DBAT3: 72 mtspr (DBAT3L, lower); 73 mtspr (DBAT3U, upper); 74 batn = 3; 75 break; 76 case IBAT3: 77 mtspr (IBAT3L, lower); 78 mtspr (IBAT3U, upper); 79 break; 80 #ifdef CONFIG_HIGH_BATS 81 case DBAT4: 82 mtspr (DBAT4L, lower); 83 mtspr (DBAT4U, upper); 84 batn = 4; 85 break; 86 case IBAT4: 87 mtspr (IBAT4L, lower); 88 mtspr (IBAT4U, upper); 89 break; 90 case DBAT5: 91 mtspr (DBAT5L, lower); 92 mtspr (DBAT5U, upper); 93 batn = 5; 94 break; 95 case IBAT5: 96 mtspr (IBAT5L, lower); 97 mtspr (IBAT5U, upper); 98 break; 99 case DBAT6: 100 mtspr (DBAT6L, lower); 101 mtspr (DBAT6U, upper); 102 batn = 6; 103 break; 104 case IBAT6: 105 mtspr (IBAT6L, lower); 106 mtspr (IBAT6U, upper); 107 break; 108 case DBAT7: 109 mtspr (DBAT7L, lower); 110 mtspr (DBAT7U, upper); 111 batn = 7; 112 break; 113 case IBAT7: 114 mtspr (IBAT7L, lower); 115 mtspr (IBAT7U, upper); 116 break; 117 #endif 118 default: 119 return (-1); 120 } 121 122 #ifdef CONFIG_ADDR_MAP 123 if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) { 124 phys_size_t size; 125 if (!BATU_VALID(upper)) 126 size = 0; 127 else 128 size = BATU_SIZE(upper); 129 addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), 130 size, batn); 131 } 132 #endif 133 134 sync(); 135 isync(); 136 137 return (0); 138 } 139 140 int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) 141 { 142 unsigned long register u; 143 unsigned long register l; 144 145 switch (bat) { 146 case DBAT0: 147 l = mfspr (DBAT0L); 148 u = mfspr (DBAT0U); 149 break; 150 case IBAT0: 151 l = mfspr (IBAT0L); 152 u = mfspr (IBAT0U); 153 break; 154 case DBAT1: 155 l = mfspr (DBAT1L); 156 u = mfspr (DBAT1U); 157 break; 158 case IBAT1: 159 l = mfspr (IBAT1L); 160 u = mfspr (IBAT1U); 161 break; 162 case DBAT2: 163 l = mfspr (DBAT2L); 164 u = mfspr (DBAT2U); 165 break; 166 case IBAT2: 167 l = mfspr (IBAT2L); 168 u = mfspr (IBAT2U); 169 break; 170 case DBAT3: 171 l = mfspr (DBAT3L); 172 u = mfspr (DBAT3U); 173 break; 174 case IBAT3: 175 l = mfspr (IBAT3L); 176 u = mfspr (IBAT3U); 177 break; 178 #ifdef CONFIG_HIGH_BATS 179 case DBAT4: 180 l = mfspr (DBAT4L); 181 u = mfspr (DBAT4U); 182 break; 183 case IBAT4: 184 l = mfspr (IBAT4L); 185 u = mfspr (IBAT4U); 186 break; 187 case DBAT5: 188 l = mfspr (DBAT5L); 189 u = mfspr (DBAT5U); 190 break; 191 case IBAT5: 192 l = mfspr (IBAT5L); 193 u = mfspr (IBAT5U); 194 break; 195 case DBAT6: 196 l = mfspr (DBAT6L); 197 u = mfspr (DBAT6U); 198 break; 199 case IBAT6: 200 l = mfspr (IBAT6L); 201 u = mfspr (IBAT6U); 202 break; 203 case DBAT7: 204 l = mfspr (DBAT7L); 205 u = mfspr (DBAT7U); 206 break; 207 case IBAT7: 208 l = mfspr (IBAT7L); 209 u = mfspr (IBAT7U); 210 break; 211 #endif 212 default: 213 return (-1); 214 } 215 216 *upper = u; 217 *lower = l; 218 219 return (0); 220 } 221 222 void print_bats(void) 223 { 224 printf("BAT registers:\n"); 225 226 printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L)); 227 printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U)); 228 printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L)); 229 printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U)); 230 printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L)); 231 printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U)); 232 printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L)); 233 printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U)); 234 printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L)); 235 printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U)); 236 printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L)); 237 printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U)); 238 printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L)); 239 printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U)); 240 printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L)); 241 printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U)); 242 243 #ifdef CONFIG_HIGH_BATS 244 printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L)); 245 printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U)); 246 printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L)); 247 printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U)); 248 printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L)); 249 printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U)); 250 printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L)); 251 printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U)); 252 printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L)); 253 printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U)); 254 printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L)); 255 printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U)); 256 printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L)); 257 printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U)); 258 printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L)); 259 printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U)); 260 #endif 261 } 262