1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a47a12beSStefan Roese /* 3a47a12beSStefan Roese * (C) Copyright 2002 4a47a12beSStefan Roese * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese 7a47a12beSStefan Roese #include <common.h> 8a47a12beSStefan Roese #include <asm/processor.h> 9a47a12beSStefan Roese #include <asm/mmu.h> 10a47a12beSStefan Roese #include <asm/io.h> 118a33201dSWolfgang Denk #include <linux/compiler.h> 12a47a12beSStefan Roese 13a47a12beSStefan Roese #ifdef CONFIG_ADDR_MAP 14a47a12beSStefan Roese #include <addr_map.h> 15a47a12beSStefan Roese #endif 16a47a12beSStefan Roese 17a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 18a47a12beSStefan Roese 19a47a12beSStefan Roese int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) 20a47a12beSStefan Roese { 218a33201dSWolfgang Denk __maybe_unused int batn = -1; 22a47a12beSStefan Roese 23a47a12beSStefan Roese sync(); 24a47a12beSStefan Roese 25a47a12beSStefan Roese switch (bat) { 26a47a12beSStefan Roese case DBAT0: 27a47a12beSStefan Roese mtspr (DBAT0L, lower); 28a47a12beSStefan Roese mtspr (DBAT0U, upper); 29a47a12beSStefan Roese batn = 0; 30a47a12beSStefan Roese break; 31a47a12beSStefan Roese case IBAT0: 32a47a12beSStefan Roese mtspr (IBAT0L, lower); 33a47a12beSStefan Roese mtspr (IBAT0U, upper); 34a47a12beSStefan Roese break; 35a47a12beSStefan Roese case DBAT1: 36a47a12beSStefan Roese mtspr (DBAT1L, lower); 37a47a12beSStefan Roese mtspr (DBAT1U, upper); 38a47a12beSStefan Roese batn = 1; 39a47a12beSStefan Roese break; 40a47a12beSStefan Roese case IBAT1: 41a47a12beSStefan Roese mtspr (IBAT1L, lower); 42a47a12beSStefan Roese mtspr (IBAT1U, upper); 43a47a12beSStefan Roese break; 44a47a12beSStefan Roese case DBAT2: 45a47a12beSStefan Roese mtspr (DBAT2L, lower); 46a47a12beSStefan Roese mtspr (DBAT2U, upper); 47a47a12beSStefan Roese batn = 2; 48a47a12beSStefan Roese break; 49a47a12beSStefan Roese case IBAT2: 50a47a12beSStefan Roese mtspr (IBAT2L, lower); 51a47a12beSStefan Roese mtspr (IBAT2U, upper); 52a47a12beSStefan Roese break; 53a47a12beSStefan Roese case DBAT3: 54a47a12beSStefan Roese mtspr (DBAT3L, lower); 55a47a12beSStefan Roese mtspr (DBAT3U, upper); 56a47a12beSStefan Roese batn = 3; 57a47a12beSStefan Roese break; 58a47a12beSStefan Roese case IBAT3: 59a47a12beSStefan Roese mtspr (IBAT3L, lower); 60a47a12beSStefan Roese mtspr (IBAT3U, upper); 61a47a12beSStefan Roese break; 62a47a12beSStefan Roese #ifdef CONFIG_HIGH_BATS 63a47a12beSStefan Roese case DBAT4: 64a47a12beSStefan Roese mtspr (DBAT4L, lower); 65a47a12beSStefan Roese mtspr (DBAT4U, upper); 66a47a12beSStefan Roese batn = 4; 67a47a12beSStefan Roese break; 68a47a12beSStefan Roese case IBAT4: 69a47a12beSStefan Roese mtspr (IBAT4L, lower); 70a47a12beSStefan Roese mtspr (IBAT4U, upper); 71a47a12beSStefan Roese break; 72a47a12beSStefan Roese case DBAT5: 73a47a12beSStefan Roese mtspr (DBAT5L, lower); 74a47a12beSStefan Roese mtspr (DBAT5U, upper); 75a47a12beSStefan Roese batn = 5; 76a47a12beSStefan Roese break; 77a47a12beSStefan Roese case IBAT5: 78a47a12beSStefan Roese mtspr (IBAT5L, lower); 79a47a12beSStefan Roese mtspr (IBAT5U, upper); 80a47a12beSStefan Roese break; 81a47a12beSStefan Roese case DBAT6: 82a47a12beSStefan Roese mtspr (DBAT6L, lower); 83a47a12beSStefan Roese mtspr (DBAT6U, upper); 84a47a12beSStefan Roese batn = 6; 85a47a12beSStefan Roese break; 86a47a12beSStefan Roese case IBAT6: 87a47a12beSStefan Roese mtspr (IBAT6L, lower); 88a47a12beSStefan Roese mtspr (IBAT6U, upper); 89a47a12beSStefan Roese break; 90a47a12beSStefan Roese case DBAT7: 91a47a12beSStefan Roese mtspr (DBAT7L, lower); 92a47a12beSStefan Roese mtspr (DBAT7U, upper); 93a47a12beSStefan Roese batn = 7; 94a47a12beSStefan Roese break; 95a47a12beSStefan Roese case IBAT7: 96a47a12beSStefan Roese mtspr (IBAT7L, lower); 97a47a12beSStefan Roese mtspr (IBAT7U, upper); 98a47a12beSStefan Roese break; 99a47a12beSStefan Roese #endif 100a47a12beSStefan Roese default: 101a47a12beSStefan Roese return (-1); 102a47a12beSStefan Roese } 103a47a12beSStefan Roese 104a47a12beSStefan Roese #ifdef CONFIG_ADDR_MAP 105a47a12beSStefan Roese if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) { 106a47a12beSStefan Roese phys_size_t size; 107a47a12beSStefan Roese if (!BATU_VALID(upper)) 108a47a12beSStefan Roese size = 0; 109a47a12beSStefan Roese else 110a47a12beSStefan Roese size = BATU_SIZE(upper); 111a47a12beSStefan Roese addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), 112a47a12beSStefan Roese size, batn); 113a47a12beSStefan Roese } 114a47a12beSStefan Roese #endif 115a47a12beSStefan Roese 116a47a12beSStefan Roese sync(); 117a47a12beSStefan Roese isync(); 118a47a12beSStefan Roese 119a47a12beSStefan Roese return (0); 120a47a12beSStefan Roese } 121a47a12beSStefan Roese 122a47a12beSStefan Roese int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) 123a47a12beSStefan Roese { 124a47a12beSStefan Roese unsigned long register u; 125a47a12beSStefan Roese unsigned long register l; 126a47a12beSStefan Roese 127a47a12beSStefan Roese switch (bat) { 128a47a12beSStefan Roese case DBAT0: 129a47a12beSStefan Roese l = mfspr (DBAT0L); 130a47a12beSStefan Roese u = mfspr (DBAT0U); 131a47a12beSStefan Roese break; 132a47a12beSStefan Roese case IBAT0: 133a47a12beSStefan Roese l = mfspr (IBAT0L); 134a47a12beSStefan Roese u = mfspr (IBAT0U); 135a47a12beSStefan Roese break; 136a47a12beSStefan Roese case DBAT1: 137a47a12beSStefan Roese l = mfspr (DBAT1L); 138a47a12beSStefan Roese u = mfspr (DBAT1U); 139a47a12beSStefan Roese break; 140a47a12beSStefan Roese case IBAT1: 141a47a12beSStefan Roese l = mfspr (IBAT1L); 142a47a12beSStefan Roese u = mfspr (IBAT1U); 143a47a12beSStefan Roese break; 144a47a12beSStefan Roese case DBAT2: 145a47a12beSStefan Roese l = mfspr (DBAT2L); 146a47a12beSStefan Roese u = mfspr (DBAT2U); 147a47a12beSStefan Roese break; 148a47a12beSStefan Roese case IBAT2: 149a47a12beSStefan Roese l = mfspr (IBAT2L); 150a47a12beSStefan Roese u = mfspr (IBAT2U); 151a47a12beSStefan Roese break; 152a47a12beSStefan Roese case DBAT3: 153a47a12beSStefan Roese l = mfspr (DBAT3L); 154a47a12beSStefan Roese u = mfspr (DBAT3U); 155a47a12beSStefan Roese break; 156a47a12beSStefan Roese case IBAT3: 157a47a12beSStefan Roese l = mfspr (IBAT3L); 158a47a12beSStefan Roese u = mfspr (IBAT3U); 159a47a12beSStefan Roese break; 160a47a12beSStefan Roese #ifdef CONFIG_HIGH_BATS 161a47a12beSStefan Roese case DBAT4: 162a47a12beSStefan Roese l = mfspr (DBAT4L); 163a47a12beSStefan Roese u = mfspr (DBAT4U); 164a47a12beSStefan Roese break; 165a47a12beSStefan Roese case IBAT4: 166a47a12beSStefan Roese l = mfspr (IBAT4L); 167a47a12beSStefan Roese u = mfspr (IBAT4U); 168a47a12beSStefan Roese break; 169a47a12beSStefan Roese case DBAT5: 170a47a12beSStefan Roese l = mfspr (DBAT5L); 171a47a12beSStefan Roese u = mfspr (DBAT5U); 172a47a12beSStefan Roese break; 173a47a12beSStefan Roese case IBAT5: 174a47a12beSStefan Roese l = mfspr (IBAT5L); 175a47a12beSStefan Roese u = mfspr (IBAT5U); 176a47a12beSStefan Roese break; 177a47a12beSStefan Roese case DBAT6: 178a47a12beSStefan Roese l = mfspr (DBAT6L); 179a47a12beSStefan Roese u = mfspr (DBAT6U); 180a47a12beSStefan Roese break; 181a47a12beSStefan Roese case IBAT6: 182a47a12beSStefan Roese l = mfspr (IBAT6L); 183a47a12beSStefan Roese u = mfspr (IBAT6U); 184a47a12beSStefan Roese break; 185a47a12beSStefan Roese case DBAT7: 186a47a12beSStefan Roese l = mfspr (DBAT7L); 187a47a12beSStefan Roese u = mfspr (DBAT7U); 188a47a12beSStefan Roese break; 189a47a12beSStefan Roese case IBAT7: 190a47a12beSStefan Roese l = mfspr (IBAT7L); 191a47a12beSStefan Roese u = mfspr (IBAT7U); 192a47a12beSStefan Roese break; 193a47a12beSStefan Roese #endif 194a47a12beSStefan Roese default: 195a47a12beSStefan Roese return (-1); 196a47a12beSStefan Roese } 197a47a12beSStefan Roese 198a47a12beSStefan Roese *upper = u; 199a47a12beSStefan Roese *lower = l; 200a47a12beSStefan Roese 201a47a12beSStefan Roese return (0); 202a47a12beSStefan Roese } 203a47a12beSStefan Roese 204a47a12beSStefan Roese void print_bats(void) 205a47a12beSStefan Roese { 206a47a12beSStefan Roese printf("BAT registers:\n"); 207a47a12beSStefan Roese 208a47a12beSStefan Roese printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L)); 209a47a12beSStefan Roese printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U)); 210a47a12beSStefan Roese printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L)); 211a47a12beSStefan Roese printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U)); 212a47a12beSStefan Roese printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L)); 213a47a12beSStefan Roese printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U)); 214a47a12beSStefan Roese printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L)); 215a47a12beSStefan Roese printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U)); 216a47a12beSStefan Roese printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L)); 217a47a12beSStefan Roese printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U)); 218a47a12beSStefan Roese printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L)); 219a47a12beSStefan Roese printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U)); 220a47a12beSStefan Roese printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L)); 221a47a12beSStefan Roese printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U)); 222a47a12beSStefan Roese printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L)); 223a47a12beSStefan Roese printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U)); 224a47a12beSStefan Roese 225a47a12beSStefan Roese #ifdef CONFIG_HIGH_BATS 226a47a12beSStefan Roese printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L)); 227a47a12beSStefan Roese printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U)); 228a47a12beSStefan Roese printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L)); 229a47a12beSStefan Roese printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U)); 230a47a12beSStefan Roese printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L)); 231a47a12beSStefan Roese printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U)); 232a47a12beSStefan Roese printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L)); 233a47a12beSStefan Roese printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U)); 234a47a12beSStefan Roese printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L)); 235a47a12beSStefan Roese printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U)); 236a47a12beSStefan Roese printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L)); 237a47a12beSStefan Roese printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U)); 238a47a12beSStefan Roese printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L)); 239a47a12beSStefan Roese printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U)); 240a47a12beSStefan Roese printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L)); 241a47a12beSStefan Roese printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U)); 242a47a12beSStefan Roese #endif 243a47a12beSStefan Roese } 244