1 #ifndef __ASM_PPC_PROCESSOR_H
2 #define __ASM_PPC_PROCESSOR_H
3 
4 /*
5  * Default implementation of macro that returns current
6  * instruction pointer ("program counter").
7  */
8 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
9 
10 #include <asm/ptrace.h>
11 #include <asm/types.h>
12 
13 /* Machine State Register (MSR) Fields */
14 
15 #ifdef CONFIG_PPC64BRIDGE
16 #define MSR_SF		(1<<63)
17 #define MSR_ISF		(1<<61)
18 #endif /* CONFIG_PPC64BRIDGE */
19 #define MSR_UCLE	(1<<26)		/* User-mode cache lock enable (e500) */
20 #define MSR_VEC		(1<<25)		/* Enable AltiVec(74xx) */
21 #define MSR_SPE		(1<<25)		/* Enable SPE(e500) */
22 #define MSR_POW		(1<<18)		/* Enable Power Management */
23 #define MSR_WE		(1<<18)		/* Wait State Enable */
24 #define MSR_TGPR	(1<<17)		/* TLB Update registers in use */
25 #define MSR_CE		(1<<17)		/* Critical Interrupt Enable */
26 #define MSR_ILE		(1<<16)		/* Interrupt Little Endian */
27 #define MSR_EE		(1<<15)		/* External Interrupt Enable */
28 #define MSR_PR		(1<<14)		/* Problem State / Privilege Level */
29 #define MSR_FP		(1<<13)		/* Floating Point enable */
30 #define MSR_ME		(1<<12)		/* Machine Check Enable */
31 #define MSR_FE0		(1<<11)		/* Floating Exception mode 0 */
32 #define MSR_SE		(1<<10)		/* Single Step */
33 #define MSR_DWE		(1<<10)		/* Debug Wait Enable (4xx) */
34 #define MSR_UBLE	(1<<10)		/* BTB lock enable (e500) */
35 #define MSR_BE		(1<<9)		/* Branch Trace */
36 #define MSR_DE		(1<<9)		/* Debug Exception Enable */
37 #define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */
38 #define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */
39 #define MSR_IR		(1<<5)		/* Instruction Relocate */
40 #define MSR_IS		(1<<5)		/* Book E Instruction space */
41 #define MSR_DR		(1<<4)		/* Data Relocate */
42 #define MSR_DS		(1<<4)		/* Book E Data space */
43 #define MSR_PE		(1<<3)		/* Protection Enable */
44 #define MSR_PX		(1<<2)		/* Protection Exclusive Mode */
45 #define MSR_PMM		(1<<2)		/* Performance monitor mark bit (e500) */
46 #define MSR_RI		(1<<1)		/* Recoverable Exception */
47 #define MSR_LE		(1<<0)		/* Little Endian */
48 
49 #ifdef CONFIG_APUS_FAST_EXCEPT
50 #define MSR_		MSR_ME|MSR_IP|MSR_RI
51 #else
52 #define MSR_		MSR_ME|MSR_RI
53 #endif
54 #ifndef CONFIG_E500
55 #define MSR_KERNEL	MSR_|MSR_IR|MSR_DR
56 #else
57 #define MSR_KERNEL	MSR_ME
58 #endif
59 
60 /* Floating Point Status and Control Register (FPSCR) Fields */
61 
62 #define FPSCR_FX	0x80000000	/* FPU exception summary */
63 #define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */
64 #define FPSCR_VX	0x20000000	/* Invalid operation summary */
65 #define FPSCR_OX	0x10000000	/* Overflow exception summary */
66 #define FPSCR_UX	0x08000000	/* Underflow exception summary */
67 #define FPSCR_ZX	0x04000000	/* Zero-devide exception summary */
68 #define FPSCR_XX	0x02000000	/* Inexact exception summary */
69 #define FPSCR_VXSNAN	0x01000000	/* Invalid op for SNaN */
70 #define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
71 #define FPSCR_VXIDI	0x00400000	/* Invalid op for Inv / Inv */
72 #define FPSCR_VXZDZ	0x00200000	/* Invalid op for Zero / Zero */
73 #define FPSCR_VXIMZ	0x00100000	/* Invalid op for Inv * Zero */
74 #define FPSCR_VXVC	0x00080000	/* Invalid op for Compare */
75 #define FPSCR_FR	0x00040000	/* Fraction rounded */
76 #define FPSCR_FI	0x00020000	/* Fraction inexact */
77 #define FPSCR_FPRF	0x0001f000	/* FPU Result Flags */
78 #define FPSCR_FPCC	0x0000f000	/* FPU Condition Codes */
79 #define FPSCR_VXSOFT	0x00000400	/* Invalid op for software request */
80 #define FPSCR_VXSQRT	0x00000200	/* Invalid op for square root */
81 #define FPSCR_VXCVI	0x00000100	/* Invalid op for integer convert */
82 #define FPSCR_VE	0x00000080	/* Invalid op exception enable */
83 #define FPSCR_OE	0x00000040	/* IEEE overflow exception enable */
84 #define FPSCR_UE	0x00000020	/* IEEE underflow exception enable */
85 #define FPSCR_ZE	0x00000010	/* IEEE zero divide exception enable */
86 #define FPSCR_XE	0x00000008	/* FP inexact exception enable */
87 #define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
88 #define FPSCR_RN	0x00000003	/* FPU rounding control */
89 
90 /* Special Purpose Registers (SPRNs)*/
91 
92 /* PPC440 Architecture is BOOK-E */
93 #ifdef CONFIG_440
94 #define CONFIG_BOOKE
95 #endif
96 
97 #define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
98 #ifdef CONFIG_BOOKE
99 #define SPRN_CCR1	0x378	/* Core Configuration Register for 440 only */
100 #endif
101 #define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
102 #define SPRN_CTR	0x009	/* Count Register */
103 #define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
104 #ifndef CONFIG_BOOKE
105 #define SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
106 #define SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
107 #else
108 #define SPRN_DAC1	0x13C	/* Book E Data Address Compare 1 */
109 #define SPRN_DAC2	0x13D	/* Book E Data Address Compare 2 */
110 #endif	/* CONFIG_BOOKE */
111 #define SPRN_DAR	0x013	/* Data Address Register */
112 #define SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
113 #define SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
114 #define SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
115 #define SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
116 #define SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
117 #define SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
118 #define SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
119 #define SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
120 #define SPRN_DBAT4L	0x239	/* Data BAT 4 Lower Register */
121 #define SPRN_DBAT4U	0x238	/* Data BAT 4 Upper Register */
122 #define SPRN_DBAT5L	0x23B	/* Data BAT 5 Lower Register */
123 #define SPRN_DBAT5U	0x23A	/* Data BAT 5 Upper Register */
124 #define SPRN_DBAT6L	0x23D	/* Data BAT 6 Lower Register */
125 #define SPRN_DBAT6U	0x23C	/* Data BAT 6 Upper Register */
126 #define SPRN_DBAT7L	0x23F	/* Data BAT 7 Lower Register */
127 #define SPRN_DBAT7U	0x23E	/* Data BAT 7 Lower Register */
128 #define SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
129 #define   DBCR_EDM	0x80000000
130 #define   DBCR_IDM	0x40000000
131 #define   DBCR_RST(x)	(((x) & 0x3) << 28)
132 #define     DBCR_RST_NONE		0
133 #define     DBCR_RST_CORE		1
134 #define     DBCR_RST_CHIP		2
135 #define     DBCR_RST_SYSTEM		3
136 #define   DBCR_IC	0x08000000	/* Instruction Completion Debug Evnt */
137 #define   DBCR_BT	0x04000000	/* Branch Taken Debug Event */
138 #define   DBCR_EDE	0x02000000	/* Exception Debug Event */
139 #define   DBCR_TDE	0x01000000	/* TRAP Debug Event */
140 #define   DBCR_FER	0x00F80000	/* First Events Remaining Mask */
141 #define   DBCR_FT	0x00040000	/* Freeze Timers on Debug Event */
142 #define   DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */
143 #define   DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */
144 #define   DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */
145 #define   DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */
146 #define   DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */
147 #define     DAC_BYTE	0
148 #define     DAC_HALF	1
149 #define     DAC_WORD	2
150 #define     DAC_QUAD	3
151 #define   DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */
152 #define   DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */
153 #define   DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */
154 #define   DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */
155 #define   DBCR_SED	0x00000020	/* Second Exception Debug Event */
156 #define   DBCR_STD	0x00000010	/* Second Trap Debug Event */
157 #define   DBCR_SIA	0x00000008	/* Second IAC Enable */
158 #define   DBCR_SDA	0x00000004	/* Second DAC Enable */
159 #define   DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */
160 #define   DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */
161 #ifndef CONFIG_BOOKE
162 #define SPRN_DBCR0	0x3F2		/* Debug Control Register 0 */
163 #else
164 #define SPRN_DBCR0	0x134		/* Book E Debug Control Register 0 */
165 #endif /* CONFIG_BOOKE */
166 #ifndef CONFIG_BOOKE
167 #define SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */
168 #define SPRN_DBSR	0x3F0	/* Debug Status Register */
169 #else
170 #define SPRN_DBCR1	0x135		/* Book E Debug Control Register 1 */
171 #ifdef CONFIG_BOOKE
172 #define	SPRN_DBDR	0x3f3		/* Debug Data Register */
173 #endif
174 #define SPRN_DBSR	0x130		/* Book E Debug Status Register */
175 #define   DBSR_IC	    0x08000000	/* Book E Instruction Completion  */
176 #define   DBSR_TIE	    0x01000000	/* Book E Trap Instruction Event */
177 #endif /* CONFIG_BOOKE */
178 #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
179 #define   DCCR_NOCACHE		0	/* Noncacheable */
180 #define   DCCR_CACHE		1	/* Cacheable */
181 #ifndef CONFIG_BOOKE
182 #define	SPRN_DCDBTRL	0x39c	/* Data Cache Debug Tag Register Low */
183 #define	SPRN_DCDBTRH	0x39d	/* Data Cache Debug Tag Register High */
184 #endif
185 #define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
186 #define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
187 #define   DCWR_COPY		0	/* Copy-back */
188 #define   DCWR_WRITE		1	/* Write-through */
189 #ifndef CONFIG_BOOKE
190 #define SPRN_DEAR	0x3D5	/* Data Error Address Register */
191 #else
192 #define SPRN_DEAR	0x03D	/* Book E Data Error Address Register */
193 #endif /* CONFIG_BOOKE */
194 #define SPRN_DEC	0x016	/* Decrement Register */
195 #define SPRN_DMISS	0x3D0	/* Data TLB Miss Register */
196 #ifdef CONFIG_BOOKE
197 #define	SPRN_DNV0	0x390	/* Data Cache Normal Victim 0 */
198 #define	SPRN_DNV1	0x391	/* Data Cache Normal Victim 1 */
199 #define	SPRN_DNV2	0x392	/* Data Cache Normal Victim 2 */
200 #define	SPRN_DNV3	0x393	/* Data Cache Normal Victim 3 */
201 #endif
202 #define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
203 #ifdef CONFIG_BOOKE
204 #define	SPRN_DTV0	0x394	/* Data Cache Transient Victim 0 */
205 #define	SPRN_DTV1	0x395	/* Data Cache Transient Victim 1 */
206 #define	SPRN_DTV2	0x396	/* Data Cache Transient Victim 2 */
207 #define	SPRN_DTV3	0x397	/* Data Cache Transient Victim 3 */
208 #define	SPRN_DVLIM	0x398	/* Data Cache Victim Limit */
209 #endif
210 #define SPRN_EAR	0x11A	/* External Address Register */
211 #ifndef CONFIG_BOOKE
212 #define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
213 #else
214 #define SPRN_ESR	0x03E		/* Book E Exception Syndrome Register */
215 #endif /* CONFIG_BOOKE */
216 #define   ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
217 #define   ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
218 #define   ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
219 #define   ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
220 #define   ESR_PIL	0x08000000	/* Program Exception - Illegal */
221 #define   ESR_PPR	0x04000000	/* Program Exception - Priveleged */
222 #define   ESR_PTR	0x02000000	/* Program Exception - Trap */
223 #define   ESR_DST	0x00800000	/* Storage Exception - Data miss */
224 #define   ESR_DIZ	0x00400000	/* Storage Exception - Zone fault */
225 #define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */
226 #define SPRN_HASH1	0x3D2	/* Primary Hash Address Register */
227 #define SPRN_HASH2	0x3D3	/* Secondary Hash Address Resgister */
228 #define SPRN_HID0	0x3F0	/* Hardware Implementation Register 0 */
229 
230 #define HID0_ICE_SHIFT		15
231 #define HID0_DCE_SHIFT		14
232 #define HID0_DLOCK_SHIFT	12
233 
234 #define   HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
235 #define   HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
236 #define   HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
237 #define   HID0_SBCLK	(1<<27)
238 #define   HID0_EICE	(1<<26)
239 #define   HID0_ECLK	(1<<25)
240 #define   HID0_PAR	(1<<24)
241 #define   HID0_DOZE	(1<<23)
242 #define   HID0_NAP	(1<<22)
243 #define   HID0_SLEEP	(1<<21)
244 #define   HID0_DPM	(1<<20)
245 #define   HID0_ICE	(1<<HID0_ICE_SHIFT)	/* Instruction Cache Enable */
246 #define   HID0_DCE	(1<<HID0_DCE_SHIFT)	/* Data Cache Enable */
247 #define   HID0_TBEN	(1<<14)		/* Time Base Enable */
248 #define   HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */
249 #define   HID0_DLOCK	(1<<HID0_DLOCK_SHIFT)	/* Data Cache Lock */
250 #define   HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */
251 #define   HID0_DCFI	(1<<10)		/* Data Cache Flash Invalidate */
252 #define   HID0_DCI	HID0_DCFI
253 #define   HID0_SPD	(1<<9)		/* Speculative disable */
254 #define   HID0_ENMAS7	(1<<7)		/* Enable MAS7 Update for 36-bit phys */
255 #define   HID0_SGE	(1<<7)		/* Store Gathering Enable */
256 #define   HID0_SIED	HID_SGE		/* Serial Instr. Execution [Disable] */
257 #define   HID0_DCFA	(1<<6)		/* Data Cache Flush Assist */
258 #define   HID0_BTIC	(1<<5)		/* Branch Target Instruction Cache Enable */
259 #define   HID0_ABE	(1<<3)		/* Address Broadcast Enable */
260 #define   HID0_BHTE	(1<<2)		/* Branch History Table Enable */
261 #define   HID0_BTCD	(1<<1)		/* Branch target cache disable */
262 #define SPRN_HID1	0x3F1	/* Hardware Implementation Register 1 */
263 #define	  HID1_RFXE	(1<<17)		/* Read Fault Exception Enable */
264 #define	  HID1_ASTME	(1<<13)		/* Address bus streaming mode */
265 #define	  HID1_ABE	(1<<12)		/* Address broadcast enable */
266 #define	  HID1_MBDD	(1<<6)		/* optimized sync instruction */
267 #define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
268 #ifndef CONFIG_BOOKE
269 #define SPRN_IAC1	0x3F4	/* Instruction Address Compare 1 */
270 #define SPRN_IAC2	0x3F5	/* Instruction Address Compare 2 */
271 #else
272 #define SPRN_IAC1	0x138	/* Book E Instruction Address Compare 1 */
273 #define SPRN_IAC2	0x139	/* Book E Instruction Address Compare 2 */
274 #endif /* CONFIG_BOOKE */
275 #define SPRN_IBAT0L	0x211	/* Instruction BAT 0 Lower Register */
276 #define SPRN_IBAT0U	0x210	/* Instruction BAT 0 Upper Register */
277 #define SPRN_IBAT1L	0x213	/* Instruction BAT 1 Lower Register */
278 #define SPRN_IBAT1U	0x212	/* Instruction BAT 1 Upper Register */
279 #define SPRN_IBAT2L	0x215	/* Instruction BAT 2 Lower Register */
280 #define SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */
281 #define SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */
282 #define SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */
283 #define SPRN_IBAT4L	0x231	/* Instruction BAT 4 Lower Register */
284 #define SPRN_IBAT4U	0x230	/* Instruction BAT 4 Upper Register */
285 #define SPRN_IBAT5L	0x233	/* Instruction BAT 5 Lower Register */
286 #define SPRN_IBAT5U	0x232	/* Instruction BAT 5 Upper Register */
287 #define SPRN_IBAT6L	0x235	/* Instruction BAT 6 Lower Register */
288 #define SPRN_IBAT6U	0x234	/* Instruction BAT 6 Upper Register */
289 #define SPRN_IBAT7L	0x237	/* Instruction BAT 7 Lower Register */
290 #define SPRN_IBAT7U	0x236	/* Instruction BAT 7 Upper Register */
291 #define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
292 #define   ICCR_NOCACHE		0	/* Noncacheable */
293 #define   ICCR_CACHE		1	/* Cacheable */
294 #define SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */
295 #ifdef CONFIG_BOOKE
296 #define SPRN_ICDBTRL	0x39e	/* instruction cache debug tag register low */
297 #define	SPRN_ICDBTRH	0x39f	/* instruction cache debug tag register high */
298 #endif
299 #define SPRN_ICMP	0x3D5	/* Instruction TLB Compare Register */
300 #define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
301 #define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
302 #define SPRN_IMMR	0x27E	/* Internal Memory Map Register */
303 #ifdef CONFIG_BOOKE
304 #define	SPRN_INV0	0x370	/* Instruction Cache Normal Victim 0 */
305 #define	SPRN_INV1	0x371	/* Instruction Cache Normal Victim 1 */
306 #define	SPRN_INV2	0x372	/* Instruction Cache Normal Victim 2 */
307 #define	SPRN_INV3	0x373	/* Instruction Cache Normal Victim 3 */
308 #define	SPRN_ITV0	0x374	/* Instruction Cache Transient Victim 0 */
309 #define	SPRN_ITV1	0x375	/* Instruction Cache Transient Victim 1 */
310 #define	SPRN_ITV2	0x376	/* Instruction Cache Transient Victim 2 */
311 #define	SPRN_ITV3	0x377	/* Instruction Cache Transient Victim 3 */
312 #define	SPRN_IVLIM	0x399	/* Instruction Cache Victim Limit */
313 #endif
314 #define SPRN_LDSTCR	0x3F8	/* Load/Store Control Register */
315 #define SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */
316 #define SPRN_LR		0x008	/* Link Register */
317 #define SPRN_MBAR	0x137	/* System memory base address */
318 #define SPRN_MMCR0	0x3B8	/* Monitor Mode Control Register 0 */
319 #define SPRN_MMCR1	0x3BC	/* Monitor Mode Control Register 1 */
320 #ifdef CONFIG_BOOKE
321 #define	SPRN_MMUCR	0x3b2	/* MMU Control Register */
322 #endif
323 #define SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */
324 #define SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */
325 #define SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */
326 #define SPRN_PBU2	0x3FF	/* Protection Bound Upper 2 */
327 #ifndef CONFIG_BOOKE
328 #define SPRN_PID	0x3B1	/* Process ID */
329 #define SPRN_PIR	0x3FF	/* Processor Identification Register */
330 #else
331 #define SPRN_PID	0x030	/* Book E Process ID */
332 #define SPRN_PIR	0x11E	/* Book E Processor Identification Register */
333 #endif /* CONFIG_BOOKE */
334 #define SPRN_PIT	0x3DB	/* Programmable Interval Timer */
335 #define SPRN_PMC1	0x3B9	/* Performance Counter Register 1 */
336 #define SPRN_PMC2	0x3BA	/* Performance Counter Register 2 */
337 #define SPRN_PMC3	0x3BD	/* Performance Counter Register 3 */
338 #define SPRN_PMC4	0x3BE	/* Performance Counter Register 4 */
339 #define SPRN_PVR	0x11F	/* Processor Version Register */
340 #define SPRN_RPA	0x3D6	/* Required Physical Address Register */
341 #ifdef CONFIG_BOOKE
342 #define	SPRN_RSTCFG	0x39b	/* Reset Configuration */
343 #endif
344 #define SPRN_SDA	0x3BF	/* Sampled Data Address Register */
345 #define SPRN_SDR1	0x019	/* MMU Hash Base Register */
346 #define SPRN_SGR	0x3B9	/* Storage Guarded Register */
347 #define   SGR_NORMAL		0
348 #define   SGR_GUARDED		1
349 #define SPRN_SIA	0x3BB	/* Sampled Instruction Address Register */
350 #define SPRN_SPRG0	0x110	/* Special Purpose Register General 0 */
351 #define SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */
352 #define SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */
353 #define SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
354 #define SPRN_SPRG4	0x114	/* Special Purpose Register General 4 */
355 #define SPRN_SPRG5	0x115	/* Special Purpose Register General 5 */
356 #define SPRN_SPRG6	0x116	/* Special Purpose Register General 6 */
357 #define SPRN_SPRG7	0x117	/* Special Purpose Register General 7 */
358 #define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
359 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
360 #define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
361 #define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
362 
363 #ifdef CONFIG_BOOKE
364 #define SPRN_SVR	0x3FF	/* System Version Register */
365 #else
366 #define SPRN_SVR	0x11E	/* System Version Register */
367 #endif
368 #define SPRN_TBHI	0x3DC	/* Time Base High */
369 #define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
370 #define SPRN_TBLO	0x3DD	/* Time Base Low */
371 #define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
372 #define SPRN_TBRL	0x10C	/* Time Base Read Lower Register */
373 #define SPRN_TBRU	0x10D	/* Time Base Read Upper Register */
374 #define SPRN_TBWL	0x11C	/* Time Base Write Lower Register */
375 #define SPRN_TBWU	0x11D	/* Time Base Write Upper Register */
376 #ifndef CONFIG_BOOKE
377 #define SPRN_TCR	0x3DA	/* Timer Control Register */
378 #else
379 #define SPRN_TCR	0x154	/* Book E Timer Control Register */
380 #endif /* CONFIG_BOOKE */
381 #ifdef CONFIG_E500MC
382 #define  TCR_WP(x)		(((64-x)&0x3)<<30)| \
383 				(((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
384 #else
385 #define   TCR_WP(x)		(((x)&0x3)<<30)	/* WDT Period */
386 #define     WP_2_17		0		/* 2^17 clocks */
387 #define     WP_2_21		1		/* 2^21 clocks */
388 #define     WP_2_25		2		/* 2^25 clocks */
389 #define     WP_2_29		3		/* 2^29 clocks */
390 #endif /* CONFIG_E500 */
391 #define   TCR_WRC(x)		(((x)&0x3)<<28)	/* WDT Reset Control */
392 #define     WRC_NONE		0		/* No reset will occur */
393 #define     WRC_CORE		1		/* Core reset will occur */
394 #define     WRC_CHIP		2		/* Chip reset will occur */
395 #define     WRC_SYSTEM		3		/* System reset will occur */
396 #define   TCR_WIE		0x08000000	/* WDT Interrupt Enable */
397 #define   TCR_PIE		0x04000000	/* PIT Interrupt Enable */
398 #define   TCR_FP(x)		(((x)&0x3)<<24)	/* FIT Period */
399 #define     FP_2_9		0		/* 2^9 clocks */
400 #define     FP_2_13		1		/* 2^13 clocks */
401 #define     FP_2_17		2		/* 2^17 clocks */
402 #define     FP_2_21		3		/* 2^21 clocks */
403 #define   TCR_FIE		0x00800000	/* FIT Interrupt Enable */
404 #define   TCR_ARE		0x00400000	/* Auto Reload Enable */
405 #define SPRN_THRM1	0x3FC	/* Thermal Management Register 1 */
406 #define   THRM1_TIN		(1<<0)
407 #define   THRM1_TIV		(1<<1)
408 #define   THRM1_THRES		(0x7f<<2)
409 #define   THRM1_TID		(1<<29)
410 #define   THRM1_TIE		(1<<30)
411 #define   THRM1_V		(1<<31)
412 #define SPRN_THRM2	0x3FD	/* Thermal Management Register 2 */
413 #define SPRN_THRM3	0x3FE	/* Thermal Management Register 3 */
414 #define   THRM3_E		(1<<31)
415 #define SPRN_TLBMISS	0x3D4	/* 980 7450 TLB Miss Register */
416 #ifndef CONFIG_BOOKE
417 #define SPRN_TSR	0x3D8	/* Timer Status Register */
418 #else
419 #define SPRN_TSR	0x150	/* Book E Timer Status Register */
420 #endif /* CONFIG_BOOKE */
421 #define   TSR_ENW		0x80000000	/* Enable Next Watchdog */
422 #define   TSR_WIS		0x40000000	/* WDT Interrupt Status */
423 #define   TSR_WRS(x)		(((x)&0x3)<<28)	/* WDT Reset Status */
424 #define     WRS_NONE		0		/* No WDT reset occurred */
425 #define     WRS_CORE		1		/* WDT forced core reset */
426 #define     WRS_CHIP		2		/* WDT forced chip reset */
427 #define     WRS_SYSTEM		3		/* WDT forced system reset */
428 #define   TSR_PIS		0x08000000	/* PIT Interrupt Status */
429 #define   TSR_FIS		0x04000000	/* FIT Interrupt Status */
430 #define SPRN_UMMCR0	0x3A8	/* User Monitor Mode Control Register 0 */
431 #define SPRN_UMMCR1	0x3AC	/* User Monitor Mode Control Register 0 */
432 #define SPRN_UPMC1	0x3A9	/* User Performance Counter Register 1 */
433 #define SPRN_UPMC2	0x3AA	/* User Performance Counter Register 2 */
434 #define SPRN_UPMC3	0x3AD	/* User Performance Counter Register 3 */
435 #define SPRN_UPMC4	0x3AE	/* User Performance Counter Register 4 */
436 #define SPRN_USIA	0x3AB	/* User Sampled Instruction Address Register */
437 #define SPRN_XER	0x001	/* Fixed Point Exception Register */
438 #define SPRN_ZPR	0x3B0	/* Zone Protection Register */
439 
440 /* Book E definitions */
441 #define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */
442 #define SPRN_CSRR0	0x03A	/* Critical SRR0 */
443 #define SPRN_CSRR1	0x03B	/* Critical SRR0 */
444 #define SPRN_IVPR	0x03F	/* Interrupt Vector Prefix Register */
445 #define SPRN_USPRG0	0x100	/* User Special Purpose Register General 0 */
446 #define SPRN_SPRG4R	0x104	/* Special Purpose Register General 4 Read */
447 #define SPRN_SPRG5R	0x105	/* Special Purpose Register General 5 Read */
448 #define SPRN_SPRG6R	0x106	/* Special Purpose Register General 6 Read */
449 #define SPRN_SPRG7R	0x107	/* Special Purpose Register General 7 Read */
450 #define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
451 #define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
452 #define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
453 #define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
454 #define SPRN_DBCR2	0x136	/* Debug Control Register 2 */
455 #define SPRN_IAC3	0x13A	/* Instruction Address Compare 3 */
456 #define SPRN_IAC4	0x13B	/* Instruction Address Compare 4 */
457 #define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
458 #define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
459 #define SPRN_IVOR0	0x190	/* Interrupt Vector Offset Register 0 */
460 #define SPRN_IVOR1	0x191	/* Interrupt Vector Offset Register 1 */
461 #define SPRN_IVOR2	0x192	/* Interrupt Vector Offset Register 2 */
462 #define SPRN_IVOR3	0x193	/* Interrupt Vector Offset Register 3 */
463 #define SPRN_IVOR4	0x194	/* Interrupt Vector Offset Register 4 */
464 #define SPRN_IVOR5	0x195	/* Interrupt Vector Offset Register 5 */
465 #define SPRN_IVOR6	0x196	/* Interrupt Vector Offset Register 6 */
466 #define SPRN_IVOR7	0x197	/* Interrupt Vector Offset Register 7 */
467 #define SPRN_IVOR8	0x198	/* Interrupt Vector Offset Register 8 */
468 #define SPRN_IVOR9	0x199	/* Interrupt Vector Offset Register 9 */
469 #define SPRN_IVOR10	0x19a	/* Interrupt Vector Offset Register 10 */
470 #define SPRN_IVOR11	0x19b	/* Interrupt Vector Offset Register 11 */
471 #define SPRN_IVOR12	0x19c	/* Interrupt Vector Offset Register 12 */
472 #define SPRN_IVOR13	0x19d	/* Interrupt Vector Offset Register 13 */
473 #define SPRN_IVOR14	0x19e	/* Interrupt Vector Offset Register 14 */
474 #define SPRN_IVOR15	0x19f	/* Interrupt Vector Offset Register 15 */
475 #define SPRN_IVOR38	0x1b0	/* Interrupt Vector Offset Register 38 */
476 #define SPRN_IVOR39	0x1b1	/* Interrupt Vector Offset Register 39 */
477 #define SPRN_IVOR40	0x1b2	/* Interrupt Vector Offset Register 40 */
478 #define SPRN_IVOR41	0x1b3	/* Interrupt Vector Offset Register 41 */
479 #define SPRN_GIVOR2	0x1b8	/* Guest Interrupt Vector Offset Register 2 */
480 #define SPRN_GIVOR3	0x1b9	/* Guest Interrupt Vector Offset Register 3 */
481 #define SPRN_GIVOR4	0x1ba	/* Guest Interrupt Vector Offset Register 4 */
482 #define SPRN_GIVOR8	0x1bb	/* Guest Interrupt Vector Offset Register 8 */
483 #define SPRN_GIVOR13	0x1bc	/* Guest Interrupt Vector Offset Register 13 */
484 #define SPRN_GIVOR14	0x1bd	/* Guest Interrupt Vector Offset Register 14 */
485 
486 /* e500 definitions */
487 #define SPRN_L1CFG0	0x203	/* L1 Cache Configuration Register 0 */
488 #define SPRN_L1CFG1	0x204	/* L1 Cache Configuration Register 1 */
489 #define SPRN_L2CFG0	0x207	/* L2 Cache Configuration Register 0 */
490 #define SPRN_L1CSR0	0x3f2	/* L1 Data Cache Control and Status Register 0 */
491 #define   L1CSR0_CPE		0x00010000	/* Data Cache Parity Enable */
492 #define   L1CSR0_CUL		0x00000400	/* (D-)Cache Unable to Lock */
493 #define   L1CSR0_DCLFR		0x00000100	/* D-Cache Lock Flash Reset */
494 #define   L1CSR0_DCFI		0x00000002	/* Data Cache Flash Invalidate */
495 #define   L1CSR0_DCE		0x00000001	/* Data Cache Enable */
496 #define SPRN_L1CSR1	0x3f3	/* L1 Instruction Cache Control and Status Register 1 */
497 #define   L1CSR1_CPE		0x00010000	/* Instruction Cache Parity Enable */
498 #define   L1CSR1_ICUL		0x00000400	/* I-Cache Unable to Lock */
499 #define   L1CSR1_ICLFR		0x00000100	/* I-Cache Lock Flash Reset */
500 #define   L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
501 #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
502 #define SPRN_L1CSR2	0x25e	/* L1 Data Cache Control and Status Register 2 */
503 #define   L1CSR2_DCWS		0x40000000	/* Data Cache Write Shadow */
504 #define SPRN_L2CSR0	0x3f9	/* L2 Data Cache Control and Status Register 0 */
505 #define   L2CSR0_L2E		0x80000000	/* L2 Cache Enable */
506 #define   L2CSR0_L2PE		0x40000000	/* L2 Cache Parity/ECC Enable */
507 #define   L2CSR0_L2WP		0x1c000000	/* L2 I/D Way Partioning */
508 #define   L2CSR0_L2CM		0x03000000	/* L2 Cache Coherency Mode */
509 #define   L2CSR0_L2FI		0x00200000	/* L2 Cache Flash Invalidate */
510 #define   L2CSR0_L2IO		0x00100000	/* L2 Cache Instruction Only */
511 #define   L2CSR0_L2DO		0x00010000	/* L2 Cache Data Only */
512 #define   L2CSR0_L2REP		0x00003000	/* L2 Line Replacement Algo */
513 
514 /* e6500 */
515 #define   L2CSR0_L2REP_SPLRUAGE	0x00000000	/* L2REP Streaming PLRU with Aging */
516 #define   L2CSR0_L2REP_FIFO	0x00001000	/* L2REP FIFO */
517 #define   L2CSR0_L2REP_SPLRU	0x00002000	/* L2REP Streaming PLRU */
518 #define   L2CSR0_L2REP_PLRU	0x00003000	/* L2REP PLRU */
519 
520 #define   L2CSR0_L2REP_MODE	L2CSR0_L2REP_SPLRUAGE
521 
522 #define   L2CSR0_L2FL		0x00000800	/* L2 Cache Flush */
523 #define   L2CSR0_L2LFC		0x00000400	/* L2 Cache Lock Flash Clear */
524 #define   L2CSR0_L2LOA		0x00000080	/* L2 Cache Lock Overflow Allocate */
525 #define   L2CSR0_L2LO		0x00000020	/* L2 Cache Lock Overflow */
526 #define SPRN_L2CSR1	0x3fa	/* L2 Data Cache Control and Status Register 1 */
527 
528 #define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
529 #define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
530 #define   TLBnCFG_NENTRY_MASK	0x00000fff
531 #define SPRN_TLB0PS	0x158	/* TLB 0 Page Size Register */
532 #define SPRN_TLB1PS	0x159	/* TLB 1 Page Size Register */
533 #define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
534 #define SPRN_MMUCFG	0x3F7	/* MMU Configuration Register */
535 #define MMUCFG_MAVN	0x00000003	/* MMU Architecture Version Number */
536 #define MMUCFG_MAVN_V1	0x00000000	/* v1.0 */
537 #define MMUCFG_MAVN_V2	0x00000001	/* v2.0 */
538 #define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
539 #define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
540 #define SPRN_MAS2	0x272	/* MMU Assist Register 2 */
541 #define SPRN_MAS3	0x273	/* MMU Assist Register 3 */
542 #define SPRN_MAS4	0x274	/* MMU Assist Register 4 */
543 #define SPRN_MAS5	0x275	/* MMU Assist Register 5 */
544 #define SPRN_MAS6	0x276	/* MMU Assist Register 6 */
545 #define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */
546 #define SPRN_MAS8	0x155	/* MMU Assist Register 8 */
547 
548 #define SPRN_IVOR32	0x210	/* Interrupt Vector Offset Register 32 */
549 #define SPRN_IVOR33	0x211	/* Interrupt Vector Offset Register 33 */
550 #define SPRN_IVOR34	0x212	/* Interrupt Vector Offset Register 34 */
551 #define SPRN_IVOR35	0x213	/* Interrupt Vector Offset Register 35 */
552 #define SPRN_IVOR36	0x214	/* Interrupt Vector Offset Register 36 */
553 #define SPRN_IVOR37	0x215	/* Interrupt Vector Offset Register 37 */
554 #define SPRN_SPEFSCR	0x200	/* SPE & Embedded FP Status & Control */
555 
556 #define SPRN_MCSRR0	0x23a	/* Machine Check Save and Restore Register 0 */
557 #define SPRN_MCSRR1	0x23b	/* Machine Check Save and Restore Register 1 */
558 #define SPRN_BUCSR	0x3f5	/* Branch Control and Status Register */
559 #define	  BUCSR_STAC_EN	0x01000000	/* Segment target addr cache enable */
560 #define	  BUCSR_LS_EN	0x00400000	/* Link stack enable */
561 #define	  BUCSR_BBFI	0x00000200	/* Branch buffer flash invalidate */
562 #define	  BUCSR_BPEN	0x00000001	/* Branch prediction enable */
563 #define   BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN)
564 #define SPRN_BBEAR	0x201	/* Branch Buffer Entry Address Register */
565 #define SPRN_BBTAR	0x202	/* Branch Buffer Target Address Register */
566 #define SPRN_PID1	0x279	/* Process ID Register 1 */
567 #define SPRN_PID2	0x27a	/* Process ID Register 2 */
568 #define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
569 #define SPRN_MCAR	0x23d	/* Machine Check Address register */
570 #define MCSR_MCS	0x80000000	/* Machine Check Summary */
571 #define MCSR_IB		0x40000000	/* Instruction PLB Error */
572 #if defined(CONFIG_440)
573 #define MCSR_DRB	0x20000000	/* Data Read PLB Error */
574 #define MCSR_DWB	0x10000000	/* Data Write PLB Error */
575 #else
576 #define MCSR_DB		0x20000000	/* Data PLB Error */
577 #endif /* defined(CONFIG_440) */
578 #define MCSR_TLBP	0x08000000	/* TLB Parity Error */
579 #define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
580 #define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
581 #define MCSR_DCFP	0x01000000	/* D-Cache Flush Parity Error */
582 #define MCSR_IMPE	0x00800000	/* Imprecise Machine Check Exception */
583 #define ESR_ST		0x00800000	/* Store Operation */
584 
585 #if defined(CONFIG_MPC86xx)
586 #define SPRN_MSSCR0	0x3f6
587 #define SPRN_MSSSR0	0x3f7
588 #endif
589 
590 #define SPRN_HDBCR0	0x3d0
591 #define SPRN_HDBCR1	0x3d1
592 #define SPRN_HDBCR2	0x3d2
593 #define SPRN_HDBCR3	0x3d3
594 #define SPRN_HDBCR4	0x3d4
595 #define SPRN_HDBCR5	0x3d5
596 #define SPRN_HDBCR6	0x3d6
597 #define SPRN_HDBCR7	0x277
598 #define SPRN_HDBCR8	0x278
599 
600 /* Short-hand versions for a number of the above SPRNs */
601 
602 #define CTR	SPRN_CTR	/* Counter Register */
603 #define DAR	SPRN_DAR	/* Data Address Register */
604 #define DABR	SPRN_DABR	/* Data Address Breakpoint Register */
605 #define DAC1	SPRN_DAC1	/* Data Address Register 1 */
606 #define DAC2	SPRN_DAC2	/* Data Address Register 2 */
607 #define DBAT0L	SPRN_DBAT0L	/* Data BAT 0 Lower Register */
608 #define DBAT0U	SPRN_DBAT0U	/* Data BAT 0 Upper Register */
609 #define DBAT1L	SPRN_DBAT1L	/* Data BAT 1 Lower Register */
610 #define DBAT1U	SPRN_DBAT1U	/* Data BAT 1 Upper Register */
611 #define DBAT2L	SPRN_DBAT2L	/* Data BAT 2 Lower Register */
612 #define DBAT2U	SPRN_DBAT2U	/* Data BAT 2 Upper Register */
613 #define DBAT3L	SPRN_DBAT3L	/* Data BAT 3 Lower Register */
614 #define DBAT3U	SPRN_DBAT3U	/* Data BAT 3 Upper Register */
615 #define DBAT4L	SPRN_DBAT4L	/* Data BAT 4 Lower Register */
616 #define DBAT4U	SPRN_DBAT4U	/* Data BAT 4 Upper Register */
617 #define DBAT5L	SPRN_DBAT5L	/* Data BAT 5 Lower Register */
618 #define DBAT5U	SPRN_DBAT5U	/* Data BAT 5 Upper Register */
619 #define DBAT6L	SPRN_DBAT6L	/* Data BAT 6 Lower Register */
620 #define DBAT6U	SPRN_DBAT6U	/* Data BAT 6 Upper Register */
621 #define DBAT7L	SPRN_DBAT7L	/* Data BAT 7 Lower Register */
622 #define DBAT7U	SPRN_DBAT7U	/* Data BAT 7 Upper Register */
623 #define DBCR0	SPRN_DBCR0	/* Debug Control Register 0 */
624 #define DBCR1	SPRN_DBCR1	/* Debug Control Register 1 */
625 #define DBSR	SPRN_DBSR	/* Debug Status Register */
626 #define DCMP	SPRN_DCMP	/* Data TLB Compare Register */
627 #define DEC	SPRN_DEC	/* Decrement Register */
628 #define DMISS	SPRN_DMISS	/* Data TLB Miss Register */
629 #define DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
630 #define EAR	SPRN_EAR	/* External Address Register */
631 #define ESR	SPRN_ESR	/* Exception Syndrome Register */
632 #define HASH1	SPRN_HASH1	/* Primary Hash Address Register */
633 #define HASH2	SPRN_HASH2	/* Secondary Hash Address Register */
634 #define HID0	SPRN_HID0	/* Hardware Implementation Register 0 */
635 #define HID1	SPRN_HID1	/* Hardware Implementation Register 1 */
636 #define IABR	SPRN_IABR	/* Instruction Address Breakpoint Register */
637 #define IAC1	SPRN_IAC1	/* Instruction Address Register 1 */
638 #define IAC2	SPRN_IAC2	/* Instruction Address Register 2 */
639 #define IBAT0L	SPRN_IBAT0L	/* Instruction BAT 0 Lower Register */
640 #define IBAT0U	SPRN_IBAT0U	/* Instruction BAT 0 Upper Register */
641 #define IBAT1L	SPRN_IBAT1L	/* Instruction BAT 1 Lower Register */
642 #define IBAT1U	SPRN_IBAT1U	/* Instruction BAT 1 Upper Register */
643 #define IBAT2L	SPRN_IBAT2L	/* Instruction BAT 2 Lower Register */
644 #define IBAT2U	SPRN_IBAT2U	/* Instruction BAT 2 Upper Register */
645 #define IBAT3L	SPRN_IBAT3L	/* Instruction BAT 3 Lower Register */
646 #define IBAT3U	SPRN_IBAT3U	/* Instruction BAT 3 Upper Register */
647 #define IBAT4L	SPRN_IBAT4L	/* Instruction BAT 4 Lower Register */
648 #define IBAT4U	SPRN_IBAT4U	/* Instruction BAT 4 Upper Register */
649 #define IBAT5L	SPRN_IBAT5L	/* Instruction BAT 5 Lower Register */
650 #define IBAT5U	SPRN_IBAT5U	/* Instruction BAT 5 Upper Register */
651 #define IBAT6L	SPRN_IBAT6L	/* Instruction BAT 6 Lower Register */
652 #define IBAT6U	SPRN_IBAT6U	/* Instruction BAT 6 Upper Register */
653 #define IBAT7L	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
654 #define IBAT7U	SPRN_IBAT7U	/* Instruction BAT 7 Lower Register */
655 #define ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
656 #define IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
657 #define IMMR	SPRN_IMMR	/* PPC 860/821 Internal Memory Map Register */
658 #define LDSTCR	SPRN_LDSTCR	/* Load/Store Control Register */
659 #define L2CR	SPRN_L2CR	/* PPC 750 L2 control register */
660 #define LR	SPRN_LR
661 #define MBAR	SPRN_MBAR	/* System memory base address */
662 #if defined(CONFIG_MPC86xx)
663 #define MSSCR0	SPRN_MSSCR0
664 #endif
665 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
666 #define PIR	SPRN_PIR
667 #endif
668 #define SVR	SPRN_SVR	/* System-On-Chip Version Register */
669 #define PVR	SPRN_PVR	/* Processor Version */
670 #define RPA	SPRN_RPA	/* Required Physical Address Register */
671 #define SDR1	SPRN_SDR1	/* MMU hash base register */
672 #define SPR0	SPRN_SPRG0	/* Supervisor Private Registers */
673 #define SPR1	SPRN_SPRG1
674 #define SPR2	SPRN_SPRG2
675 #define SPR3	SPRN_SPRG3
676 #define SPRG0	SPRN_SPRG0
677 #define SPRG1	SPRN_SPRG1
678 #define SPRG2	SPRN_SPRG2
679 #define SPRG3	SPRN_SPRG3
680 #define SPRG4	SPRN_SPRG4
681 #define SPRG5	SPRN_SPRG5
682 #define SPRG6	SPRN_SPRG6
683 #define SPRG7	SPRN_SPRG7
684 #define SRR0	SPRN_SRR0	/* Save and Restore Register 0 */
685 #define SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
686 #define SRR2	SPRN_SRR2	/* Save and Restore Register 2 */
687 #define SRR3	SPRN_SRR3	/* Save and Restore Register 3 */
688 #define SVR	SPRN_SVR	/* System Version Register */
689 #define TBRL	SPRN_TBRL	/* Time Base Read Lower Register */
690 #define TBRU	SPRN_TBRU	/* Time Base Read Upper Register */
691 #define TBWL	SPRN_TBWL	/* Time Base Write Lower Register */
692 #define TBWU	SPRN_TBWU	/* Time Base Write Upper Register */
693 #define TCR	SPRN_TCR	/* Timer Control Register */
694 #define TSR	SPRN_TSR	/* Timer Status Register */
695 #define ICTC	1019
696 #define THRM1	SPRN_THRM1	/* Thermal Management Register 1 */
697 #define THRM2	SPRN_THRM2	/* Thermal Management Register 2 */
698 #define THRM3	SPRN_THRM3	/* Thermal Management Register 3 */
699 #define XER	SPRN_XER
700 
701 #define DECAR	SPRN_DECAR
702 #define CSRR0	SPRN_CSRR0
703 #define CSRR1	SPRN_CSRR1
704 #define IVPR	SPRN_IVPR
705 #define USPRG0	SPRN_USPRG
706 #define SPRG4R	SPRN_SPRG4R
707 #define SPRG5R	SPRN_SPRG5R
708 #define SPRG6R	SPRN_SPRG6R
709 #define SPRG7R	SPRN_SPRG7R
710 #define SPRG4W	SPRN_SPRG4W
711 #define SPRG5W	SPRN_SPRG5W
712 #define SPRG6W	SPRN_SPRG6W
713 #define SPRG7W	SPRN_SPRG7W
714 #define DEAR	SPRN_DEAR
715 #define DBCR2	SPRN_DBCR2
716 #define IAC3	SPRN_IAC3
717 #define IAC4	SPRN_IAC4
718 #define DVC1	SPRN_DVC1
719 #define DVC2	SPRN_DVC2
720 #define IVOR0	SPRN_IVOR0
721 #define IVOR1	SPRN_IVOR1
722 #define IVOR2	SPRN_IVOR2
723 #define IVOR3	SPRN_IVOR3
724 #define IVOR4	SPRN_IVOR4
725 #define IVOR5	SPRN_IVOR5
726 #define IVOR6	SPRN_IVOR6
727 #define IVOR7	SPRN_IVOR7
728 #define IVOR8	SPRN_IVOR8
729 #define IVOR9	SPRN_IVOR9
730 #define IVOR10	SPRN_IVOR10
731 #define IVOR11	SPRN_IVOR11
732 #define IVOR12	SPRN_IVOR12
733 #define IVOR13	SPRN_IVOR13
734 #define IVOR14	SPRN_IVOR14
735 #define IVOR15	SPRN_IVOR15
736 #define IVOR32	SPRN_IVOR32
737 #define IVOR33	SPRN_IVOR33
738 #define IVOR34	SPRN_IVOR34
739 #define IVOR35	SPRN_IVOR35
740 #define MCSRR0	SPRN_MCSRR0
741 #define MCSRR1	SPRN_MCSRR1
742 #define L1CSR0	SPRN_L1CSR0
743 #define L1CSR1	SPRN_L1CSR1
744 #define L1CSR2	SPRN_L1CSR2
745 #define L1CFG0	SPRN_L1CFG0
746 #define L1CFG1	SPRN_L1CFG1
747 #define L2CFG0	SPRN_L2CFG0
748 #define L2CSR0	SPRN_L2CSR0
749 #define L2CSR1	SPRN_L2CSR1
750 #define MCSR	SPRN_MCSR
751 #define MMUCSR0	SPRN_MMUCSR0
752 #define BUCSR	SPRN_BUCSR
753 #define PID0	SPRN_PID
754 #define PID1	SPRN_PID1
755 #define PID2	SPRN_PID2
756 #define MAS0	SPRN_MAS0
757 #define MAS1	SPRN_MAS1
758 #define MAS2	SPRN_MAS2
759 #define MAS3	SPRN_MAS3
760 #define MAS4	SPRN_MAS4
761 #define MAS5	SPRN_MAS5
762 #define MAS6	SPRN_MAS6
763 #define MAS7	SPRN_MAS7
764 #define MAS8 	SPRN_MAS8
765 
766 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
767 #define DAR_DEAR DEAR
768 #else
769 #define DAR_DEAR DAR
770 #endif
771 
772 /* Device Control Registers */
773 
774 #define DCRN_BEAR	0x090	/* Bus Error Address Register */
775 #define DCRN_BESR	0x091	/* Bus Error Syndrome Register */
776 #define   BESR_DSES	0x80000000	/* Data-Side Error Status */
777 #define   BESR_DMES	0x40000000	/* DMA Error Status */
778 #define   BESR_RWS	0x20000000	/* Read/Write Status */
779 #define   BESR_ETMASK	0x1C000000	/* Error Type */
780 #define     ET_PROT	0
781 #define     ET_PARITY	1
782 #define     ET_NCFG	2
783 #define     ET_BUSERR	4
784 #define     ET_BUSTO	6
785 #define DCRN_DMACC0	0x0C4	/* DMA Chained Count Register 0 */
786 #define DCRN_DMACC1	0x0CC	/* DMA Chained Count Register 1 */
787 #define DCRN_DMACC2	0x0D4	/* DMA Chained Count Register 2 */
788 #define DCRN_DMACC3	0x0DC	 /* DMA Chained Count Register 3 */
789 #define DCRN_DMACR0	0x0C0	 /* DMA Channel Control Register 0 */
790 #define DCRN_DMACR1	0x0C8	 /* DMA Channel Control Register 1 */
791 #define DCRN_DMACR2	0x0D0	 /* DMA Channel Control Register 2 */
792 #define DCRN_DMACR3	0x0D8	 /* DMA Channel Control Register 3 */
793 #define DCRN_DMACT0	0x0C1	 /* DMA Count Register 0 */
794 #define DCRN_DMACT1	0x0C9	 /* DMA Count Register 1 */
795 #define DCRN_DMACT2	0x0D1	 /* DMA Count Register 2 */
796 #define DCRN_DMACT3	0x0D9	 /* DMA Count Register 3 */
797 #define DCRN_DMADA0	0x0C2	 /* DMA Destination Address Register 0 */
798 #define DCRN_DMADA1	0x0CA	 /* DMA Destination Address Register 1 */
799 #define DCRN_DMADA2	0x0D2	 /* DMA Destination Address Register 2 */
800 #define DCRN_DMADA3	0x0DA	 /* DMA Destination Address Register 3 */
801 #define DCRN_DMASA0	0x0C3	 /* DMA Source Address Register 0 */
802 #define DCRN_DMASA1	0x0CB	 /* DMA Source Address Register 1 */
803 #define DCRN_DMASA2	0x0D3	 /* DMA Source Address Register 2 */
804 #define DCRN_DMASA3	0x0DB	 /* DMA Source Address Register 3 */
805 #define DCRN_DMASR	0x0E0	 /* DMA Status Register */
806 #define DCRN_EXIER	0x042	 /* External Interrupt Enable Register */
807 #define   EXIER_CIE	0x80000000	/* Critical Interrupt Enable */
808 #define   EXIER_SRIE	0x08000000	/* Serial Port Rx Int. Enable */
809 #define   EXIER_STIE	0x04000000	/* Serial Port Tx Int. Enable */
810 #define   EXIER_JRIE	0x02000000	/* JTAG Serial Port Rx Int. Enable */
811 #define   EXIER_JTIE	0x01000000	/* JTAG Serial Port Tx Int. Enable */
812 #define   EXIER_D0IE	0x00800000	/* DMA Channel 0 Interrupt Enable */
813 #define   EXIER_D1IE	0x00400000	/* DMA Channel 1 Interrupt Enable */
814 #define   EXIER_D2IE	0x00200000	/* DMA Channel 2 Interrupt Enable */
815 #define   EXIER_D3IE	0x00100000	/* DMA Channel 3 Interrupt Enable */
816 #define   EXIER_E0IE	0x00000010	/* External Interrupt 0 Enable */
817 #define   EXIER_E1IE	0x00000008	/* External Interrupt 1 Enable */
818 #define   EXIER_E2IE	0x00000004	/* External Interrupt 2 Enable */
819 #define   EXIER_E3IE	0x00000002	/* External Interrupt 3 Enable */
820 #define   EXIER_E4IE	0x00000001	/* External Interrupt 4 Enable */
821 #define DCRN_EXISR	0x040	 /* External Interrupt Status Register */
822 #define DCRN_IOCR	0x0A0	 /* Input/Output Configuration Register */
823 #define   IOCR_E0TE	0x80000000
824 #define   IOCR_E0LP	0x40000000
825 #define   IOCR_E1TE	0x20000000
826 #define   IOCR_E1LP	0x10000000
827 #define   IOCR_E2TE	0x08000000
828 #define   IOCR_E2LP	0x04000000
829 #define   IOCR_E3TE	0x02000000
830 #define   IOCR_E3LP	0x01000000
831 #define   IOCR_E4TE	0x00800000
832 #define   IOCR_E4LP	0x00400000
833 #define   IOCR_EDT	0x00080000
834 #define   IOCR_SOR	0x00040000
835 #define   IOCR_EDO	0x00008000
836 #define   IOCR_2XC	0x00004000
837 #define   IOCR_ATC	0x00002000
838 #define   IOCR_SPD	0x00001000
839 #define   IOCR_BEM	0x00000800
840 #define   IOCR_PTD	0x00000400
841 #define   IOCR_ARE	0x00000080
842 #define   IOCR_DRC	0x00000020
843 #define   IOCR_RDM(x)	(((x) & 0x3) << 3)
844 #define   IOCR_TCS	0x00000004
845 #define   IOCR_SCS	0x00000002
846 #define   IOCR_SPC	0x00000001
847 
848 /* System-On-Chip Version Register */
849 
850 /* System-On-Chip Version Register (SVR) field extraction */
851 
852 #define SVR_VER(svr)	(((svr) >> 16) & 0xFFFF) /* Version field */
853 #define SVR_REV(svr)	(((svr) >>  0) & 0xFF)	 /* Revision field */
854 
855 #define SVR_CID(svr)	(((svr) >> 28) & 0x0F)	 /* Company or manufacturer ID */
856 #define SVR_SOCOP(svr)	(((svr) >> 22) & 0x3F)	 /* SOC integration options */
857 #define SVR_SID(svr)	(((svr) >> 16) & 0x3F)	 /* SOC ID */
858 #define SVR_PROC(svr)	(((svr) >> 12) & 0x0F)	 /* Process revision field */
859 #define SVR_MFG(svr)	(((svr) >>  8) & 0x0F)	 /* Manufacturing revision */
860 #define SVR_MJREV(svr)	(((svr) >>  4) & 0x0F)	 /* Major SOC design revision indicator */
861 #define SVR_MNREV(svr)	(((svr) >>  0) & 0x0F)	 /* Minor SOC design revision indicator */
862 
863 /* Processor Version Register */
864 
865 /* Processor Version Register (PVR) field extraction */
866 
867 #define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF)	/* Version field */
868 #define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF)	/* Revison field */
869 
870 /*
871  * AMCC has further subdivided the standard PowerPC 16-bit version and
872  * revision subfields of the PVR for the PowerPC 403s into the following:
873  */
874 
875 #define PVR_FAM(pvr)	(((pvr) >> 20) & 0xFFF)	/* Family field */
876 #define PVR_MEM(pvr)	(((pvr) >> 16) & 0xF)	/* Member field */
877 #define PVR_CORE(pvr)	(((pvr) >> 12) & 0xF)	/* Core field */
878 #define PVR_CFG(pvr)	(((pvr) >>  8) & 0xF)	/* Configuration field */
879 #define PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
880 #define PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */
881 
882 /* e600 core PVR fields */
883 
884 #define PVR_E600_VER(pvr)	(((pvr) >> 15) & 0xFFFF) /* Version/type */
885 #define PVR_E600_TECH(pvr)	(((pvr) >> 12) & 0xF)	 /* Technology */
886 #define PVR_E600_MAJ(pvr)	(((pvr) >> 8) & 0xF)	 /* Major revision */
887 #define PVR_E600_MIN(pvr)	(((pvr) >> 0) & 0xFF)	 /* Minor revision */
888 
889 /* Processor Version Numbers */
890 
891 #define PVR_403GA	0x00200000
892 #define PVR_403GB	0x00200100
893 #define PVR_403GC	0x00200200
894 #define PVR_403GCX	0x00201400
895 #define PVR_405GP	0x40110000
896 #define PVR_405GP_RB	0x40110040
897 #define PVR_405GP_RC	0x40110082
898 #define PVR_405GP_RD	0x401100C4
899 #define PVR_405GP_RE	0x40110145  /* same as pc405cr rev c */
900 #define PVR_405EP_RA	0x51210950
901 #define PVR_405GPR_RB	0x50910951
902 #define PVR_405EZ_RA	0x41511460
903 #define PVR_405EXR2_RA	0x12911471 /* 405EXr rev A/B without Security */
904 #define PVR_405EX1_RA	0x12911477 /* 405EX rev A/B with Security */
905 #define PVR_405EXR1_RC	0x1291147B /* 405EXr rev C with Security */
906 #define PVR_405EXR2_RC	0x12911479 /* 405EXr rev C without Security */
907 #define PVR_405EX1_RC	0x1291147F /* 405EX rev C with Security */
908 #define PVR_405EX2_RC	0x1291147D /* 405EX rev C without Security */
909 #define PVR_405EXR1_RD	0x12911472 /* 405EXr rev D with Security */
910 #define PVR_405EXR2_RD	0x12911470 /* 405EXr rev D without Security */
911 #define PVR_405EX1_RD	0x12911475 /* 405EX rev D with Security */
912 #define PVR_405EX2_RD	0x12911473 /* 405EX rev D without Security */
913 #define PVR_440GP_RB	0x40120440
914 #define PVR_440GP_RC	0x40120481
915 #define PVR_440EP_RA	0x42221850
916 #define PVR_440EP_RB	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
917 #define PVR_440EP_RC	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
918 #define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
919 #define PVR_440GR_RB	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
920 #define PVR_440EPX1_RA	0x216218D0 /* 440EPX rev A with Security / Kasumi */
921 #define PVR_440EPX2_RA	0x216218D4 /* 440EPX rev A without Security / Kasumi */
922 #define PVR_440GRX1_RA	0x216218D0 /* 440GRX rev A with Security / Kasumi */
923 #define PVR_440GRX2_RA	0x216218D4 /* 440GRX rev A without Security / Kasumi */
924 #define PVR_440GX_RA	0x51B21850
925 #define PVR_440GX_RB	0x51B21851
926 #define PVR_440GX_RC	0x51B21892
927 #define PVR_440GX_RF	0x51B21894
928 #define PVR_405EP_RB	0x51210950
929 #define PVR_440SP_6_RAB	0x53221850 /* 440SP rev A&B with RAID 6 support enabled	*/
930 #define PVR_440SP_RAB	0x53321850 /* 440SP rev A&B without RAID 6 support	*/
931 #define PVR_440SP_6_RC	0x53221891 /* 440SP rev C with RAID 6 support enabled	*/
932 #define PVR_440SP_RC	0x53321891 /* 440SP rev C without RAID 6 support	*/
933 #define PVR_440SPe_6_RA	0x53421890 /* 440SPe rev A with RAID 6 support enabled	*/
934 #define PVR_440SPe_RA	0x53521890 /* 440SPe rev A without RAID 6 support	*/
935 #define PVR_440SPe_6_RB	0x53421891 /* 440SPe rev B with RAID 6 support enabled	*/
936 #define PVR_440SPe_RB	0x53521891 /* 440SPe rev B without RAID 6 support	*/
937 #define PVR_460EX_SE_RA	0x130218A2 /* 460EX rev A with Security Engine	  */
938 #define PVR_460EX_RA	0x130218A3 /* 460EX rev A without Security Engine */
939 #define PVR_460EX_RB	0x130218A4 /* 460EX rev B with and without Sec Eng*/
940 #define PVR_460GT_SE_RA	0x130218A0 /* 460GT rev A with Security Engine	  */
941 #define PVR_460GT_RA	0x130218A1 /* 460GT rev A without Security Engine */
942 #define PVR_460GT_RB	0x130218A5 /* 460GT rev B with and without Sec Eng*/
943 #define PVR_460SX_RA    0x13541800 /* 460SX rev A                   */
944 #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
945 #define PVR_460GX_RA    0x13541802 /* 460GX rev A                   */
946 #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
947 #define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */
948 #define PVR_601		0x00010000
949 #define PVR_602		0x00050000
950 #define PVR_603		0x00030000
951 #define PVR_603e	0x00060000
952 #define PVR_603ev	0x00070000
953 #define PVR_603r	0x00071000
954 #define PVR_604		0x00040000
955 #define PVR_604e	0x00090000
956 #define PVR_604r	0x000A0000
957 #define PVR_620		0x00140000
958 #define PVR_740		0x00080000
959 #define PVR_750		PVR_740
960 #define PVR_740P	0x10080000
961 #define PVR_750P	PVR_740P
962 #define PVR_7400	0x000C0000
963 #define PVR_7410	0x800C0000
964 #define PVR_7450	0x80000000
965 
966 #define PVR_85xx	0x80200000
967 #define PVR_85xx_REV1	(PVR_85xx | 0x0010)
968 #define PVR_85xx_REV2	(PVR_85xx | 0x0020)
969 #define PVR_VER_E500_V1	0x8020
970 #define PVR_VER_E500_V2	0x8021
971 #define PVR_VER_E500MC	0x8023
972 #define PVR_VER_E5500	0x8024
973 #define PVR_VER_E6500	0x8040
974 
975 #define PVR_86xx	0x80040000
976 
977 #define PVR_VIRTEX5     0x7ff21912
978 
979 /*
980  * For the 8xx processors, all of them report the same PVR family for
981  * the PowerPC core. The various versions of these processors must be
982  * differentiated by the version number in the Communication Processor
983  * Module (CPM).
984  */
985 #define PVR_821		0x00500000
986 #define PVR_823		PVR_821
987 #define PVR_850		PVR_821
988 #define PVR_860		PVR_821
989 #define PVR_7400	0x000C0000
990 #define PVR_8240	0x00810100
991 
992 /*
993  * PowerQUICC II family processors report different PVR values depending
994  * on silicon process (HiP3, HiP4, HiP7, etc.)
995  */
996 #define PVR_8260	PVR_8240
997 #define PVR_8260_HIP3	0x00810101
998 #define PVR_8260_HIP4	0x80811014
999 #define PVR_8260_HIP7	0x80822011
1000 #define PVR_8260_HIP7R1 0x80822013
1001 #define PVR_8260_HIP7RA	0x80822014
1002 
1003 /*
1004  * MPC 52xx
1005  */
1006 #define PVR_5200	0x80822011
1007 #define PVR_5200B	0x80822014
1008 
1009 /*
1010  * 405EX/EXr CHIP_21 Errata
1011  */
1012 #ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
1013 #define CONFIG_SYS_4xx_CHIP_21_ERRATA
1014 #define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX1_RC
1015 #define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX1_RD
1016 #define CONFIG_405EX_CHIP21_ECID3_REV_D	0x0
1017 #endif
1018 
1019 #ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
1020 #define CONFIG_SYS_4xx_CHIP_21_ERRATA
1021 #define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX2_RC
1022 #define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX2_RD
1023 #define CONFIG_405EX_CHIP21_ECID3_REV_D	0x1
1024 #endif
1025 
1026 #ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
1027 #define CONFIG_SYS_4xx_CHIP_21_ERRATA
1028 #define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR1_RC
1029 #define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR1_RD
1030 #define CONFIG_405EX_CHIP21_ECID3_REV_D	0x2
1031 #endif
1032 
1033 #ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
1034 #define CONFIG_SYS_4xx_CHIP_21_ERRATA
1035 #define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR2_RC
1036 #define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR2_RD
1037 #define CONFIG_405EX_CHIP21_ECID3_REV_D	0x3
1038 #endif
1039 
1040 /*
1041  * System Version Register
1042  */
1043 
1044 /* System Version Register (SVR) field extraction */
1045 
1046 #define SVR_SUBVER(svr)	(((svr) >>  8) & 0xFF)	/* Process/MFG sub-version */
1047 
1048 #define SVR_FAM(svr)	(((svr) >> 20) & 0xFFF)	/* Family field */
1049 #define SVR_MEM(svr)	(((svr) >> 16) & 0xF)	/* Member field */
1050 
1051 #ifdef CONFIG_ARCH_MPC8536
1052 #define SVR_MAJ(svr)	(((svr) >>  4) & 0x7)	/* Major revision field*/
1053 #else
1054 #define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
1055 #endif
1056 #define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
1057 
1058 /* Some parts define SVR[0:23] as the SOC version */
1059 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
1060 
1061 /* whether MPC8xxxE (i.e. has SEC) */
1062 #if defined(CONFIG_MPC85xx)
1063 #define IS_E_PROCESSOR(svr)	(svr & 0x80000)
1064 #else
1065 #if defined(CONFIG_MPC83xx)
1066 #define IS_E_PROCESSOR(spridr)	(!(spridr & 0x00010000))
1067 #endif
1068 #endif
1069 
1070 #define IS_SVR_REV(svr, maj, min) \
1071 	((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
1072 
1073 /*
1074  * SVR_SOC_VER() Version Values
1075  */
1076 
1077 #define SVR_8533	0x803400
1078 #define SVR_8535	0x803701
1079 #define SVR_8536	0x803700
1080 #define SVR_8540	0x803000
1081 #define SVR_8541	0x807200
1082 #define SVR_8543	0x803200
1083 #define SVR_8544	0x803401
1084 #define SVR_8545	0x803102
1085 #define SVR_8547	0x803101
1086 #define SVR_8548	0x803100
1087 #define SVR_8555	0x807100
1088 #define SVR_8560	0x807000
1089 #define SVR_8567	0x807501
1090 #define SVR_8568	0x807500
1091 #define SVR_8569	0x808000
1092 #define SVR_8572	0x80E000
1093 #define SVR_P1010	0x80F100
1094 #define SVR_P1011	0x80E500
1095 #define SVR_P1012	0x80E501
1096 #define SVR_P1013	0x80E700
1097 #define SVR_P1014	0x80F101
1098 #define SVR_P1017	0x80F700
1099 #define SVR_P1020	0x80E400
1100 #define SVR_P1021	0x80E401
1101 #define SVR_P1022	0x80E600
1102 #define SVR_P1023	0x80F600
1103 #define SVR_P1024	0x80E402
1104 #define SVR_P1025	0x80E403
1105 #define SVR_P2010	0x80E300
1106 #define SVR_P2020	0x80E200
1107 #define SVR_P2040	0x821000
1108 #define SVR_P2041	0x821001
1109 #define SVR_P3041	0x821103
1110 #define SVR_P4040	0x820100
1111 #define SVR_P4080	0x820000
1112 #define SVR_P5010	0x822100
1113 #define SVR_P5020	0x822000
1114 #define SVR_P5021	0X820500
1115 #define SVR_P5040	0x820400
1116 #define SVR_T4240	0x824000
1117 #define SVR_T4120	0x824001
1118 #define SVR_T4160	0x824100
1119 #define SVR_T4080	0x824102
1120 #define SVR_C291	0x850000
1121 #define SVR_C292	0x850020
1122 #define SVR_C293	0x850030
1123 #define SVR_B4860	0X868000
1124 #define SVR_G4860	0x868001
1125 #define SVR_B4460	0x868003
1126 #define SVR_B4440	0x868100
1127 #define SVR_G4440	0x868101
1128 #define SVR_B4420	0x868102
1129 #define SVR_B4220	0x868103
1130 #define SVR_T1040	0x852000
1131 #define SVR_T1041	0x852001
1132 #define SVR_T1042	0x852002
1133 #define SVR_T1020	0x852100
1134 #define SVR_T1021	0x852101
1135 #define SVR_T1022	0x852102
1136 #define SVR_T1024	0x854000
1137 #define SVR_T1023	0x854100
1138 #define SVR_T1014	0x854400
1139 #define SVR_T1013	0x854500
1140 #define SVR_T2080	0x853000
1141 #define SVR_T2081	0x853100
1142 
1143 #define SVR_8610	0x80A000
1144 #define SVR_8641	0x809000
1145 #define SVR_8641D	0x809001
1146 
1147 #define SVR_9130	0x860001
1148 #define SVR_9131	0x860000
1149 #define SVR_9132	0x861000
1150 #define SVR_9232	0x861400
1151 
1152 #define SVR_Unknown	0xFFFFFF
1153 
1154 #define _GLOBAL(n)\
1155 	.globl n;\
1156 n:
1157 
1158 /* Macros for setting and retrieving special purpose registers */
1159 
1160 #define stringify(s)	tostring(s)
1161 #define tostring(s)	#s
1162 
1163 #define mfdcr(rn)	({unsigned int rval; \
1164 			asm volatile("mfdcr %0," stringify(rn) \
1165 				     : "=r" (rval)); rval;})
1166 #define mtdcr(rn, v)	asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
1167 
1168 #define mfmsr()		({unsigned int rval; \
1169 			asm volatile("mfmsr %0" : "=r" (rval)); rval;})
1170 #define mtmsr(v)	asm volatile("mtmsr %0" : : "r" (v))
1171 
1172 #define mfspr(rn)	({unsigned int rval; \
1173 			asm volatile("mfspr %0," stringify(rn) \
1174 				     : "=r" (rval)); rval;})
1175 #define mtspr(rn, v)	asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
1176 
1177 #define tlbie(v)	asm volatile("tlbie %0 \n sync" : : "r" (v))
1178 
1179 /* Segment Registers */
1180 
1181 #define SR0	0
1182 #define SR1	1
1183 #define SR2	2
1184 #define SR3	3
1185 #define SR4	4
1186 #define SR5	5
1187 #define SR6	6
1188 #define SR7	7
1189 #define SR8	8
1190 #define SR9	9
1191 #define SR10	10
1192 #define SR11	11
1193 #define SR12	12
1194 #define SR13	13
1195 #define SR14	14
1196 #define SR15	15
1197 
1198 #ifndef __ASSEMBLY__
1199 
1200 struct cpu_type {
1201 	char name[15];
1202 	u32 soc_ver;
1203 	u32 num_cores;
1204 	u32 mask;	/* which cpu(s) actually exist */
1205 #ifdef CONFIG_HETROGENOUS_CLUSTERS
1206 	u32 dsp_num_cores;
1207 	u32 dsp_mask;	/* which DSP cpu(s) actually exist */
1208 #endif
1209 };
1210 
1211 struct cpu_type *identify_cpu(u32 ver);
1212 int fixup_cpu(void);
1213 
1214 int fsl_qoriq_core_to_cluster(unsigned int core);
1215 int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
1216 
1217 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
1218 #define CPU_TYPE_ENTRY(n, v, nc) \
1219 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
1220 	  .mask = (1 << (nc)) - 1 }
1221 #define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \
1222 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) }
1223 #else
1224 #if defined(CONFIG_MPC83xx)
1225 #define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
1226 #endif
1227 #endif
1228 
1229 
1230 #ifndef CONFIG_MACH_SPECIFIC
1231 extern int _machine;
1232 extern int have_of;
1233 #endif /* CONFIG_MACH_SPECIFIC */
1234 
1235 /* what kind of prep workstation we are */
1236 extern int _prep_type;
1237 /*
1238  * This is used to identify the board type from a given PReP board
1239  * vendor. Board revision is also made available.
1240  */
1241 extern unsigned char ucSystemType;
1242 extern unsigned char ucBoardRev;
1243 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
1244 
1245 struct task_struct;
1246 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
1247 void release_thread(struct task_struct *);
1248 
1249 /*
1250  * Create a new kernel thread.
1251  */
1252 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
1253 
1254 /*
1255  * Bus types
1256  */
1257 #define EISA_bus 0
1258 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
1259 #define MCA_bus 0
1260 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
1261 
1262 /* Lazy FPU handling on uni-processor */
1263 extern struct task_struct *last_task_used_math;
1264 extern struct task_struct *last_task_used_altivec;
1265 
1266 /*
1267  * this is the minimum allowable io space due to the location
1268  * of the io areas on prep (first one at 0x80000000) but
1269  * as soon as I get around to remapping the io areas with the BATs
1270  * to match the mac we can raise this. -- Cort
1271  */
1272 #define TASK_SIZE	(0x80000000UL)
1273 
1274 /* This decides where the kernel will search for a free chunk of vm
1275  * space during mmap's.
1276  */
1277 #define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
1278 
1279 typedef struct {
1280 	unsigned long seg;
1281 } mm_segment_t;
1282 
1283 struct thread_struct {
1284 	unsigned long	ksp;		/* Kernel stack pointer */
1285 	unsigned long	wchan;		/* Event task is sleeping on */
1286 	struct pt_regs	*regs;		/* Pointer to saved register state */
1287 	mm_segment_t	fs;		/* for get_fs() validation */
1288 	void		*pgdir;		/* root of page-table tree */
1289 	signed long	last_syscall;
1290 	double		fpr[32];	/* Complete floating point set */
1291 	unsigned long	fpscr_pad;	/* fpr ... fpscr must be contiguous */
1292 	unsigned long	fpscr;		/* Floating point status */
1293 #ifdef CONFIG_ALTIVEC
1294 	vector128	vr[32];		/* Complete AltiVec set */
1295 	vector128	vscr;		/* AltiVec status */
1296 	unsigned long	vrsave;
1297 #endif /* CONFIG_ALTIVEC */
1298 };
1299 
1300 #define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
1301 
1302 #define INIT_THREAD  { \
1303 	INIT_SP, /* ksp */ \
1304 	0, /* wchan */ \
1305 	(struct pt_regs *)INIT_SP - 1, /* regs */ \
1306 	KERNEL_DS, /*fs*/ \
1307 	swapper_pg_dir, /* pgdir */ \
1308 	0, /* last_syscall */ \
1309 	{0}, 0, 0 \
1310 }
1311 
1312 /*
1313  * Note: the vm_start and vm_end fields here should *not*
1314  * be in kernel space.	(Could vm_end == vm_start perhaps?)
1315  */
1316 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
1317 		    PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
1318 		    1, NULL, NULL }
1319 
1320 /*
1321  * Return saved PC of a blocked thread. For now, this is the "user" PC
1322  */
1323 static inline unsigned long thread_saved_pc(struct thread_struct *t)
1324 {
1325 	return (t->regs) ? t->regs->nip : 0;
1326 }
1327 
1328 #define copy_segments(tsk, mm)		do { } while (0)
1329 #define release_segments(mm)		do { } while (0)
1330 #define forget_segments()		do { } while (0)
1331 
1332 unsigned long get_wchan(struct task_struct *p);
1333 
1334 #define KSTK_EIP(tsk)  ((tsk)->thread.regs->nip)
1335 #define KSTK_ESP(tsk)  ((tsk)->thread.regs->gpr[1])
1336 
1337 /*
1338  * NOTE! The task struct and the stack go together
1339  */
1340 #define THREAD_SIZE (2*PAGE_SIZE)
1341 #define alloc_task_struct() \
1342 	((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
1343 #define free_task_struct(p)	free_pages((unsigned long)(p),1)
1344 #define get_task_struct(tsk)	  atomic_inc(&mem_map[MAP_NR(tsk)].count)
1345 
1346 /* in process.c - for early bootup debug -- Cort */
1347 int ll_printk(const char *, ...);
1348 void ll_puts(const char *);
1349 
1350 #define init_task	(init_task_union.task)
1351 #define init_stack	(init_task_union.stack)
1352 
1353 /* In misc.c */
1354 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
1355 
1356 #endif /* ndef ASSEMBLY*/
1357 
1358 #ifdef CONFIG_MACH_SPECIFIC
1359 #if defined(CONFIG_8xx)
1360 #define _machine _MACH_8xx
1361 #define have_of 0
1362 #elif defined(CONFIG_WALNUT)
1363 #define _machine _MACH_walnut
1364 #define have_of 0
1365 #elif defined(CONFIG_MPC8260)
1366 #define _machine _MACH_8260
1367 #define have_of 0
1368 #else
1369 #error "Machine not defined correctly"
1370 #endif
1371 #endif /* CONFIG_MACH_SPECIFIC */
1372 
1373 #if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
1374  #define EPAPR_MAGIC	(0x45504150)
1375 #else
1376  #define EPAPR_MAGIC	(0x65504150)
1377 #endif
1378 
1379 #endif /* __ASM_PPC_PROCESSOR_H */
1380