xref: /openbmc/u-boot/arch/powerpc/include/asm/io.h (revision e9b43cae)
1 /* originally from linux source.
2  * removed the dependencies on CONFIG_ values
3  * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
4  * Modified By Rob Taylor, Flying Pig Systems, 2000
5  */
6 
7 #ifndef _PPC_IO_H
8 #define _PPC_IO_H
9 
10 #include <linux/config.h>
11 #include <asm/byteorder.h>
12 
13 #ifdef CONFIG_ADDR_MAP
14 #include <addr_map.h>
15 #endif
16 
17 #define SIO_CONFIG_RA   0x398
18 #define SIO_CONFIG_RD   0x399
19 
20 #ifndef _IO_BASE
21 #define _IO_BASE 0
22 #endif
23 
24 #define readb(addr) in_8((volatile u8 *)(addr))
25 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
26 #if !defined(__BIG_ENDIAN)
27 #define readw(addr) (*(volatile u16 *) (addr))
28 #define readl(addr) (*(volatile u32 *) (addr))
29 #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
30 #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
31 #else
32 #define readw(addr) in_le16((volatile u16 *)(addr))
33 #define readl(addr) in_le32((volatile u32 *)(addr))
34 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
35 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
36 #endif
37 
38 /*
39  * The insw/outsw/insl/outsl macros don't do byte-swapping.
40  * They are only used in practice for transferring buffers which
41  * are arrays of bytes, and byte-swapping is not appropriate in
42  * that case.  - paulus
43  */
44 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
45 #define outsb(port, buf, ns)    _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
46 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
47 #define outsw(port, buf, ns)    _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
48 #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
49 #define outsl(port, buf, nl)    _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
50 
51 #define inb(port)       in_8((u8 *)((port)+_IO_BASE))
52 #define outb(val, port)     out_8((u8 *)((port)+_IO_BASE), (val))
53 #if !defined(__BIG_ENDIAN)
54 #define inw(port)       in_be16((u16 *)((port)+_IO_BASE))
55 #define outw(val, port)     out_be16((u16 *)((port)+_IO_BASE), (val))
56 #define inl(port)       in_be32((u32 *)((port)+_IO_BASE))
57 #define outl(val, port)     out_be32((u32 *)((port)+_IO_BASE), (val))
58 #else
59 #define inw(port)       in_le16((u16 *)((port)+_IO_BASE))
60 #define outw(val, port)     out_le16((u16 *)((port)+_IO_BASE), (val))
61 #define inl(port)       in_le32((u32 *)((port)+_IO_BASE))
62 #define outl(val, port)     out_le32((u32 *)((port)+_IO_BASE), (val))
63 #endif
64 
65 #define inb_p(port)     in_8((u8 *)((port)+_IO_BASE))
66 #define outb_p(val, port)   out_8((u8 *)((port)+_IO_BASE), (val))
67 #define inw_p(port)     in_le16((u16 *)((port)+_IO_BASE))
68 #define outw_p(val, port)   out_le16((u16 *)((port)+_IO_BASE), (val))
69 #define inl_p(port)     in_le32((u32 *)((port)+_IO_BASE))
70 #define outl_p(val, port)   out_le32((u32 *)((port)+_IO_BASE), (val))
71 
72 extern void _insb(volatile u8 *port, void *buf, int ns);
73 extern void _outsb(volatile u8 *port, const void *buf, int ns);
74 extern void _insw(volatile u16 *port, void *buf, int ns);
75 extern void _outsw(volatile u16 *port, const void *buf, int ns);
76 extern void _insl(volatile u32 *port, void *buf, int nl);
77 extern void _outsl(volatile u32 *port, const void *buf, int nl);
78 extern void _insw_ns(volatile u16 *port, void *buf, int ns);
79 extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
80 extern void _insl_ns(volatile u32 *port, void *buf, int nl);
81 extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
82 
83 /*
84  * The *_ns versions below don't do byte-swapping.
85  * Neither do the standard versions now, these are just here
86  * for older code.
87  */
88 #define insw_ns(port, buf, ns)  _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
89 #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
90 #define insl_ns(port, buf, nl)  _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
91 #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
92 
93 
94 #define IO_SPACE_LIMIT ~0
95 
96 #define memset_io(a,b,c)       memset((void *)(a),(b),(c))
97 #define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
98 #define memcpy_toio(a,b,c)  memcpy((void *)(a),(b),(c))
99 
100 /*
101  * Enforce In-order Execution of I/O:
102  * Acts as a barrier to ensure all previous I/O accesses have
103  * completed before any further ones are issued.
104  */
105 static inline void eieio(void)
106 {
107 	__asm__ __volatile__ ("eieio" : : : "memory");
108 }
109 
110 static inline void sync(void)
111 {
112 	__asm__ __volatile__ ("sync" : : : "memory");
113 }
114 
115 static inline void isync(void)
116 {
117 	__asm__ __volatile__ ("isync" : : : "memory");
118 }
119 
120 /* Enforce in-order execution of data I/O.
121  * No distinction between read/write on PPC; use eieio for all three.
122  */
123 #define iobarrier_rw() eieio()
124 #define iobarrier_r()  eieio()
125 #define iobarrier_w()  eieio()
126 
127 /*
128  * Non ordered and non-swapping "raw" accessors
129  */
130 #define __iomem
131 #define PCI_FIX_ADDR(addr)	(addr)
132 
133 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
134 {
135 	return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
136 }
137 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
138 {
139 	return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
140 }
141 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
142 {
143 	return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
144 }
145 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
146 {
147 	*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
148 }
149 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
150 {
151 	*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
152 }
153 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
154 {
155 	*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
156 }
157 
158 /*
159  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
160  *
161  * Read operations have additional twi & isync to make sure the read
162  * is actually performed (i.e. the data has come back) before we start
163  * executing any following instructions.
164  */
165 extern inline int in_8(const volatile unsigned char __iomem *addr)
166 {
167 	int ret;
168 
169 	__asm__ __volatile__(
170 		"sync; lbz%U1%X1 %0,%1;\n"
171 		"twi 0,%0,0;\n"
172 		"isync" : "=r" (ret) : "m" (*addr));
173 	return ret;
174 }
175 
176 extern inline void out_8(volatile unsigned char __iomem *addr, int val)
177 {
178 	__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
179 }
180 
181 extern inline int in_le16(const volatile unsigned short __iomem *addr)
182 {
183 	int ret;
184 
185 	__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
186 			     "twi 0,%0,0;\n"
187 			     "isync" : "=r" (ret) :
188 			      "r" (addr), "m" (*addr));
189 	return ret;
190 }
191 
192 extern inline int in_be16(const volatile unsigned short __iomem *addr)
193 {
194 	int ret;
195 
196 	__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
197 			     "twi 0,%0,0;\n"
198 			     "isync" : "=r" (ret) : "m" (*addr));
199 	return ret;
200 }
201 
202 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
203 {
204 	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
205 			      "r" (val), "r" (addr));
206 }
207 
208 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
209 {
210 	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
211 }
212 
213 extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
214 {
215 	unsigned ret;
216 
217 	__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
218 			     "twi 0,%0,0;\n"
219 			     "isync" : "=r" (ret) :
220 			     "r" (addr), "m" (*addr));
221 	return ret;
222 }
223 
224 extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
225 {
226 	unsigned ret;
227 
228 	__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
229 			     "twi 0,%0,0;\n"
230 			     "isync" : "=r" (ret) : "m" (*addr));
231 	return ret;
232 }
233 
234 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
235 {
236 	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
237 			     "r" (val), "r" (addr));
238 }
239 
240 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
241 {
242 	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
243 }
244 
245 /* Clear and set bits in one shot. These macros can be used to clear and
246  * set multiple bits in a register using a single call. These macros can
247  * also be used to set a multiple-bit bit pattern using a mask, by
248  * specifying the mask in the 'clear' parameter and the new bit pattern
249  * in the 'set' parameter.
250  */
251 
252 #define clrbits(type, addr, clear) \
253 	out_##type((addr), in_##type(addr) & ~(clear))
254 
255 #define setbits(type, addr, set) \
256 	out_##type((addr), in_##type(addr) | (set))
257 
258 #define clrsetbits(type, addr, clear, set) \
259 	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
260 
261 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
262 #define setbits_be32(addr, set) setbits(be32, addr, set)
263 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
264 
265 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
266 #define setbits_le32(addr, set) setbits(le32, addr, set)
267 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
268 
269 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
270 #define setbits_be16(addr, set) setbits(be16, addr, set)
271 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
272 
273 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
274 #define setbits_le16(addr, set) setbits(le16, addr, set)
275 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
276 
277 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
278 #define setbits_8(addr, set) setbits(8, addr, set)
279 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
280 
281 /*
282  * Given a physical address and a length, return a virtual address
283  * that can be used to access the memory range with the caching
284  * properties specified by "flags".
285  */
286 #define MAP_NOCACHE	(0)
287 #define MAP_WRCOMBINE	(0)
288 #define MAP_WRBACK	(0)
289 #define MAP_WRTHROUGH	(0)
290 
291 static inline void *
292 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
293 {
294 #ifdef CONFIG_ADDR_MAP
295 	return (void *)(addrmap_phys_to_virt(paddr));
296 #else
297 	return (void *)((unsigned long)paddr);
298 #endif
299 }
300 
301 /*
302  * Take down a mapping set up by map_physmem().
303  */
304 static inline void unmap_physmem(void *vaddr, unsigned long flags)
305 {
306 
307 }
308 
309 static inline phys_addr_t virt_to_phys(void * vaddr)
310 {
311 #ifdef CONFIG_ADDR_MAP
312 	return addrmap_virt_to_phys(vaddr);
313 #else
314 	return (phys_addr_t)((unsigned long)vaddr);
315 #endif
316 }
317 
318 #endif
319