1 /* 2 * MPC85xx Internal Memory Map 3 * 4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 5 * 6 * Copyright(c) 2002,2003 Motorola Inc. 7 * Xianghua Xiao (x.xiao@motorola.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __IMMAP_85xx__ 29 #define __IMMAP_85xx__ 30 31 #include <asm/types.h> 32 #include <asm/fsl_dma.h> 33 #include <asm/fsl_i2c.h> 34 #include <asm/fsl_lbc.h> 35 36 typedef struct ccsr_local { 37 u32 ccsrbarh; /* CCSR Base Addr High */ 38 u32 ccsrbarl; /* CCSR Base Addr Low */ 39 u32 ccsrar; /* CCSR Attr */ 40 #define CCSRAR_C 0x80000000 /* Commit */ 41 u8 res1[4]; 42 u32 altcbarh; /* Alternate Configuration Base Addr High */ 43 u32 altcbarl; /* Alternate Configuration Base Addr Low */ 44 u32 altcar; /* Alternate Configuration Attr */ 45 u8 res2[4]; 46 u32 bstrh; /* Boot space translation high */ 47 u32 bstrl; /* Boot space translation Low */ 48 u32 bstrar; /* Boot space translation attributes */ 49 u8 res3[0xbd4]; 50 struct { 51 u32 lawbarh; /* LAWn base addr high */ 52 u32 lawbarl; /* LAWn base addr low */ 53 u32 lawar; /* LAWn attributes */ 54 u8 res4[4]; 55 } law[32]; 56 u8 res35[0x204]; 57 } ccsr_local_t; 58 59 /* Local-Access Registers & ECM Registers */ 60 typedef struct ccsr_local_ecm { 61 u32 ccsrbar; /* CCSR Base Addr */ 62 u8 res1[4]; 63 u32 altcbar; /* Alternate Configuration Base Addr */ 64 u8 res2[4]; 65 u32 altcar; /* Alternate Configuration Attr */ 66 u8 res3[12]; 67 u32 bptr; /* Boot Page Translation */ 68 u8 res4[3044]; 69 u32 lawbar0; /* Local Access Window 0 Base Addr */ 70 u8 res5[4]; 71 u32 lawar0; /* Local Access Window 0 Attrs */ 72 u8 res6[20]; 73 u32 lawbar1; /* Local Access Window 1 Base Addr */ 74 u8 res7[4]; 75 u32 lawar1; /* Local Access Window 1 Attrs */ 76 u8 res8[20]; 77 u32 lawbar2; /* Local Access Window 2 Base Addr */ 78 u8 res9[4]; 79 u32 lawar2; /* Local Access Window 2 Attrs */ 80 u8 res10[20]; 81 u32 lawbar3; /* Local Access Window 3 Base Addr */ 82 u8 res11[4]; 83 u32 lawar3; /* Local Access Window 3 Attrs */ 84 u8 res12[20]; 85 u32 lawbar4; /* Local Access Window 4 Base Addr */ 86 u8 res13[4]; 87 u32 lawar4; /* Local Access Window 4 Attrs */ 88 u8 res14[20]; 89 u32 lawbar5; /* Local Access Window 5 Base Addr */ 90 u8 res15[4]; 91 u32 lawar5; /* Local Access Window 5 Attrs */ 92 u8 res16[20]; 93 u32 lawbar6; /* Local Access Window 6 Base Addr */ 94 u8 res17[4]; 95 u32 lawar6; /* Local Access Window 6 Attrs */ 96 u8 res18[20]; 97 u32 lawbar7; /* Local Access Window 7 Base Addr */ 98 u8 res19[4]; 99 u32 lawar7; /* Local Access Window 7 Attrs */ 100 u8 res19_8a[20]; 101 u32 lawbar8; /* Local Access Window 8 Base Addr */ 102 u8 res19_8b[4]; 103 u32 lawar8; /* Local Access Window 8 Attrs */ 104 u8 res19_9a[20]; 105 u32 lawbar9; /* Local Access Window 9 Base Addr */ 106 u8 res19_9b[4]; 107 u32 lawar9; /* Local Access Window 9 Attrs */ 108 u8 res19_10a[20]; 109 u32 lawbar10; /* Local Access Window 10 Base Addr */ 110 u8 res19_10b[4]; 111 u32 lawar10; /* Local Access Window 10 Attrs */ 112 u8 res19_11a[20]; 113 u32 lawbar11; /* Local Access Window 11 Base Addr */ 114 u8 res19_11b[4]; 115 u32 lawar11; /* Local Access Window 11 Attrs */ 116 u8 res20[652]; 117 u32 eebacr; /* ECM CCB Addr Configuration */ 118 u8 res21[12]; 119 u32 eebpcr; /* ECM CCB Port Configuration */ 120 u8 res22[3564]; 121 u32 eedr; /* ECM Error Detect */ 122 u8 res23[4]; 123 u32 eeer; /* ECM Error Enable */ 124 u32 eeatr; /* ECM Error Attrs Capture */ 125 u32 eeadr; /* ECM Error Addr Capture */ 126 u8 res24[492]; 127 } ccsr_local_ecm_t; 128 129 /* DDR memory controller registers */ 130 typedef struct ccsr_ddr { 131 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ 132 u8 res1[4]; 133 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ 134 u8 res2[4]; 135 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ 136 u8 res3[4]; 137 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ 138 u8 res4[100]; 139 u32 cs0_config; /* Chip Select Configuration */ 140 u32 cs1_config; /* Chip Select Configuration */ 141 u32 cs2_config; /* Chip Select Configuration */ 142 u32 cs3_config; /* Chip Select Configuration */ 143 u8 res4a[48]; 144 u32 cs0_config_2; /* Chip Select Configuration 2 */ 145 u32 cs1_config_2; /* Chip Select Configuration 2 */ 146 u32 cs2_config_2; /* Chip Select Configuration 2 */ 147 u32 cs3_config_2; /* Chip Select Configuration 2 */ 148 u8 res5[48]; 149 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 150 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 151 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 152 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 153 u32 sdram_cfg; /* SDRAM Control Configuration */ 154 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ 155 u32 sdram_mode; /* SDRAM Mode Configuration */ 156 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ 157 u32 sdram_md_cntl; /* SDRAM Mode Control */ 158 u32 sdram_interval; /* SDRAM Interval Configuration */ 159 u32 sdram_data_init; /* SDRAM Data initialization */ 160 u8 res6[4]; 161 u32 sdram_clk_cntl; /* SDRAM Clock Control */ 162 u8 res7[20]; 163 u32 init_addr; /* training init addr */ 164 u32 init_ext_addr; /* training init extended addr */ 165 u8 res8_1[16]; 166 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ 167 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ 168 u8 reg8_1a[8]; 169 u32 ddr_zq_cntl; /* ZQ calibration control*/ 170 u32 ddr_wrlvl_cntl; /* write leveling control*/ 171 u8 reg8_1aa[4]; 172 u32 ddr_sr_cntr; /* self refresh counter */ 173 u32 ddr_sdram_rcw_1; /* Control Words 1 */ 174 u32 ddr_sdram_rcw_2; /* Control Words 2 */ 175 u8 res8_1b[2456]; 176 u32 ddr_dsr1; /* Debug Status 1 */ 177 u32 ddr_dsr2; /* Debug Status 2 */ 178 u32 ddr_cdr1; /* Control Driver 1 */ 179 u32 ddr_cdr2; /* Control Driver 2 */ 180 u8 res8_1c[200]; 181 u32 ip_rev1; /* IP Block Revision 1 */ 182 u32 ip_rev2; /* IP Block Revision 2 */ 183 u8 res8_2[512]; 184 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ 185 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ 186 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ 187 u8 res9[20]; 188 u32 capture_data_hi; /* Data Path Read Capture High */ 189 u32 capture_data_lo; /* Data Path Read Capture Low */ 190 u32 capture_ecc; /* Data Path Read Capture ECC */ 191 u8 res10[20]; 192 u32 err_detect; /* Error Detect */ 193 u32 err_disable; /* Error Disable */ 194 u32 err_int_en; 195 u32 capture_attributes; /* Error Attrs Capture */ 196 u32 capture_address; /* Error Addr Capture */ 197 u32 capture_ext_address; /* Error Extended Addr Capture */ 198 u32 err_sbe; /* Single-Bit ECC Error Management */ 199 u8 res11[164]; 200 u32 debug_1; 201 u32 debug_2; 202 u32 debug_3; 203 u32 debug_4; 204 u32 debug_5; 205 u32 debug_6; 206 u32 debug_7; 207 u32 debug_8; 208 u32 debug_9; 209 u32 debug_10; 210 u32 debug_11; 211 u32 debug_12; 212 u32 debug_13; 213 u32 debug_14; 214 u32 debug_15; 215 u32 debug_16; 216 u32 debug_17; 217 u32 debug_18; 218 u8 res12[184]; 219 } ccsr_ddr_t; 220 221 /* I2C Registers */ 222 typedef struct ccsr_i2c { 223 struct fsl_i2c i2c[1]; 224 u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; 225 } ccsr_i2c_t; 226 227 #if defined(CONFIG_MPC8540) \ 228 || defined(CONFIG_MPC8541) \ 229 || defined(CONFIG_MPC8548) \ 230 || defined(CONFIG_MPC8555) 231 /* DUART Registers */ 232 typedef struct ccsr_duart { 233 u8 res1[1280]; 234 /* URBR1, UTHR1, UDLB1 with the same addr */ 235 u8 urbr1_uthr1_udlb1; 236 /* UIER1, UDMB1 with the same addr01 */ 237 u8 uier1_udmb1; 238 /* UIIR1, UFCR1, UAFR1 with the same addr */ 239 u8 uiir1_ufcr1_uafr1; 240 u8 ulcr1; /* UART1 Line Control */ 241 u8 umcr1; /* UART1 Modem Control */ 242 u8 ulsr1; /* UART1 Line Status */ 243 u8 umsr1; /* UART1 Modem Status */ 244 u8 uscr1; /* UART1 Scratch */ 245 u8 res2[8]; 246 u8 udsr1; /* UART1 DMA Status */ 247 u8 res3[239]; 248 /* URBR2, UTHR2, UDLB2 with the same addr */ 249 u8 urbr2_uthr2_udlb2; 250 /* UIER2, UDMB2 with the same addr */ 251 u8 uier2_udmb2; 252 /* UIIR2, UFCR2, UAFR2 with the same addr */ 253 u8 uiir2_ufcr2_uafr2; 254 u8 ulcr2; /* UART2 Line Control */ 255 u8 umcr2; /* UART2 Modem Control */ 256 u8 ulsr2; /* UART2 Line Status */ 257 u8 umsr2; /* UART2 Modem Status */ 258 u8 uscr2; /* UART2 Scratch */ 259 u8 res4[8]; 260 u8 udsr2; /* UART2 DMA Status */ 261 u8 res5[2543]; 262 } ccsr_duart_t; 263 #else /* MPC8560 uses UART on its CPM */ 264 typedef struct ccsr_duart { 265 u8 res[4096]; 266 } ccsr_duart_t; 267 #endif 268 269 /* eSPI Registers */ 270 typedef struct ccsr_espi { 271 u32 mode; /* eSPI mode */ 272 u32 event; /* eSPI event */ 273 u32 mask; /* eSPI mask */ 274 u32 com; /* eSPI command */ 275 u32 tx; /* eSPI transmit FIFO access */ 276 u32 rx; /* eSPI receive FIFO access */ 277 u8 res1[8]; /* reserved */ 278 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ 279 u8 res2[4048]; /* fill up to 0x1000 */ 280 } ccsr_espi_t; 281 282 /* PCI Registers */ 283 typedef struct ccsr_pcix { 284 u32 cfg_addr; /* PCIX Configuration Addr */ 285 u32 cfg_data; /* PCIX Configuration Data */ 286 u32 int_ack; /* PCIX IRQ Acknowledge */ 287 u8 res1[3060]; 288 u32 potar0; /* PCIX Outbound Transaction Addr 0 */ 289 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ 290 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ 291 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ 292 u32 powar0; /* PCIX Outbound Window Attrs 0 */ 293 u8 res2[12]; 294 u32 potar1; /* PCIX Outbound Transaction Addr 1 */ 295 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ 296 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ 297 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ 298 u32 powar1; /* PCIX Outbound Window Attrs 1 */ 299 u8 res3[12]; 300 u32 potar2; /* PCIX Outbound Transaction Addr 2 */ 301 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ 302 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ 303 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ 304 u32 powar2; /* PCIX Outbound Window Attrs 2 */ 305 u8 res4[12]; 306 u32 potar3; /* PCIX Outbound Transaction Addr 3 */ 307 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ 308 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ 309 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ 310 u32 powar3; /* PCIX Outbound Window Attrs 3 */ 311 u8 res5[12]; 312 u32 potar4; /* PCIX Outbound Transaction Addr 4 */ 313 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ 314 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ 315 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ 316 u32 powar4; /* PCIX Outbound Window Attrs 4 */ 317 u8 res6[268]; 318 u32 pitar3; /* PCIX Inbound Translation Addr 3 */ 319 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ 320 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ 321 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ 322 u32 piwar3; /* PCIX Inbound Window Attrs 3 */ 323 u8 res7[12]; 324 u32 pitar2; /* PCIX Inbound Translation Addr 2 */ 325 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ 326 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ 327 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ 328 u32 piwar2; /* PCIX Inbound Window Attrs 2 */ 329 u8 res8[12]; 330 u32 pitar1; /* PCIX Inbound Translation Addr 1 */ 331 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ 332 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ 333 u8 res9[4]; 334 u32 piwar1; /* PCIX Inbound Window Attrs 1 */ 335 u8 res10[12]; 336 u32 pedr; /* PCIX Error Detect */ 337 u32 pecdr; /* PCIX Error Capture Disable */ 338 u32 peer; /* PCIX Error Enable */ 339 u32 peattrcr; /* PCIX Error Attrs Capture */ 340 u32 peaddrcr; /* PCIX Error Addr Capture */ 341 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ 342 u32 pedlcr; /* PCIX Error Data Low Capture */ 343 u32 pedhcr; /* PCIX Error Error Data High Capture */ 344 u32 gas_timr; /* PCIX Gasket Timer */ 345 u8 res11[476]; 346 } ccsr_pcix_t; 347 348 #define PCIX_COMMAND 0x62 349 #define POWAR_EN 0x80000000 350 #define POWAR_IO_READ 0x00080000 351 #define POWAR_MEM_READ 0x00040000 352 #define POWAR_IO_WRITE 0x00008000 353 #define POWAR_MEM_WRITE 0x00004000 354 #define POWAR_MEM_512M 0x0000001c 355 #define POWAR_IO_1M 0x00000013 356 357 #define PIWAR_EN 0x80000000 358 #define PIWAR_PF 0x20000000 359 #define PIWAR_LOCAL 0x00f00000 360 #define PIWAR_READ_SNOOP 0x00050000 361 #define PIWAR_WRITE_SNOOP 0x00005000 362 #define PIWAR_MEM_2G 0x0000001e 363 364 typedef struct ccsr_gpio { 365 u32 gpdir; 366 u32 gpodr; 367 u32 gpdat; 368 u32 gpier; 369 u32 gpimr; 370 u32 gpicr; 371 } ccsr_gpio_t; 372 373 /* L2 Cache Registers */ 374 typedef struct ccsr_l2cache { 375 u32 l2ctl; /* L2 configuration 0 */ 376 u8 res1[12]; 377 u32 l2cewar0; /* L2 cache external write addr 0 */ 378 u8 res2[4]; 379 u32 l2cewcr0; /* L2 cache external write control 0 */ 380 u8 res3[4]; 381 u32 l2cewar1; /* L2 cache external write addr 1 */ 382 u8 res4[4]; 383 u32 l2cewcr1; /* L2 cache external write control 1 */ 384 u8 res5[4]; 385 u32 l2cewar2; /* L2 cache external write addr 2 */ 386 u8 res6[4]; 387 u32 l2cewcr2; /* L2 cache external write control 2 */ 388 u8 res7[4]; 389 u32 l2cewar3; /* L2 cache external write addr 3 */ 390 u8 res8[4]; 391 u32 l2cewcr3; /* L2 cache external write control 3 */ 392 u8 res9[180]; 393 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ 394 u8 res10[4]; 395 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ 396 u8 res11[3316]; 397 u32 l2errinjhi; /* L2 error injection mask high */ 398 u32 l2errinjlo; /* L2 error injection mask low */ 399 u32 l2errinjctl; /* L2 error injection tag/ECC control */ 400 u8 res12[20]; 401 u32 l2captdatahi; /* L2 error data high capture */ 402 u32 l2captdatalo; /* L2 error data low capture */ 403 u32 l2captecc; /* L2 error ECC capture */ 404 u8 res13[20]; 405 u32 l2errdet; /* L2 error detect */ 406 u32 l2errdis; /* L2 error disable */ 407 u32 l2errinten; /* L2 error interrupt enable */ 408 u32 l2errattr; /* L2 error attributes capture */ 409 u32 l2erraddr; /* L2 error addr capture */ 410 u8 res14[4]; 411 u32 l2errctl; /* L2 error control */ 412 u8 res15[420]; 413 } ccsr_l2cache_t; 414 415 #define MPC85xx_L2CTL_L2E 0x80000000 416 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 417 #define MPC85xx_L2ERRDIS_MBECC 0x00000008 418 #define MPC85xx_L2ERRDIS_SBECC 0x00000004 419 420 /* DMA Registers */ 421 typedef struct ccsr_dma { 422 u8 res1[256]; 423 struct fsl_dma dma[4]; 424 u32 dgsr; /* DMA General Status */ 425 u8 res2[11516]; 426 } ccsr_dma_t; 427 428 /* tsec */ 429 typedef struct ccsr_tsec { 430 u8 res1[16]; 431 u32 ievent; /* IRQ Event */ 432 u32 imask; /* IRQ Mask */ 433 u32 edis; /* Error Disabled */ 434 u8 res2[4]; 435 u32 ecntrl; /* Ethernet Control */ 436 u32 minflr; /* Minimum Frame Len */ 437 u32 ptv; /* Pause Time Value */ 438 u32 dmactrl; /* DMA Control */ 439 u32 tbipa; /* TBI PHY Addr */ 440 u8 res3[88]; 441 u32 fifo_tx_thr; /* FIFO transmit threshold */ 442 u8 res4[8]; 443 u32 fifo_tx_starve; /* FIFO transmit starve */ 444 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ 445 u8 res5[96]; 446 u32 tctrl; /* TX Control */ 447 u32 tstat; /* TX Status */ 448 u8 res6[4]; 449 u32 tbdlen; /* TX Buffer Desc Data Len */ 450 u8 res7[16]; 451 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ 452 u32 ctbptr; /* Current TX Buffer Desc Ptr */ 453 u8 res8[88]; 454 u32 tbptrh; /* TX Buffer Desc Ptr High */ 455 u32 tbptr; /* TX Buffer Desc Ptr Low */ 456 u8 res9[120]; 457 u32 tbaseh; /* TX Desc Base Addr High */ 458 u32 tbase; /* TX Desc Base Addr */ 459 u8 res10[168]; 460 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ 461 u32 ostbdp; /* OOS TX Data Buffer Ptr */ 462 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ 463 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ 464 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ 465 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ 466 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ 467 u8 res11[52]; 468 u32 rctrl; /* RX Control */ 469 u32 rstat; /* RX Status */ 470 u8 res12[4]; 471 u32 rbdlen; /* RxBD Data Len */ 472 u8 res13[16]; 473 u32 crbptrh; /* Current RX Buffer Desc Ptr High */ 474 u32 crbptr; /* Current RX Buffer Desc Ptr */ 475 u8 res14[24]; 476 u32 mrblr; /* Maximum RX Buffer Len */ 477 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ 478 u8 res15[56]; 479 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ 480 u32 rbptr; /* RX Buffer Desc Ptr */ 481 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ 482 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ 483 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ 484 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ 485 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ 486 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ 487 u8 res16[96]; 488 u32 rbaseh; /* RX Desc Base Addr High 0 */ 489 u32 rbase; /* RX Desc Base Addr */ 490 u32 rbaseh1; /* RX Desc Base Addr High 1 */ 491 u32 rbasel1; /* RX Desc Base Addr Low 1 */ 492 u32 rbaseh2; /* RX Desc Base Addr High 2 */ 493 u32 rbasel2; /* RX Desc Base Addr Low 2 */ 494 u32 rbaseh3; /* RX Desc Base Addr High 3 */ 495 u32 rbasel3; /* RX Desc Base Addr Low 3 */ 496 u8 res17[224]; 497 u32 maccfg1; /* MAC Configuration 1 */ 498 u32 maccfg2; /* MAC Configuration 2 */ 499 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 500 u32 hafdup; /* Half Duplex */ 501 u32 maxfrm; /* Maximum Frame Len */ 502 u8 res18[12]; 503 u32 miimcfg; /* MII Management Configuration */ 504 u32 miimcom; /* MII Management Cmd */ 505 u32 miimadd; /* MII Management Addr */ 506 u32 miimcon; /* MII Management Control */ 507 u32 miimstat; /* MII Management Status */ 508 u32 miimind; /* MII Management Indicator */ 509 u8 res19[4]; 510 u32 ifstat; /* Interface Status */ 511 u32 macstnaddr1; /* Station Addr Part 1 */ 512 u32 macstnaddr2; /* Station Addr Part 2 */ 513 u8 res20[312]; 514 u32 tr64; /* TX & RX 64-byte Frame Counter */ 515 u32 tr127; /* TX & RX 65-127 byte Frame Counter */ 516 u32 tr255; /* TX & RX 128-255 byte Frame Counter */ 517 u32 tr511; /* TX & RX 256-511 byte Frame Counter */ 518 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ 519 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ 520 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ 521 u32 rbyt; /* RX Byte Counter */ 522 u32 rpkt; /* RX Packet Counter */ 523 u32 rfcs; /* RX FCS Error Counter */ 524 u32 rmca; /* RX Multicast Packet Counter */ 525 u32 rbca; /* RX Broadcast Packet Counter */ 526 u32 rxcf; /* RX Control Frame Packet Counter */ 527 u32 rxpf; /* RX Pause Frame Packet Counter */ 528 u32 rxuo; /* RX Unknown OP Code Counter */ 529 u32 raln; /* RX Alignment Error Counter */ 530 u32 rflr; /* RX Frame Len Error Counter */ 531 u32 rcde; /* RX Code Error Counter */ 532 u32 rcse; /* RX Carrier Sense Error Counter */ 533 u32 rund; /* RX Undersize Packet Counter */ 534 u32 rovr; /* RX Oversize Packet Counter */ 535 u32 rfrg; /* RX Fragments Counter */ 536 u32 rjbr; /* RX Jabber Counter */ 537 u32 rdrp; /* RX Drop Counter */ 538 u32 tbyt; /* TX Byte Counter Counter */ 539 u32 tpkt; /* TX Packet Counter */ 540 u32 tmca; /* TX Multicast Packet Counter */ 541 u32 tbca; /* TX Broadcast Packet Counter */ 542 u32 txpf; /* TX Pause Control Frame Counter */ 543 u32 tdfr; /* TX Deferral Packet Counter */ 544 u32 tedf; /* TX Excessive Deferral Packet Counter */ 545 u32 tscl; /* TX Single Collision Packet Counter */ 546 u32 tmcl; /* TX Multiple Collision Packet Counter */ 547 u32 tlcl; /* TX Late Collision Packet Counter */ 548 u32 txcl; /* TX Excessive Collision Packet Counter */ 549 u32 tncl; /* TX Total Collision Counter */ 550 u8 res21[4]; 551 u32 tdrp; /* TX Drop Frame Counter */ 552 u32 tjbr; /* TX Jabber Frame Counter */ 553 u32 tfcs; /* TX FCS Error Counter */ 554 u32 txcf; /* TX Control Frame Counter */ 555 u32 tovr; /* TX Oversize Frame Counter */ 556 u32 tund; /* TX Undersize Frame Counter */ 557 u32 tfrg; /* TX Fragments Frame Counter */ 558 u32 car1; /* Carry One */ 559 u32 car2; /* Carry Two */ 560 u32 cam1; /* Carry Mask One */ 561 u32 cam2; /* Carry Mask Two */ 562 u8 res22[192]; 563 u32 iaddr0; /* Indivdual addr 0 */ 564 u32 iaddr1; /* Indivdual addr 1 */ 565 u32 iaddr2; /* Indivdual addr 2 */ 566 u32 iaddr3; /* Indivdual addr 3 */ 567 u32 iaddr4; /* Indivdual addr 4 */ 568 u32 iaddr5; /* Indivdual addr 5 */ 569 u32 iaddr6; /* Indivdual addr 6 */ 570 u32 iaddr7; /* Indivdual addr 7 */ 571 u8 res23[96]; 572 u32 gaddr0; /* Global addr 0 */ 573 u32 gaddr1; /* Global addr 1 */ 574 u32 gaddr2; /* Global addr 2 */ 575 u32 gaddr3; /* Global addr 3 */ 576 u32 gaddr4; /* Global addr 4 */ 577 u32 gaddr5; /* Global addr 5 */ 578 u32 gaddr6; /* Global addr 6 */ 579 u32 gaddr7; /* Global addr 7 */ 580 u8 res24[96]; 581 u32 pmd0; /* Pattern Match Data */ 582 u8 res25[4]; 583 u32 pmask0; /* Pattern Mask */ 584 u8 res26[4]; 585 u32 pcntrl0; /* Pattern Match Control */ 586 u8 res27[4]; 587 u32 pattrb0; /* Pattern Match Attrs */ 588 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ 589 u32 pmd1; /* Pattern Match Data */ 590 u8 res28[4]; 591 u32 pmask1; /* Pattern Mask */ 592 u8 res29[4]; 593 u32 pcntrl1; /* Pattern Match Control */ 594 u8 res30[4]; 595 u32 pattrb1; /* Pattern Match Attrs */ 596 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ 597 u32 pmd2; /* Pattern Match Data */ 598 u8 res31[4]; 599 u32 pmask2; /* Pattern Mask */ 600 u8 res32[4]; 601 u32 pcntrl2; /* Pattern Match Control */ 602 u8 res33[4]; 603 u32 pattrb2; /* Pattern Match Attrs */ 604 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ 605 u32 pmd3; /* Pattern Match Data */ 606 u8 res34[4]; 607 u32 pmask3; /* Pattern Mask */ 608 u8 res35[4]; 609 u32 pcntrl3; /* Pattern Match Control */ 610 u8 res36[4]; 611 u32 pattrb3; /* Pattern Match Attrs */ 612 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ 613 u32 pmd4; /* Pattern Match Data */ 614 u8 res37[4]; 615 u32 pmask4; /* Pattern Mask */ 616 u8 res38[4]; 617 u32 pcntrl4; /* Pattern Match Control */ 618 u8 res39[4]; 619 u32 pattrb4; /* Pattern Match Attrs */ 620 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ 621 u32 pmd5; /* Pattern Match Data */ 622 u8 res40[4]; 623 u32 pmask5; /* Pattern Mask */ 624 u8 res41[4]; 625 u32 pcntrl5; /* Pattern Match Control */ 626 u8 res42[4]; 627 u32 pattrb5; /* Pattern Match Attrs */ 628 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ 629 u32 pmd6; /* Pattern Match Data */ 630 u8 res43[4]; 631 u32 pmask6; /* Pattern Mask */ 632 u8 res44[4]; 633 u32 pcntrl6; /* Pattern Match Control */ 634 u8 res45[4]; 635 u32 pattrb6; /* Pattern Match Attrs */ 636 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ 637 u32 pmd7; /* Pattern Match Data */ 638 u8 res46[4]; 639 u32 pmask7; /* Pattern Mask */ 640 u8 res47[4]; 641 u32 pcntrl7; /* Pattern Match Control */ 642 u8 res48[4]; 643 u32 pattrb7; /* Pattern Match Attrs */ 644 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ 645 u32 pmd8; /* Pattern Match Data */ 646 u8 res49[4]; 647 u32 pmask8; /* Pattern Mask */ 648 u8 res50[4]; 649 u32 pcntrl8; /* Pattern Match Control */ 650 u8 res51[4]; 651 u32 pattrb8; /* Pattern Match Attrs */ 652 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ 653 u32 pmd9; /* Pattern Match Data */ 654 u8 res52[4]; 655 u32 pmask9; /* Pattern Mask */ 656 u8 res53[4]; 657 u32 pcntrl9; /* Pattern Match Control */ 658 u8 res54[4]; 659 u32 pattrb9; /* Pattern Match Attrs */ 660 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ 661 u32 pmd10; /* Pattern Match Data */ 662 u8 res55[4]; 663 u32 pmask10; /* Pattern Mask */ 664 u8 res56[4]; 665 u32 pcntrl10; /* Pattern Match Control */ 666 u8 res57[4]; 667 u32 pattrb10; /* Pattern Match Attrs */ 668 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ 669 u32 pmd11; /* Pattern Match Data */ 670 u8 res58[4]; 671 u32 pmask11; /* Pattern Mask */ 672 u8 res59[4]; 673 u32 pcntrl11; /* Pattern Match Control */ 674 u8 res60[4]; 675 u32 pattrb11; /* Pattern Match Attrs */ 676 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ 677 u32 pmd12; /* Pattern Match Data */ 678 u8 res61[4]; 679 u32 pmask12; /* Pattern Mask */ 680 u8 res62[4]; 681 u32 pcntrl12; /* Pattern Match Control */ 682 u8 res63[4]; 683 u32 pattrb12; /* Pattern Match Attrs */ 684 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ 685 u32 pmd13; /* Pattern Match Data */ 686 u8 res64[4]; 687 u32 pmask13; /* Pattern Mask */ 688 u8 res65[4]; 689 u32 pcntrl13; /* Pattern Match Control */ 690 u8 res66[4]; 691 u32 pattrb13; /* Pattern Match Attrs */ 692 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ 693 u32 pmd14; /* Pattern Match Data */ 694 u8 res67[4]; 695 u32 pmask14; /* Pattern Mask */ 696 u8 res68[4]; 697 u32 pcntrl14; /* Pattern Match Control */ 698 u8 res69[4]; 699 u32 pattrb14; /* Pattern Match Attrs */ 700 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ 701 u32 pmd15; /* Pattern Match Data */ 702 u8 res70[4]; 703 u32 pmask15; /* Pattern Mask */ 704 u8 res71[4]; 705 u32 pcntrl15; /* Pattern Match Control */ 706 u8 res72[4]; 707 u32 pattrb15; /* Pattern Match Attrs */ 708 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ 709 u8 res73[248]; 710 u32 attr; /* Attrs */ 711 u32 attreli; /* Attrs Extract Len & Idx */ 712 u8 res74[1024]; 713 } ccsr_tsec_t; 714 715 /* PIC Registers */ 716 typedef struct ccsr_pic { 717 u8 res1[64]; 718 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ 719 u8 res2[12]; 720 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ 721 u8 res3[12]; 722 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ 723 u8 res4[12]; 724 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ 725 u8 res5[12]; 726 u32 ctpr; /* Current Task Priority */ 727 u8 res6[12]; 728 u32 whoami; /* Who Am I */ 729 u8 res7[12]; 730 u32 iack; /* IRQ Acknowledge */ 731 u8 res8[12]; 732 u32 eoi; /* End Of IRQ */ 733 u8 res9[3916]; 734 u32 frr; /* Feature Reporting */ 735 u8 res10[28]; 736 u32 gcr; /* Global Configuration */ 737 #define MPC85xx_PICGCR_RST 0x80000000 738 #define MPC85xx_PICGCR_M 0x20000000 739 u8 res11[92]; 740 u32 vir; /* Vendor Identification */ 741 u8 res12[12]; 742 u32 pir; /* Processor Initialization */ 743 u8 res13[12]; 744 u32 ipivpr0; /* IPI Vector/Priority 0 */ 745 u8 res14[12]; 746 u32 ipivpr1; /* IPI Vector/Priority 1 */ 747 u8 res15[12]; 748 u32 ipivpr2; /* IPI Vector/Priority 2 */ 749 u8 res16[12]; 750 u32 ipivpr3; /* IPI Vector/Priority 3 */ 751 u8 res17[12]; 752 u32 svr; /* Spurious Vector */ 753 u8 res18[12]; 754 u32 tfrr; /* Timer Frequency Reporting */ 755 u8 res19[12]; 756 u32 gtccr0; /* Global Timer Current Count 0 */ 757 u8 res20[12]; 758 u32 gtbcr0; /* Global Timer Base Count 0 */ 759 u8 res21[12]; 760 u32 gtvpr0; /* Global Timer Vector/Priority 0 */ 761 u8 res22[12]; 762 u32 gtdr0; /* Global Timer Destination 0 */ 763 u8 res23[12]; 764 u32 gtccr1; /* Global Timer Current Count 1 */ 765 u8 res24[12]; 766 u32 gtbcr1; /* Global Timer Base Count 1 */ 767 u8 res25[12]; 768 u32 gtvpr1; /* Global Timer Vector/Priority 1 */ 769 u8 res26[12]; 770 u32 gtdr1; /* Global Timer Destination 1 */ 771 u8 res27[12]; 772 u32 gtccr2; /* Global Timer Current Count 2 */ 773 u8 res28[12]; 774 u32 gtbcr2; /* Global Timer Base Count 2 */ 775 u8 res29[12]; 776 u32 gtvpr2; /* Global Timer Vector/Priority 2 */ 777 u8 res30[12]; 778 u32 gtdr2; /* Global Timer Destination 2 */ 779 u8 res31[12]; 780 u32 gtccr3; /* Global Timer Current Count 3 */ 781 u8 res32[12]; 782 u32 gtbcr3; /* Global Timer Base Count 3 */ 783 u8 res33[12]; 784 u32 gtvpr3; /* Global Timer Vector/Priority 3 */ 785 u8 res34[12]; 786 u32 gtdr3; /* Global Timer Destination 3 */ 787 u8 res35[268]; 788 u32 tcr; /* Timer Control */ 789 u8 res36[12]; 790 u32 irqsr0; /* IRQ_OUT Summary 0 */ 791 u8 res37[12]; 792 u32 irqsr1; /* IRQ_OUT Summary 1 */ 793 u8 res38[12]; 794 u32 cisr0; /* Critical IRQ Summary 0 */ 795 u8 res39[12]; 796 u32 cisr1; /* Critical IRQ Summary 1 */ 797 u8 res40[188]; 798 u32 msgr0; /* Message 0 */ 799 u8 res41[12]; 800 u32 msgr1; /* Message 1 */ 801 u8 res42[12]; 802 u32 msgr2; /* Message 2 */ 803 u8 res43[12]; 804 u32 msgr3; /* Message 3 */ 805 u8 res44[204]; 806 u32 mer; /* Message Enable */ 807 u8 res45[12]; 808 u32 msr; /* Message Status */ 809 u8 res46[60140]; 810 u32 eivpr0; /* External IRQ Vector/Priority 0 */ 811 u8 res47[12]; 812 u32 eidr0; /* External IRQ Destination 0 */ 813 u8 res48[12]; 814 u32 eivpr1; /* External IRQ Vector/Priority 1 */ 815 u8 res49[12]; 816 u32 eidr1; /* External IRQ Destination 1 */ 817 u8 res50[12]; 818 u32 eivpr2; /* External IRQ Vector/Priority 2 */ 819 u8 res51[12]; 820 u32 eidr2; /* External IRQ Destination 2 */ 821 u8 res52[12]; 822 u32 eivpr3; /* External IRQ Vector/Priority 3 */ 823 u8 res53[12]; 824 u32 eidr3; /* External IRQ Destination 3 */ 825 u8 res54[12]; 826 u32 eivpr4; /* External IRQ Vector/Priority 4 */ 827 u8 res55[12]; 828 u32 eidr4; /* External IRQ Destination 4 */ 829 u8 res56[12]; 830 u32 eivpr5; /* External IRQ Vector/Priority 5 */ 831 u8 res57[12]; 832 u32 eidr5; /* External IRQ Destination 5 */ 833 u8 res58[12]; 834 u32 eivpr6; /* External IRQ Vector/Priority 6 */ 835 u8 res59[12]; 836 u32 eidr6; /* External IRQ Destination 6 */ 837 u8 res60[12]; 838 u32 eivpr7; /* External IRQ Vector/Priority 7 */ 839 u8 res61[12]; 840 u32 eidr7; /* External IRQ Destination 7 */ 841 u8 res62[12]; 842 u32 eivpr8; /* External IRQ Vector/Priority 8 */ 843 u8 res63[12]; 844 u32 eidr8; /* External IRQ Destination 8 */ 845 u8 res64[12]; 846 u32 eivpr9; /* External IRQ Vector/Priority 9 */ 847 u8 res65[12]; 848 u32 eidr9; /* External IRQ Destination 9 */ 849 u8 res66[12]; 850 u32 eivpr10; /* External IRQ Vector/Priority 10 */ 851 u8 res67[12]; 852 u32 eidr10; /* External IRQ Destination 10 */ 853 u8 res68[12]; 854 u32 eivpr11; /* External IRQ Vector/Priority 11 */ 855 u8 res69[12]; 856 u32 eidr11; /* External IRQ Destination 11 */ 857 u8 res70[140]; 858 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ 859 u8 res71[12]; 860 u32 iidr0; /* Internal IRQ Destination 0 */ 861 u8 res72[12]; 862 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ 863 u8 res73[12]; 864 u32 iidr1; /* Internal IRQ Destination 1 */ 865 u8 res74[12]; 866 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ 867 u8 res75[12]; 868 u32 iidr2; /* Internal IRQ Destination 2 */ 869 u8 res76[12]; 870 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ 871 u8 res77[12]; 872 u32 iidr3; /* Internal IRQ Destination 3 */ 873 u8 res78[12]; 874 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ 875 u8 res79[12]; 876 u32 iidr4; /* Internal IRQ Destination 4 */ 877 u8 res80[12]; 878 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ 879 u8 res81[12]; 880 u32 iidr5; /* Internal IRQ Destination 5 */ 881 u8 res82[12]; 882 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ 883 u8 res83[12]; 884 u32 iidr6; /* Internal IRQ Destination 6 */ 885 u8 res84[12]; 886 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ 887 u8 res85[12]; 888 u32 iidr7; /* Internal IRQ Destination 7 */ 889 u8 res86[12]; 890 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ 891 u8 res87[12]; 892 u32 iidr8; /* Internal IRQ Destination 8 */ 893 u8 res88[12]; 894 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ 895 u8 res89[12]; 896 u32 iidr9; /* Internal IRQ Destination 9 */ 897 u8 res90[12]; 898 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ 899 u8 res91[12]; 900 u32 iidr10; /* Internal IRQ Destination 10 */ 901 u8 res92[12]; 902 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ 903 u8 res93[12]; 904 u32 iidr11; /* Internal IRQ Destination 11 */ 905 u8 res94[12]; 906 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ 907 u8 res95[12]; 908 u32 iidr12; /* Internal IRQ Destination 12 */ 909 u8 res96[12]; 910 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ 911 u8 res97[12]; 912 u32 iidr13; /* Internal IRQ Destination 13 */ 913 u8 res98[12]; 914 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ 915 u8 res99[12]; 916 u32 iidr14; /* Internal IRQ Destination 14 */ 917 u8 res100[12]; 918 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ 919 u8 res101[12]; 920 u32 iidr15; /* Internal IRQ Destination 15 */ 921 u8 res102[12]; 922 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ 923 u8 res103[12]; 924 u32 iidr16; /* Internal IRQ Destination 16 */ 925 u8 res104[12]; 926 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ 927 u8 res105[12]; 928 u32 iidr17; /* Internal IRQ Destination 17 */ 929 u8 res106[12]; 930 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ 931 u8 res107[12]; 932 u32 iidr18; /* Internal IRQ Destination 18 */ 933 u8 res108[12]; 934 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ 935 u8 res109[12]; 936 u32 iidr19; /* Internal IRQ Destination 19 */ 937 u8 res110[12]; 938 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ 939 u8 res111[12]; 940 u32 iidr20; /* Internal IRQ Destination 20 */ 941 u8 res112[12]; 942 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ 943 u8 res113[12]; 944 u32 iidr21; /* Internal IRQ Destination 21 */ 945 u8 res114[12]; 946 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ 947 u8 res115[12]; 948 u32 iidr22; /* Internal IRQ Destination 22 */ 949 u8 res116[12]; 950 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ 951 u8 res117[12]; 952 u32 iidr23; /* Internal IRQ Destination 23 */ 953 u8 res118[12]; 954 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ 955 u8 res119[12]; 956 u32 iidr24; /* Internal IRQ Destination 24 */ 957 u8 res120[12]; 958 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ 959 u8 res121[12]; 960 u32 iidr25; /* Internal IRQ Destination 25 */ 961 u8 res122[12]; 962 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ 963 u8 res123[12]; 964 u32 iidr26; /* Internal IRQ Destination 26 */ 965 u8 res124[12]; 966 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ 967 u8 res125[12]; 968 u32 iidr27; /* Internal IRQ Destination 27 */ 969 u8 res126[12]; 970 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ 971 u8 res127[12]; 972 u32 iidr28; /* Internal IRQ Destination 28 */ 973 u8 res128[12]; 974 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ 975 u8 res129[12]; 976 u32 iidr29; /* Internal IRQ Destination 29 */ 977 u8 res130[12]; 978 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ 979 u8 res131[12]; 980 u32 iidr30; /* Internal IRQ Destination 30 */ 981 u8 res132[12]; 982 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ 983 u8 res133[12]; 984 u32 iidr31; /* Internal IRQ Destination 31 */ 985 u8 res134[4108]; 986 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ 987 u8 res135[12]; 988 u32 midr0; /* Messaging IRQ Destination 0 */ 989 u8 res136[12]; 990 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ 991 u8 res137[12]; 992 u32 midr1; /* Messaging IRQ Destination 1 */ 993 u8 res138[12]; 994 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ 995 u8 res139[12]; 996 u32 midr2; /* Messaging IRQ Destination 2 */ 997 u8 res140[12]; 998 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ 999 u8 res141[12]; 1000 u32 midr3; /* Messaging IRQ Destination 3 */ 1001 u8 res142[59852]; 1002 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ 1003 u8 res143[12]; 1004 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ 1005 u8 res144[12]; 1006 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ 1007 u8 res145[12]; 1008 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ 1009 u8 res146[12]; 1010 u32 ctpr0; /* Current Task Priority for Processor 0 */ 1011 u8 res147[12]; 1012 u32 whoami0; /* Who Am I for Processor 0 */ 1013 u8 res148[12]; 1014 u32 iack0; /* IRQ Acknowledge for Processor 0 */ 1015 u8 res149[12]; 1016 u32 eoi0; /* End Of IRQ for Processor 0 */ 1017 u8 res150[130892]; 1018 } ccsr_pic_t; 1019 1020 /* CPM Block */ 1021 #ifndef CONFIG_CPM2 1022 typedef struct ccsr_cpm { 1023 u8 res[262144]; 1024 } ccsr_cpm_t; 1025 #else 1026 /* 1027 * DPARM 1028 * General SIU 1029 */ 1030 typedef struct ccsr_cpm_siu { 1031 u8 res1[80]; 1032 u32 smaer; 1033 u32 smser; 1034 u32 smevr; 1035 u8 res2[4]; 1036 u32 lmaer; 1037 u32 lmser; 1038 u32 lmevr; 1039 u8 res3[2964]; 1040 } ccsr_cpm_siu_t; 1041 1042 /* IRQ Controller */ 1043 typedef struct ccsr_cpm_intctl { 1044 u16 sicr; 1045 u8 res1[2]; 1046 u32 sivec; 1047 u32 sipnrh; 1048 u32 sipnrl; 1049 u32 siprr; 1050 u32 scprrh; 1051 u32 scprrl; 1052 u32 simrh; 1053 u32 simrl; 1054 u32 siexr; 1055 u8 res2[88]; 1056 u32 sccr; 1057 u8 res3[124]; 1058 } ccsr_cpm_intctl_t; 1059 1060 /* input/output port */ 1061 typedef struct ccsr_cpm_iop { 1062 u32 pdira; 1063 u32 ppara; 1064 u32 psora; 1065 u32 podra; 1066 u32 pdata; 1067 u8 res1[12]; 1068 u32 pdirb; 1069 u32 pparb; 1070 u32 psorb; 1071 u32 podrb; 1072 u32 pdatb; 1073 u8 res2[12]; 1074 u32 pdirc; 1075 u32 pparc; 1076 u32 psorc; 1077 u32 podrc; 1078 u32 pdatc; 1079 u8 res3[12]; 1080 u32 pdird; 1081 u32 ppard; 1082 u32 psord; 1083 u32 podrd; 1084 u32 pdatd; 1085 u8 res4[12]; 1086 } ccsr_cpm_iop_t; 1087 1088 /* CPM timers */ 1089 typedef struct ccsr_cpm_timer { 1090 u8 tgcr1; 1091 u8 res1[3]; 1092 u8 tgcr2; 1093 u8 res2[11]; 1094 u16 tmr1; 1095 u16 tmr2; 1096 u16 trr1; 1097 u16 trr2; 1098 u16 tcr1; 1099 u16 tcr2; 1100 u16 tcn1; 1101 u16 tcn2; 1102 u16 tmr3; 1103 u16 tmr4; 1104 u16 trr3; 1105 u16 trr4; 1106 u16 tcr3; 1107 u16 tcr4; 1108 u16 tcn3; 1109 u16 tcn4; 1110 u16 ter1; 1111 u16 ter2; 1112 u16 ter3; 1113 u16 ter4; 1114 u8 res3[608]; 1115 } ccsr_cpm_timer_t; 1116 1117 /* SDMA */ 1118 typedef struct ccsr_cpm_sdma { 1119 u8 sdsr; 1120 u8 res1[3]; 1121 u8 sdmr; 1122 u8 res2[739]; 1123 } ccsr_cpm_sdma_t; 1124 1125 /* FCC1 */ 1126 typedef struct ccsr_cpm_fcc1 { 1127 u32 gfmr; 1128 u32 fpsmr; 1129 u16 ftodr; 1130 u8 res1[2]; 1131 u16 fdsr; 1132 u8 res2[2]; 1133 u16 fcce; 1134 u8 res3[2]; 1135 u16 fccm; 1136 u8 res4[2]; 1137 u8 fccs; 1138 u8 res5[3]; 1139 u8 ftirr_phy[4]; 1140 } ccsr_cpm_fcc1_t; 1141 1142 /* FCC2 */ 1143 typedef struct ccsr_cpm_fcc2 { 1144 u32 gfmr; 1145 u32 fpsmr; 1146 u16 ftodr; 1147 u8 res1[2]; 1148 u16 fdsr; 1149 u8 res2[2]; 1150 u16 fcce; 1151 u8 res3[2]; 1152 u16 fccm; 1153 u8 res4[2]; 1154 u8 fccs; 1155 u8 res5[3]; 1156 u8 ftirr_phy[4]; 1157 } ccsr_cpm_fcc2_t; 1158 1159 /* FCC3 */ 1160 typedef struct ccsr_cpm_fcc3 { 1161 u32 gfmr; 1162 u32 fpsmr; 1163 u16 ftodr; 1164 u8 res1[2]; 1165 u16 fdsr; 1166 u8 res2[2]; 1167 u16 fcce; 1168 u8 res3[2]; 1169 u16 fccm; 1170 u8 res4[2]; 1171 u8 fccs; 1172 u8 res5[3]; 1173 u8 res[36]; 1174 } ccsr_cpm_fcc3_t; 1175 1176 /* FCC1 extended */ 1177 typedef struct ccsr_cpm_fcc1_ext { 1178 u32 firper; 1179 u32 firer; 1180 u32 firsr_h; 1181 u32 firsr_l; 1182 u8 gfemr; 1183 u8 res[15]; 1184 1185 } ccsr_cpm_fcc1_ext_t; 1186 1187 /* FCC2 extended */ 1188 typedef struct ccsr_cpm_fcc2_ext { 1189 u32 firper; 1190 u32 firer; 1191 u32 firsr_h; 1192 u32 firsr_l; 1193 u8 gfemr; 1194 u8 res[31]; 1195 } ccsr_cpm_fcc2_ext_t; 1196 1197 /* FCC3 extended */ 1198 typedef struct ccsr_cpm_fcc3_ext { 1199 u8 gfemr; 1200 u8 res[47]; 1201 } ccsr_cpm_fcc3_ext_t; 1202 1203 /* TC layers */ 1204 typedef struct ccsr_cpm_tmp1 { 1205 u8 res[496]; 1206 } ccsr_cpm_tmp1_t; 1207 1208 /* BRGs:5,6,7,8 */ 1209 typedef struct ccsr_cpm_brg2 { 1210 u32 brgc5; 1211 u32 brgc6; 1212 u32 brgc7; 1213 u32 brgc8; 1214 u8 res[608]; 1215 } ccsr_cpm_brg2_t; 1216 1217 /* I2C */ 1218 typedef struct ccsr_cpm_i2c { 1219 u8 i2mod; 1220 u8 res1[3]; 1221 u8 i2add; 1222 u8 res2[3]; 1223 u8 i2brg; 1224 u8 res3[3]; 1225 u8 i2com; 1226 u8 res4[3]; 1227 u8 i2cer; 1228 u8 res5[3]; 1229 u8 i2cmr; 1230 u8 res6[331]; 1231 } ccsr_cpm_i2c_t; 1232 1233 /* CPM core */ 1234 typedef struct ccsr_cpm_cp { 1235 u32 cpcr; 1236 u32 rccr; 1237 u8 res1[14]; 1238 u16 rter; 1239 u8 res2[2]; 1240 u16 rtmr; 1241 u16 rtscr; 1242 u8 res3[2]; 1243 u32 rtsr; 1244 u8 res4[12]; 1245 } ccsr_cpm_cp_t; 1246 1247 /* BRGs:1,2,3,4 */ 1248 typedef struct ccsr_cpm_brg1 { 1249 u32 brgc1; 1250 u32 brgc2; 1251 u32 brgc3; 1252 u32 brgc4; 1253 } ccsr_cpm_brg1_t; 1254 1255 /* SCC1-SCC4 */ 1256 typedef struct ccsr_cpm_scc { 1257 u32 gsmrl; 1258 u32 gsmrh; 1259 u16 psmr; 1260 u8 res1[2]; 1261 u16 todr; 1262 u16 dsr; 1263 u16 scce; 1264 u8 res2[2]; 1265 u16 sccm; 1266 u8 res3; 1267 u8 sccs; 1268 u8 res4[8]; 1269 } ccsr_cpm_scc_t; 1270 1271 typedef struct ccsr_cpm_tmp2 { 1272 u8 res[32]; 1273 } ccsr_cpm_tmp2_t; 1274 1275 /* SPI */ 1276 typedef struct ccsr_cpm_spi { 1277 u16 spmode; 1278 u8 res1[4]; 1279 u8 spie; 1280 u8 res2[3]; 1281 u8 spim; 1282 u8 res3[2]; 1283 u8 spcom; 1284 u8 res4[82]; 1285 } ccsr_cpm_spi_t; 1286 1287 /* CPM MUX */ 1288 typedef struct ccsr_cpm_mux { 1289 u8 cmxsi1cr; 1290 u8 res1; 1291 u8 cmxsi2cr; 1292 u8 res2; 1293 u32 cmxfcr; 1294 u32 cmxscr; 1295 u8 res3[2]; 1296 u16 cmxuar; 1297 u8 res4[16]; 1298 } ccsr_cpm_mux_t; 1299 1300 /* SI,MCC,etc */ 1301 typedef struct ccsr_cpm_tmp3 { 1302 u8 res[58592]; 1303 } ccsr_cpm_tmp3_t; 1304 1305 typedef struct ccsr_cpm_iram { 1306 u32 iram[8192]; 1307 u8 res[98304]; 1308 } ccsr_cpm_iram_t; 1309 1310 typedef struct ccsr_cpm { 1311 /* Some references are into the unique & known dpram spaces, 1312 * others are from the generic base. 1313 */ 1314 #define im_dprambase im_dpram1 1315 u8 im_dpram1[16*1024]; 1316 u8 res1[16*1024]; 1317 u8 im_dpram2[16*1024]; 1318 u8 res2[16*1024]; 1319 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ 1320 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ 1321 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ 1322 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ 1323 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ 1324 ccsr_cpm_fcc1_t im_cpm_fcc1; 1325 ccsr_cpm_fcc2_t im_cpm_fcc2; 1326 ccsr_cpm_fcc3_t im_cpm_fcc3; 1327 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; 1328 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; 1329 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; 1330 ccsr_cpm_tmp1_t im_cpm_tmp1; 1331 ccsr_cpm_brg2_t im_cpm_brg2; 1332 ccsr_cpm_i2c_t im_cpm_i2c; 1333 ccsr_cpm_cp_t im_cpm_cp; 1334 ccsr_cpm_brg1_t im_cpm_brg1; 1335 ccsr_cpm_scc_t im_cpm_scc[4]; 1336 ccsr_cpm_tmp2_t im_cpm_tmp2; 1337 ccsr_cpm_spi_t im_cpm_spi; 1338 ccsr_cpm_mux_t im_cpm_mux; 1339 ccsr_cpm_tmp3_t im_cpm_tmp3; 1340 ccsr_cpm_iram_t im_cpm_iram; 1341 } ccsr_cpm_t; 1342 #endif 1343 1344 /* RapidIO Registers */ 1345 typedef struct ccsr_rio { 1346 u32 didcar; /* Device Identity Capability */ 1347 u32 dicar; /* Device Information Capability */ 1348 u32 aidcar; /* Assembly Identity Capability */ 1349 u32 aicar; /* Assembly Information Capability */ 1350 u32 pefcar; /* Processing Element Features Capability */ 1351 u32 spicar; /* Switch Port Information Capability */ 1352 u32 socar; /* Source Operations Capability */ 1353 u32 docar; /* Destination Operations Capability */ 1354 u8 res1[32]; 1355 u32 msr; /* Mailbox Cmd And Status */ 1356 u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ 1357 u8 res2[4]; 1358 u32 pellccsr; /* Processing Element Logic Layer CCSR */ 1359 u8 res3[12]; 1360 u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ 1361 u32 bdidcsr; /* Base Device ID Cmd & Status */ 1362 u8 res4[4]; 1363 u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ 1364 u32 ctcsr; /* Component Tag Cmd & Status */ 1365 u8 res5[144]; 1366 u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ 1367 u8 res6[28]; 1368 u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ 1369 u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ 1370 u8 res7[20]; 1371 u32 pgccsr; /* Port General Cmd & Status */ 1372 u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ 1373 u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ 1374 u32 plascsr; /* Port Local Ackid Status Cmd & Status */ 1375 u8 res8[12]; 1376 u32 pescsr; /* Port Error & Status Cmd & Status */ 1377 u32 pccsr; /* Port Control Cmd & Status */ 1378 u8 res9[65184]; 1379 u32 cr; /* Port Control Cmd & Status */ 1380 u8 res10[12]; 1381 u32 pcr; /* Port Configuration */ 1382 u32 peir; /* Port Error Injection */ 1383 u8 res11[3048]; 1384 u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ 1385 u8 res12[12]; 1386 u32 rowar0; /* RIO Outbound Attrs 0 */ 1387 u8 res13[12]; 1388 u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ 1389 u8 res14[4]; 1390 u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ 1391 u8 res15[4]; 1392 u32 rowar1; /* RIO Outbound Attrs 1 */ 1393 u8 res16[12]; 1394 u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ 1395 u8 res17[4]; 1396 u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ 1397 u8 res18[4]; 1398 u32 rowar2; /* RIO Outbound Attrs 2 */ 1399 u8 res19[12]; 1400 u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ 1401 u8 res20[4]; 1402 u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ 1403 u8 res21[4]; 1404 u32 rowar3; /* RIO Outbound Attrs 3 */ 1405 u8 res22[12]; 1406 u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ 1407 u8 res23[4]; 1408 u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ 1409 u8 res24[4]; 1410 u32 rowar4; /* RIO Outbound Attrs 4 */ 1411 u8 res25[12]; 1412 u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ 1413 u8 res26[4]; 1414 u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ 1415 u8 res27[4]; 1416 u32 rowar5; /* RIO Outbound Attrs 5 */ 1417 u8 res28[12]; 1418 u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ 1419 u8 res29[4]; 1420 u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ 1421 u8 res30[4]; 1422 u32 rowar6; /* RIO Outbound Attrs 6 */ 1423 u8 res31[12]; 1424 u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ 1425 u8 res32[4]; 1426 u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ 1427 u8 res33[4]; 1428 u32 rowar7; /* RIO Outbound Attrs 7 */ 1429 u8 res34[12]; 1430 u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ 1431 u8 res35[4]; 1432 u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ 1433 u8 res36[4]; 1434 u32 rowar8; /* RIO Outbound Attrs 8 */ 1435 u8 res37[76]; 1436 u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ 1437 u8 res38[4]; 1438 u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ 1439 u8 res39[4]; 1440 u32 riwar4; /* RIO Inbound Attrs 4 */ 1441 u8 res40[12]; 1442 u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ 1443 u8 res41[4]; 1444 u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ 1445 u8 res42[4]; 1446 u32 riwar3; /* RIO Inbound Attrs 3 */ 1447 u8 res43[12]; 1448 u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ 1449 u8 res44[4]; 1450 u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ 1451 u8 res45[4]; 1452 u32 riwar2; /* RIO Inbound Attrs 2 */ 1453 u8 res46[12]; 1454 u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ 1455 u8 res47[4]; 1456 u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ 1457 u8 res48[4]; 1458 u32 riwar1; /* RIO Inbound Attrs 1 */ 1459 u8 res49[12]; 1460 u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ 1461 u8 res50[12]; 1462 u32 riwar0; /* RIO Inbound Attrs 0 */ 1463 u8 res51[12]; 1464 u32 pnfedr; /* Port Notification/Fatal Error Detect */ 1465 u32 pnfedir; /* Port Notification/Fatal Error Detect */ 1466 u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ 1467 u32 pecr; /* Port Error Control */ 1468 u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ 1469 u32 pepr1; /* Port Error Packet 1 */ 1470 u32 pepr2; /* Port Error Packet 2 */ 1471 u8 res52[4]; 1472 u32 predr; /* Port Recoverable Error Detect */ 1473 u8 res53[4]; 1474 u32 pertr; /* Port Error Recovery Threshold */ 1475 u32 prtr; /* Port Retry Threshold */ 1476 u8 res54[464]; 1477 u32 omr; /* Outbound Mode */ 1478 u32 osr; /* Outbound Status */ 1479 u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ 1480 u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ 1481 u32 eosar; /* Extended Outbound Unit Source Addr */ 1482 u32 osar; /* Outbound Unit Source Addr */ 1483 u32 odpr; /* Outbound Destination Port */ 1484 u32 odatr; /* Outbound Destination Attrs */ 1485 u32 odcr; /* Outbound Doubleword Count */ 1486 u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ 1487 u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ 1488 u8 res55[52]; 1489 u32 imr; /* Outbound Mode */ 1490 u32 isr; /* Inbound Status */ 1491 u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ 1492 u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ 1493 u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ 1494 u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ 1495 u8 res56[1000]; 1496 u32 dmr; /* Doorbell Mode */ 1497 u32 dsr; /* Doorbell Status */ 1498 u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ 1499 u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ 1500 u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ 1501 u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ 1502 u8 res57[104]; 1503 u32 pwmr; /* Port-Write Mode */ 1504 u32 pwsr; /* Port-Write Status */ 1505 u32 epwqbar; /* Extended Port-Write Queue Base Addr */ 1506 u32 pwqbar; /* Port-Write Queue Base Addr */ 1507 u8 res58[60176]; 1508 } ccsr_rio_t; 1509 1510 /* Quick Engine Block Pin Muxing Registers */ 1511 typedef struct par_io { 1512 u32 cpodr; 1513 u32 cpdat; 1514 u32 cpdir1; 1515 u32 cpdir2; 1516 u32 cppar1; 1517 u32 cppar2; 1518 u8 res[8]; 1519 } par_io_t; 1520 1521 #ifdef CONFIG_SYS_FSL_CPC 1522 /* 1523 * Define a single offset that is the start of all the CPC register 1524 * blocks - if there is more than one CPC, we expect these to be 1525 * contiguous 4k regions 1526 */ 1527 1528 typedef struct cpc_corenet { 1529 u32 cpccsr0; /* Config/status reg */ 1530 u32 res1; 1531 u32 cpccfg0; /* Configuration register */ 1532 u32 res2; 1533 u32 cpcewcr0; /* External Write reg 0 */ 1534 u32 cpcewabr0; /* External write base reg 0 */ 1535 u32 res3[2]; 1536 u32 cpcewcr1; /* External Write reg 1 */ 1537 u32 cpcewabr1; /* External write base reg 1 */ 1538 u32 res4[54]; 1539 u32 cpcsrcr1; /* SRAM control reg 1 */ 1540 u32 cpcsrcr0; /* SRAM control reg 0 */ 1541 u32 res5[62]; 1542 struct { 1543 u32 id; /* partition ID */ 1544 u32 res; 1545 u32 alloc; /* partition allocation */ 1546 u32 way; /* partition way */ 1547 } partition_regs[16]; 1548 u32 res6[704]; 1549 u32 cpcerrinjhi; /* Error injection high */ 1550 u32 cpcerrinjlo; /* Error injection lo */ 1551 u32 cpcerrinjctl; /* Error injection control */ 1552 u32 res7[5]; 1553 u32 cpccaptdatahi; /* capture data high */ 1554 u32 cpccaptdatalo; /* capture data low */ 1555 u32 cpcaptecc; /* capture ECC */ 1556 u32 res8[5]; 1557 u32 cpcerrdet; /* error detect */ 1558 u32 cpcerrdis; /* error disable */ 1559 u32 cpcerrinten; /* errir interrupt enable */ 1560 u32 cpcerrattr; /* error attribute */ 1561 u32 cpcerreaddr; /* error extended address */ 1562 u32 cpcerraddr; /* error address */ 1563 u32 cpcerrctl; /* error control */ 1564 u32 res9[105]; /* pad out to 4k */ 1565 } cpc_corenet_t; 1566 1567 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ 1568 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */ 1569 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ 1570 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */ 1571 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ 1572 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ 1573 #define CPC_CFG0_SZ_MASK 0x00003fff 1574 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) 1575 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) 1576 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) 1577 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff 1578 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ 1579 & CPC_SRCR1_SRBARU_MASK) 1580 #define CPC_SRCR0_SRBARL_MASK 0xffff8000 1581 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) 1582 #define CPC_SRCR0_INTLVEN 0x00000100 1583 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 1584 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 1585 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 1586 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 1587 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 1588 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a 1589 #define CPC_SRCR0_SRAMEN 0x00000001 1590 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ 1591 #endif /* CONFIG_SYS_FSL_CPC */ 1592 1593 /* Global Utilities Block */ 1594 #ifdef CONFIG_FSL_CORENET 1595 typedef struct ccsr_gur { 1596 u32 porsr1; /* POR status */ 1597 u8 res1[28]; 1598 u32 gpporcr1; /* General-purpose POR configuration */ 1599 u8 res2[12]; 1600 u32 gpiocr; /* GPIO control */ 1601 u8 res3[12]; 1602 u32 gpoutdr; /* General-purpose output data */ 1603 u8 res4[12]; 1604 u32 gpindr; /* General-purpose input data */ 1605 u8 res5[12]; 1606 u32 alt_pmuxcr; /* Alt function signal multiplex control */ 1607 u8 res6[12]; 1608 u32 devdisr; /* Device disable control */ 1609 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 1610 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 1611 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 1612 #define FSL_CORENET_DEVDISR_RMU 0x08000000 1613 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000 1614 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000 1615 #define FSL_CORENET_DEVDISR_DMA1 0x00400000 1616 #define FSL_CORENET_DEVDISR_DMA2 0x00200000 1617 #define FSL_CORENET_DEVDISR_DDR1 0x00100000 1618 #define FSL_CORENET_DEVDISR_DDR2 0x00080000 1619 #define FSL_CORENET_DEVDISR_DBG 0x00010000 1620 #define FSL_CORENET_DEVDISR_NAL 0x00008000 1621 #define FSL_CORENET_DEVDISR_ELBC 0x00001000 1622 #define FSL_CORENET_DEVDISR_USB1 0x00000800 1623 #define FSL_CORENET_DEVDISR_USB2 0x00000400 1624 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100 1625 #define FSL_CORENET_DEVDISR_GPIO 0x00000080 1626 #define FSL_CORENET_DEVDISR_ESPI 0x00000040 1627 #define FSL_CORENET_DEVDISR_I2C1 0x00000020 1628 #define FSL_CORENET_DEVDISR_I2C2 0x00000010 1629 #define FSL_CORENET_DEVDISR_DUART1 0x00000002 1630 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 1631 u32 devdisr2; /* Device disable control 2 */ 1632 #define FSL_CORENET_DEVDISR2_PME 0x80000000 1633 #define FSL_CORENET_DEVDISR2_SEC 0x40000000 1634 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000 1635 #define FSL_CORENET_DEVDISR2_FM1 0x02000000 1636 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000 1637 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000 1638 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 1639 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 1640 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 1641 #define FSL_CORENET_DEVDISR2_FM2 0x00020000 1642 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 1643 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 1644 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 1645 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 1646 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 1647 u8 res7[8]; 1648 u32 powmgtcsr; /* Power management status & control */ 1649 u8 res8[12]; 1650 u32 coredisru; /* uppper portion for support of 64 cores */ 1651 u32 coredisrl; /* lower portion for support of 64 cores */ 1652 u8 res9[8]; 1653 u32 pvr; /* Processor version */ 1654 u32 svr; /* System version */ 1655 u8 res10[8]; 1656 u32 rstcr; /* Reset control */ 1657 u32 rstrqpblsr; /* Reset request preboot loader status */ 1658 u8 res11[8]; 1659 u32 rstrqmr1; /* Reset request mask */ 1660 u8 res12[4]; 1661 u32 rstrqsr1; /* Reset request status */ 1662 u8 res13[4]; 1663 u8 res14[4]; 1664 u32 rstrqwdtmrl; /* Reset request WDT mask */ 1665 u8 res15[4]; 1666 u32 rstrqwdtsrl; /* Reset request WDT status */ 1667 u8 res16[4]; 1668 u32 brrl; /* Boot release */ 1669 u8 res17[24]; 1670 u32 rcwsr[16]; /* Reset control word status */ 1671 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 1672 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 1673 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 1674 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 1675 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 1676 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 1677 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 1678 u8 res18[192]; 1679 u32 scratchrw[4]; /* Scratch Read/Write */ 1680 u8 res19[240]; 1681 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 1682 u8 res20[240]; 1683 u32 scrtsr[8]; /* Core reset status */ 1684 u8 res21[224]; 1685 u32 pex1liodnr; /* PCI Express 1 LIODN */ 1686 u32 pex2liodnr; /* PCI Express 2 LIODN */ 1687 u32 pex3liodnr; /* PCI Express 3 LIODN */ 1688 u32 pex4liodnr; /* PCI Express 4 LIODN */ 1689 u32 rio1liodnr; /* RIO 1 LIODN */ 1690 u32 rio2liodnr; /* RIO 2 LIODN */ 1691 u32 rio3liodnr; /* RIO 3 LIODN */ 1692 u32 rio4liodnr; /* RIO 4 LIODN */ 1693 u32 usb1liodnr; /* USB 1 LIODN */ 1694 u32 usb2liodnr; /* USB 2 LIODN */ 1695 u32 usb3liodnr; /* USB 3 LIODN */ 1696 u32 usb4liodnr; /* USB 4 LIODN */ 1697 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ 1698 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ 1699 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ 1700 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ 1701 u32 rmuliodnr; /* RIO Message Unit LIODN */ 1702 u32 rduliodnr; /* RIO Doorbell Unit LIODN */ 1703 u32 rpwuliodnr; /* RIO Port Write Unit LIODN */ 1704 u8 res22[52]; 1705 u32 dma1liodnr; /* DMA 1 LIODN */ 1706 u32 dma2liodnr; /* DMA 2 LIODN */ 1707 u32 dma3liodnr; /* DMA 3 LIODN */ 1708 u32 dma4liodnr; /* DMA 4 LIODN */ 1709 u8 res23[48]; 1710 u8 res24[64]; 1711 u32 pblsr; /* Preboot loader status */ 1712 u32 pamubypenr; /* PAMU bypass enable */ 1713 u32 dmacr1; /* DMA control */ 1714 u8 res25[4]; 1715 u32 gensr1; /* General status */ 1716 u8 res26[12]; 1717 u32 gencr1; /* General control */ 1718 u8 res27[12]; 1719 u8 res28[4]; 1720 u32 cgensrl; /* Core general status */ 1721 u8 res29[8]; 1722 u8 res30[4]; 1723 u32 cgencrl; /* Core general control */ 1724 u8 res31[184]; 1725 u32 sriopstecr; /* SRIO prescaler timer enable control */ 1726 u8 res32[1788]; 1727 u32 pmuxcr; /* Pin multiplexing control */ 1728 u8 res33[60]; 1729 u32 iovselsr; /* I/O voltage selection status */ 1730 u8 res34[28]; 1731 u32 ddrclkdr; /* DDR clock disable */ 1732 u8 res35; 1733 u32 elbcclkdr; /* eLBC clock disable */ 1734 u8 res36[20]; 1735 u32 sdhcpcr; /* eSDHC polarity configuration */ 1736 u8 res37[380]; 1737 } ccsr_gur_t; 1738 1739 typedef struct ccsr_clk { 1740 u32 clkc0csr; /* Core 0 Clock control/status */ 1741 u8 res1[0x1c]; 1742 u32 clkc1csr; /* Core 1 Clock control/status */ 1743 u8 res2[0x1c]; 1744 u32 clkc2csr; /* Core 2 Clock control/status */ 1745 u8 res3[0x1c]; 1746 u32 clkc3csr; /* Core 3 Clock control/status */ 1747 u8 res4[0x1c]; 1748 u32 clkc4csr; /* Core 4 Clock control/status */ 1749 u8 res5[0x1c]; 1750 u32 clkc5csr; /* Core 5 Clock control/status */ 1751 u8 res6[0x1c]; 1752 u32 clkc6csr; /* Core 6 Clock control/status */ 1753 u8 res7[0x1c]; 1754 u32 clkc7csr; /* Core 7 Clock control/status */ 1755 u8 res8[0x71c]; 1756 u32 pllc1gsr; /* Cluster PLL 1 General Status */ 1757 u8 res10[0x1c]; 1758 u32 pllc2gsr; /* Cluster PLL 2 General Status */ 1759 u8 res11[0x1c]; 1760 u32 pllc3gsr; /* Cluster PLL 3 General Status */ 1761 u8 res12[0x1c]; 1762 u32 pllc4gsr; /* Cluster PLL 4 General Status */ 1763 u8 res13[0x39c]; 1764 u32 pllpgsr; /* Platform PLL General Status */ 1765 u8 res14[0x1c]; 1766 u32 plldgsr; /* DDR PLL General Status */ 1767 u8 res15[0x3dc]; 1768 } ccsr_clk_t; 1769 1770 typedef struct ccsr_rcpm { 1771 u8 res1[4]; 1772 u32 cdozsrl; /* Core Doze Status */ 1773 u8 res2[4]; 1774 u32 cdozcrl; /* Core Doze Control */ 1775 u8 res3[4]; 1776 u32 cnapsrl; /* Core Nap Status */ 1777 u8 res4[4]; 1778 u32 cnapcrl; /* Core Nap Control */ 1779 u8 res5[4]; 1780 u32 cdozpsrl; /* Core Doze Previous Status */ 1781 u8 res6[4]; 1782 u32 cdozpcrl; /* Core Doze Previous Control */ 1783 u8 res7[4]; 1784 u32 cwaitsrl; /* Core Wait Status */ 1785 u8 res8[8]; 1786 u32 powmgtcsr; /* Power Mangement Control & Status */ 1787 u8 res9[12]; 1788 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ 1789 u8 res10[12]; 1790 u8 res11[4]; 1791 u32 cpmimrl; /* Core PM IRQ Masking */ 1792 u8 res12[4]; 1793 u32 cpmcimrl; /* Core PM Critical IRQ Masking */ 1794 u8 res13[4]; 1795 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ 1796 u8 res14[4]; 1797 u32 cpmnmimrl; /* Core PM NMI Masking */ 1798 u8 res15[4]; 1799 u32 ctbenrl; /* Core Time Base Enable */ 1800 u8 res16[4]; 1801 u32 ctbclkselrl; /* Core Time Base Clock Select */ 1802 u8 res17[4]; 1803 u32 ctbhltcrl; /* Core Time Base Halt Control */ 1804 u8 res18[0xf68]; 1805 } ccsr_rcpm_t; 1806 1807 #else 1808 typedef struct ccsr_gur { 1809 u32 porpllsr; /* POR PLL ratio status */ 1810 #ifdef CONFIG_MPC8536 1811 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 1812 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 1813 #else 1814 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 1815 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 1816 #endif 1817 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 1818 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 1819 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e 1820 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 1821 u32 porbmsr; /* POR boot mode status */ 1822 #define MPC85xx_PORBMSR_HA 0x00070000 1823 #define MPC85xx_PORBMSR_HA_SHIFT 16 1824 u32 porimpscr; /* POR I/O impedance status & control */ 1825 u32 pordevsr; /* POR I/O device status regsiter */ 1826 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 1827 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 1828 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 1829 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 1830 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 1831 #define MPC85xx_PORDEVSR_PCI1 0x00800000 1832 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 1833 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 1834 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 1835 #else 1836 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 1837 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 1838 #endif 1839 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 1840 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 1841 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 1842 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 1843 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 1844 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 1845 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 1846 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 1847 u32 pordbgmsr; /* POR debug mode status */ 1848 u32 pordevsr2; /* POR I/O device status 2 */ 1849 /* The 8544 RM says this is bit 26, but it's really bit 24 */ 1850 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 1851 u8 res1[8]; 1852 u32 gpporcr; /* General-purpose POR configuration */ 1853 u8 res2[12]; 1854 u32 gpiocr; /* GPIO control */ 1855 u8 res3[12]; 1856 #if defined(CONFIG_MPC8569) 1857 u32 plppar1; /* Platform port pin assignment 1 */ 1858 u32 plppar2; /* Platform port pin assignment 2 */ 1859 u32 plpdir1; /* Platform port pin direction 1 */ 1860 u32 plpdir2; /* Platform port pin direction 2 */ 1861 #else 1862 u32 gpoutdr; /* General-purpose output data */ 1863 u8 res4[12]; 1864 #endif 1865 u32 gpindr; /* General-purpose input data */ 1866 u8 res5[12]; 1867 u32 pmuxcr; /* Alt. function signal multiplex control */ 1868 #define MPC85xx_PMUXCR_SD_DATA 0x80000000 1869 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 1870 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 1871 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ 1872 u8 res6[8]; 1873 u32 devdisr; /* Device disable control */ 1874 #define MPC85xx_DEVDISR_PCI1 0x80000000 1875 #define MPC85xx_DEVDISR_PCI2 0x40000000 1876 #define MPC85xx_DEVDISR_PCIE 0x20000000 1877 #define MPC85xx_DEVDISR_LBC 0x08000000 1878 #define MPC85xx_DEVDISR_PCIE2 0x04000000 1879 #define MPC85xx_DEVDISR_PCIE3 0x02000000 1880 #define MPC85xx_DEVDISR_SEC 0x01000000 1881 #define MPC85xx_DEVDISR_SRIO 0x00080000 1882 #define MPC85xx_DEVDISR_RMSG 0x00040000 1883 #define MPC85xx_DEVDISR_DDR 0x00010000 1884 #define MPC85xx_DEVDISR_CPU 0x00008000 1885 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU 1886 #define MPC85xx_DEVDISR_TB 0x00004000 1887 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB 1888 #define MPC85xx_DEVDISR_CPU1 0x00002000 1889 #define MPC85xx_DEVDISR_TB1 0x00001000 1890 #define MPC85xx_DEVDISR_DMA 0x00000400 1891 #define MPC85xx_DEVDISR_TSEC1 0x00000080 1892 #define MPC85xx_DEVDISR_TSEC2 0x00000040 1893 #define MPC85xx_DEVDISR_TSEC3 0x00000020 1894 #define MPC85xx_DEVDISR_TSEC4 0x00000010 1895 #define MPC85xx_DEVDISR_I2C 0x00000004 1896 #define MPC85xx_DEVDISR_DUART 0x00000002 1897 u8 res7[12]; 1898 u32 powmgtcsr; /* Power management status & control */ 1899 u8 res8[12]; 1900 u32 mcpsumr; /* Machine check summary */ 1901 u8 res9[12]; 1902 u32 pvr; /* Processor version */ 1903 u32 svr; /* System version */ 1904 u8 res10a[8]; 1905 u32 rstcr; /* Reset control */ 1906 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) 1907 u8 res10b[76]; 1908 par_io_t qe_par_io[7]; 1909 u8 res10c[1600]; 1910 #else 1911 u8 res10b[1868]; 1912 #endif 1913 u32 clkdvdr; /* Clock Divide register */ 1914 u8 res10d[1532]; 1915 u32 clkocr; /* Clock out select */ 1916 u8 res11[12]; 1917 u32 ddrdllcr; /* DDR DLL control */ 1918 u8 res12[12]; 1919 u32 lbcdllcr; /* LBC DLL control */ 1920 u8 res13[248]; 1921 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ 1922 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ 1923 u32 ddrioovcr; /* DDR IO Override Control */ 1924 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ 1925 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ 1926 u8 res15[61648]; 1927 } ccsr_gur_t; 1928 #endif 1929 1930 typedef struct serdes_corenet { 1931 struct { 1932 u32 rstctl; /* Reset Control Register */ 1933 #define SRDS_RSTCTL_RST 0x80000000 1934 #define SRDS_RSTCTL_RSTDONE 0x40000000 1935 #define SRDS_RSTCTL_RSTERR 0x20000000 1936 #define SRDS_RSTCTL_SDPD 0x00000020 1937 u32 pllcr0; /* PLL Control Register 0 */ 1938 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000 1939 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 1940 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 1941 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 1942 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 1943 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 1944 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 1945 u32 pllcr1; /* PLL Control Register 1 */ 1946 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 1947 u32 res[5]; 1948 } bank[3]; 1949 u32 res1[12]; 1950 u32 srdstcalcr; /* TX Calibration Control */ 1951 u32 res2[3]; 1952 u32 srdsrcalcr; /* RX Calibration Control */ 1953 u32 res3[3]; 1954 u32 srdsgr0; /* General Register 0 */ 1955 u32 res4[11]; 1956 u32 srdspccr0; /* Protocol Converter Config 0 */ 1957 u32 srdspccr1; /* Protocol Converter Config 1 */ 1958 u32 srdspccr2; /* Protocol Converter Config 2 */ 1959 #define SRDS_PCCR2_RST_XGMII1 0x00800000 1960 #define SRDS_PCCR2_RST_XGMII2 0x00400000 1961 u32 res5[197]; 1962 struct { 1963 u32 gcr0; /* General Control Register 0 */ 1964 #define SRDS_GCR0_RRST 0x00400000 1965 #define SRDS_GCR0_1STLANE 0x00010000 1966 u32 gcr1; /* General Control Register 1 */ 1967 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 1968 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 1969 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 1970 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 1971 #define SRDS_GCR1_OPAD_CTL 0x04000000 1972 u32 res1[4]; 1973 u32 tecr0; /* TX Equalization Control Reg 0 */ 1974 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 1975 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 1976 u32 res3; 1977 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ 1978 u32 res4[7]; 1979 } lane[24]; 1980 u32 res6[384]; 1981 } serdes_corenet_t; 1982 1983 enum { 1984 FSL_SRDS_B1_LANE_A = 0, 1985 FSL_SRDS_B1_LANE_B = 1, 1986 FSL_SRDS_B1_LANE_C = 2, 1987 FSL_SRDS_B1_LANE_D = 3, 1988 FSL_SRDS_B1_LANE_E = 4, 1989 FSL_SRDS_B1_LANE_F = 5, 1990 FSL_SRDS_B1_LANE_G = 6, 1991 FSL_SRDS_B1_LANE_H = 7, 1992 FSL_SRDS_B1_LANE_I = 8, 1993 FSL_SRDS_B1_LANE_J = 9, 1994 FSL_SRDS_B2_LANE_A = 16, 1995 FSL_SRDS_B2_LANE_B = 17, 1996 FSL_SRDS_B2_LANE_C = 18, 1997 FSL_SRDS_B2_LANE_D = 19, 1998 FSL_SRDS_B3_LANE_A = 20, 1999 FSL_SRDS_B3_LANE_B = 21, 2000 FSL_SRDS_B3_LANE_C = 22, 2001 FSL_SRDS_B3_LANE_D = 23, 2002 }; 2003 2004 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ 2005 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 2006 typedef struct ccsr_sec { 2007 u8 res1[0xfa0]; 2008 u32 crnr_ms; /* CHA Revision Number Register, MS */ 2009 u32 crnr_ls; /* CHA Revision Number Register, LS */ 2010 u32 ctpr_ms; /* Compile Time Parameters Register, MS */ 2011 #define SEC_CTPR_MS_AXI_LIODN 0x08000000 2012 #define SEC_CTPR_MS_QI 0x02000000 2013 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ 2014 u8 res2[0x10]; 2015 u32 far_ms; /* Fault Address Register, MS */ 2016 u32 far_ls; /* Fault Address Register, LS */ 2017 u32 falr; /* Fault Address LIODN Register */ 2018 u32 fadr; /* Fault Address Detail Register */ 2019 u8 res3[0x4]; 2020 u32 csta; /* CAAM Status Register */ 2021 u8 res4[0x8]; 2022 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ 2023 #define SEC_RVID_MA 0x0f000000 2024 u32 ccbvid; /* CHA Cluster Block Version ID Register */ 2025 u32 chavid_ms; /* CHA Version ID Register, MS */ 2026 u32 chavid_ls; /* CHA Version ID Register, LS */ 2027 u32 chanum_ms; /* CHA Number Register, MS */ 2028 #define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 2029 #define SEC_CHANUM_MS_JQNUM_SHIFT 28 2030 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 2031 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 2032 u32 chanum_ls; /* CHA Number Register, LS */ 2033 u32 caamvid_ms; /* CAAM Version ID Register, MS */ 2034 u32 caamvid_ls; /* CAAM Version ID Register, LS */ 2035 u8 res5[0xf000]; 2036 } ccsr_sec_t; 2037 #endif 2038 2039 #ifdef CONFIG_FSL_CORENET 2040 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 2041 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 2042 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 2043 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 2044 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 2045 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 2046 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 2047 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 2048 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 2049 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 2050 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 2051 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 2052 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 2053 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 2054 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 2055 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 2056 #define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */ 2057 #else 2058 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 2059 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 2060 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 2061 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 2062 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 2063 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 2064 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 2065 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 2066 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 2067 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 2068 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 2069 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) 2070 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 2071 #else 2072 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 2073 #endif 2074 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 2075 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 2076 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 2077 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 2078 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 2079 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 2080 #ifdef CONFIG_TSECV2 2081 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 2082 #else 2083 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 2084 #endif 2085 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 2086 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 2087 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 2088 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 2089 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 2090 #endif 2091 2092 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 2093 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 2094 2095 #define CONFIG_SYS_FSL_CPC_ADDR \ 2096 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) 2097 #define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ 2098 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) 2099 #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ 2100 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) 2101 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ 2102 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) 2103 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ 2104 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) 2105 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ 2106 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) 2107 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ 2108 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) 2109 #define CONFIG_SYS_MPC85xx_ECM_ADDR \ 2110 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) 2111 #define CONFIG_SYS_MPC85xx_DDR_ADDR \ 2112 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) 2113 #define CONFIG_SYS_MPC85xx_DDR2_ADDR \ 2114 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) 2115 #define CONFIG_SYS_LBC_ADDR \ 2116 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) 2117 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ 2118 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) 2119 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ 2120 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) 2121 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ 2122 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) 2123 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \ 2124 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) 2125 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \ 2126 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) 2127 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \ 2128 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) 2129 #define CONFIG_SYS_MPC85xx_L2_ADDR \ 2130 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) 2131 #define CONFIG_SYS_MPC85xx_DMA_ADDR \ 2132 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) 2133 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ 2134 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) 2135 #define CONFIG_SYS_MPC85xx_PIC_ADDR \ 2136 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) 2137 #define CONFIG_SYS_MPC85xx_CPM_ADDR \ 2138 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) 2139 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ 2140 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 2141 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ 2142 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 2143 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ 2144 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) 2145 #define CONFIG_SYS_MPC85xx_USB_ADDR \ 2146 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) 2147 #define CONFIG_SYS_FSL_SEC_ADDR \ 2148 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 2149 2150 #define CONFIG_SYS_PCI1_ADDR \ 2151 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) 2152 #define CONFIG_SYS_PCI2_ADDR \ 2153 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) 2154 #define CONFIG_SYS_PCIE1_ADDR \ 2155 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) 2156 #define CONFIG_SYS_PCIE2_ADDR \ 2157 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) 2158 #define CONFIG_SYS_PCIE3_ADDR \ 2159 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) 2160 2161 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 2162 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 2163 2164 #endif /*__IMMAP_85xx__*/ 2165