1 /* 2 * MPC85xx Internal Memory Map 3 * 4 * Copyright 2007-2011 Freescale Semiconductor, Inc. 5 * 6 * Copyright(c) 2002,2003 Motorola Inc. 7 * Xianghua Xiao (x.xiao@motorola.com) 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __IMMAP_85xx__ 29 #define __IMMAP_85xx__ 30 31 #include <asm/types.h> 32 #include <asm/fsl_dma.h> 33 #include <asm/fsl_i2c.h> 34 #include <asm/fsl_ifc.h> 35 #include <asm/fsl_lbc.h> 36 #include <asm/fsl_fman.h> 37 38 typedef struct ccsr_local { 39 u32 ccsrbarh; /* CCSR Base Addr High */ 40 u32 ccsrbarl; /* CCSR Base Addr Low */ 41 u32 ccsrar; /* CCSR Attr */ 42 #define CCSRAR_C 0x80000000 /* Commit */ 43 u8 res1[4]; 44 u32 altcbarh; /* Alternate Configuration Base Addr High */ 45 u32 altcbarl; /* Alternate Configuration Base Addr Low */ 46 u32 altcar; /* Alternate Configuration Attr */ 47 u8 res2[4]; 48 u32 bstrh; /* Boot space translation high */ 49 u32 bstrl; /* Boot space translation Low */ 50 u32 bstrar; /* Boot space translation attributes */ 51 u8 res3[0xbd4]; 52 struct { 53 u32 lawbarh; /* LAWn base addr high */ 54 u32 lawbarl; /* LAWn base addr low */ 55 u32 lawar; /* LAWn attributes */ 56 u8 res4[4]; 57 } law[32]; 58 u8 res35[0x204]; 59 } ccsr_local_t; 60 61 /* Local-Access Registers & ECM Registers */ 62 typedef struct ccsr_local_ecm { 63 u32 ccsrbar; /* CCSR Base Addr */ 64 u8 res1[4]; 65 u32 altcbar; /* Alternate Configuration Base Addr */ 66 u8 res2[4]; 67 u32 altcar; /* Alternate Configuration Attr */ 68 u8 res3[12]; 69 u32 bptr; /* Boot Page Translation */ 70 u8 res4[3044]; 71 u32 lawbar0; /* Local Access Window 0 Base Addr */ 72 u8 res5[4]; 73 u32 lawar0; /* Local Access Window 0 Attrs */ 74 u8 res6[20]; 75 u32 lawbar1; /* Local Access Window 1 Base Addr */ 76 u8 res7[4]; 77 u32 lawar1; /* Local Access Window 1 Attrs */ 78 u8 res8[20]; 79 u32 lawbar2; /* Local Access Window 2 Base Addr */ 80 u8 res9[4]; 81 u32 lawar2; /* Local Access Window 2 Attrs */ 82 u8 res10[20]; 83 u32 lawbar3; /* Local Access Window 3 Base Addr */ 84 u8 res11[4]; 85 u32 lawar3; /* Local Access Window 3 Attrs */ 86 u8 res12[20]; 87 u32 lawbar4; /* Local Access Window 4 Base Addr */ 88 u8 res13[4]; 89 u32 lawar4; /* Local Access Window 4 Attrs */ 90 u8 res14[20]; 91 u32 lawbar5; /* Local Access Window 5 Base Addr */ 92 u8 res15[4]; 93 u32 lawar5; /* Local Access Window 5 Attrs */ 94 u8 res16[20]; 95 u32 lawbar6; /* Local Access Window 6 Base Addr */ 96 u8 res17[4]; 97 u32 lawar6; /* Local Access Window 6 Attrs */ 98 u8 res18[20]; 99 u32 lawbar7; /* Local Access Window 7 Base Addr */ 100 u8 res19[4]; 101 u32 lawar7; /* Local Access Window 7 Attrs */ 102 u8 res19_8a[20]; 103 u32 lawbar8; /* Local Access Window 8 Base Addr */ 104 u8 res19_8b[4]; 105 u32 lawar8; /* Local Access Window 8 Attrs */ 106 u8 res19_9a[20]; 107 u32 lawbar9; /* Local Access Window 9 Base Addr */ 108 u8 res19_9b[4]; 109 u32 lawar9; /* Local Access Window 9 Attrs */ 110 u8 res19_10a[20]; 111 u32 lawbar10; /* Local Access Window 10 Base Addr */ 112 u8 res19_10b[4]; 113 u32 lawar10; /* Local Access Window 10 Attrs */ 114 u8 res19_11a[20]; 115 u32 lawbar11; /* Local Access Window 11 Base Addr */ 116 u8 res19_11b[4]; 117 u32 lawar11; /* Local Access Window 11 Attrs */ 118 u8 res20[652]; 119 u32 eebacr; /* ECM CCB Addr Configuration */ 120 u8 res21[12]; 121 u32 eebpcr; /* ECM CCB Port Configuration */ 122 u8 res22[3564]; 123 u32 eedr; /* ECM Error Detect */ 124 u8 res23[4]; 125 u32 eeer; /* ECM Error Enable */ 126 u32 eeatr; /* ECM Error Attrs Capture */ 127 u32 eeadr; /* ECM Error Addr Capture */ 128 u8 res24[492]; 129 } ccsr_local_ecm_t; 130 131 /* DDR memory controller registers */ 132 typedef struct ccsr_ddr { 133 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ 134 u8 res1[4]; 135 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ 136 u8 res2[4]; 137 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ 138 u8 res3[4]; 139 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ 140 u8 res4[100]; 141 u32 cs0_config; /* Chip Select Configuration */ 142 u32 cs1_config; /* Chip Select Configuration */ 143 u32 cs2_config; /* Chip Select Configuration */ 144 u32 cs3_config; /* Chip Select Configuration */ 145 u8 res4a[48]; 146 u32 cs0_config_2; /* Chip Select Configuration 2 */ 147 u32 cs1_config_2; /* Chip Select Configuration 2 */ 148 u32 cs2_config_2; /* Chip Select Configuration 2 */ 149 u32 cs3_config_2; /* Chip Select Configuration 2 */ 150 u8 res5[48]; 151 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 152 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 153 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 154 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 155 u32 sdram_cfg; /* SDRAM Control Configuration */ 156 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ 157 u32 sdram_mode; /* SDRAM Mode Configuration */ 158 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ 159 u32 sdram_md_cntl; /* SDRAM Mode Control */ 160 u32 sdram_interval; /* SDRAM Interval Configuration */ 161 u32 sdram_data_init; /* SDRAM Data initialization */ 162 u8 res6[4]; 163 u32 sdram_clk_cntl; /* SDRAM Clock Control */ 164 u8 res7[20]; 165 u32 init_addr; /* training init addr */ 166 u32 init_ext_addr; /* training init extended addr */ 167 u8 res8_1[16]; 168 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ 169 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ 170 u8 reg8_1a[8]; 171 u32 ddr_zq_cntl; /* ZQ calibration control*/ 172 u32 ddr_wrlvl_cntl; /* write leveling control*/ 173 u8 reg8_1aa[4]; 174 u32 ddr_sr_cntr; /* self refresh counter */ 175 u32 ddr_sdram_rcw_1; /* Control Words 1 */ 176 u32 ddr_sdram_rcw_2; /* Control Words 2 */ 177 u8 reg_1ab[8]; 178 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ 179 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ 180 u8 res8_1b[104]; 181 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ 182 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ 183 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ 184 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ 185 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ 186 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ 187 u8 res8_1ba[0x908]; 188 u32 ddr_dsr1; /* Debug Status 1 */ 189 u32 ddr_dsr2; /* Debug Status 2 */ 190 u32 ddr_cdr1; /* Control Driver 1 */ 191 u32 ddr_cdr2; /* Control Driver 2 */ 192 u8 res8_1c[200]; 193 u32 ip_rev1; /* IP Block Revision 1 */ 194 u32 ip_rev2; /* IP Block Revision 2 */ 195 u32 eor; /* Enhanced Optimization Register */ 196 u8 res8_2[252]; 197 u32 mtcr; /* Memory Test Control Register */ 198 u8 res8_3[28]; 199 u32 mtp1; /* Memory Test Pattern 1 */ 200 u32 mtp2; /* Memory Test Pattern 2 */ 201 u32 mtp3; /* Memory Test Pattern 3 */ 202 u32 mtp4; /* Memory Test Pattern 4 */ 203 u32 mtp5; /* Memory Test Pattern 5 */ 204 u32 mtp6; /* Memory Test Pattern 6 */ 205 u32 mtp7; /* Memory Test Pattern 7 */ 206 u32 mtp8; /* Memory Test Pattern 8 */ 207 u32 mtp9; /* Memory Test Pattern 9 */ 208 u32 mtp10; /* Memory Test Pattern 10 */ 209 u8 res8_4[184]; 210 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ 211 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ 212 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ 213 u8 res9[20]; 214 u32 capture_data_hi; /* Data Path Read Capture High */ 215 u32 capture_data_lo; /* Data Path Read Capture Low */ 216 u32 capture_ecc; /* Data Path Read Capture ECC */ 217 u8 res10[20]; 218 u32 err_detect; /* Error Detect */ 219 u32 err_disable; /* Error Disable */ 220 u32 err_int_en; 221 u32 capture_attributes; /* Error Attrs Capture */ 222 u32 capture_address; /* Error Addr Capture */ 223 u32 capture_ext_address; /* Error Extended Addr Capture */ 224 u32 err_sbe; /* Single-Bit ECC Error Management */ 225 u8 res11[164]; 226 u32 debug[32]; /* debug_1 to debug_32 */ 227 u8 res12[128]; 228 } ccsr_ddr_t; 229 230 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ 231 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ 232 233 /* I2C Registers */ 234 typedef struct ccsr_i2c { 235 struct fsl_i2c i2c[1]; 236 u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; 237 } ccsr_i2c_t; 238 239 #if defined(CONFIG_MPC8540) \ 240 || defined(CONFIG_MPC8541) \ 241 || defined(CONFIG_MPC8548) \ 242 || defined(CONFIG_MPC8555) 243 /* DUART Registers */ 244 typedef struct ccsr_duart { 245 u8 res1[1280]; 246 /* URBR1, UTHR1, UDLB1 with the same addr */ 247 u8 urbr1_uthr1_udlb1; 248 /* UIER1, UDMB1 with the same addr01 */ 249 u8 uier1_udmb1; 250 /* UIIR1, UFCR1, UAFR1 with the same addr */ 251 u8 uiir1_ufcr1_uafr1; 252 u8 ulcr1; /* UART1 Line Control */ 253 u8 umcr1; /* UART1 Modem Control */ 254 u8 ulsr1; /* UART1 Line Status */ 255 u8 umsr1; /* UART1 Modem Status */ 256 u8 uscr1; /* UART1 Scratch */ 257 u8 res2[8]; 258 u8 udsr1; /* UART1 DMA Status */ 259 u8 res3[239]; 260 /* URBR2, UTHR2, UDLB2 with the same addr */ 261 u8 urbr2_uthr2_udlb2; 262 /* UIER2, UDMB2 with the same addr */ 263 u8 uier2_udmb2; 264 /* UIIR2, UFCR2, UAFR2 with the same addr */ 265 u8 uiir2_ufcr2_uafr2; 266 u8 ulcr2; /* UART2 Line Control */ 267 u8 umcr2; /* UART2 Modem Control */ 268 u8 ulsr2; /* UART2 Line Status */ 269 u8 umsr2; /* UART2 Modem Status */ 270 u8 uscr2; /* UART2 Scratch */ 271 u8 res4[8]; 272 u8 udsr2; /* UART2 DMA Status */ 273 u8 res5[2543]; 274 } ccsr_duart_t; 275 #else /* MPC8560 uses UART on its CPM */ 276 typedef struct ccsr_duart { 277 u8 res[4096]; 278 } ccsr_duart_t; 279 #endif 280 281 /* eSPI Registers */ 282 typedef struct ccsr_espi { 283 u32 mode; /* eSPI mode */ 284 u32 event; /* eSPI event */ 285 u32 mask; /* eSPI mask */ 286 u32 com; /* eSPI command */ 287 u32 tx; /* eSPI transmit FIFO access */ 288 u32 rx; /* eSPI receive FIFO access */ 289 u8 res1[8]; /* reserved */ 290 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ 291 u8 res2[4048]; /* fill up to 0x1000 */ 292 } ccsr_espi_t; 293 294 /* PCI Registers */ 295 typedef struct ccsr_pcix { 296 u32 cfg_addr; /* PCIX Configuration Addr */ 297 u32 cfg_data; /* PCIX Configuration Data */ 298 u32 int_ack; /* PCIX IRQ Acknowledge */ 299 u8 res1[3060]; 300 u32 potar0; /* PCIX Outbound Transaction Addr 0 */ 301 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ 302 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ 303 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ 304 u32 powar0; /* PCIX Outbound Window Attrs 0 */ 305 u8 res2[12]; 306 u32 potar1; /* PCIX Outbound Transaction Addr 1 */ 307 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ 308 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ 309 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ 310 u32 powar1; /* PCIX Outbound Window Attrs 1 */ 311 u8 res3[12]; 312 u32 potar2; /* PCIX Outbound Transaction Addr 2 */ 313 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ 314 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ 315 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ 316 u32 powar2; /* PCIX Outbound Window Attrs 2 */ 317 u8 res4[12]; 318 u32 potar3; /* PCIX Outbound Transaction Addr 3 */ 319 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ 320 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ 321 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ 322 u32 powar3; /* PCIX Outbound Window Attrs 3 */ 323 u8 res5[12]; 324 u32 potar4; /* PCIX Outbound Transaction Addr 4 */ 325 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ 326 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ 327 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ 328 u32 powar4; /* PCIX Outbound Window Attrs 4 */ 329 u8 res6[268]; 330 u32 pitar3; /* PCIX Inbound Translation Addr 3 */ 331 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ 332 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ 333 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ 334 u32 piwar3; /* PCIX Inbound Window Attrs 3 */ 335 u8 res7[12]; 336 u32 pitar2; /* PCIX Inbound Translation Addr 2 */ 337 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ 338 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ 339 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ 340 u32 piwar2; /* PCIX Inbound Window Attrs 2 */ 341 u8 res8[12]; 342 u32 pitar1; /* PCIX Inbound Translation Addr 1 */ 343 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ 344 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ 345 u8 res9[4]; 346 u32 piwar1; /* PCIX Inbound Window Attrs 1 */ 347 u8 res10[12]; 348 u32 pedr; /* PCIX Error Detect */ 349 u32 pecdr; /* PCIX Error Capture Disable */ 350 u32 peer; /* PCIX Error Enable */ 351 u32 peattrcr; /* PCIX Error Attrs Capture */ 352 u32 peaddrcr; /* PCIX Error Addr Capture */ 353 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ 354 u32 pedlcr; /* PCIX Error Data Low Capture */ 355 u32 pedhcr; /* PCIX Error Error Data High Capture */ 356 u32 gas_timr; /* PCIX Gasket Timer */ 357 u8 res11[476]; 358 } ccsr_pcix_t; 359 360 #define PCIX_COMMAND 0x62 361 #define POWAR_EN 0x80000000 362 #define POWAR_IO_READ 0x00080000 363 #define POWAR_MEM_READ 0x00040000 364 #define POWAR_IO_WRITE 0x00008000 365 #define POWAR_MEM_WRITE 0x00004000 366 #define POWAR_MEM_512M 0x0000001c 367 #define POWAR_IO_1M 0x00000013 368 369 #define PIWAR_EN 0x80000000 370 #define PIWAR_PF 0x20000000 371 #define PIWAR_LOCAL 0x00f00000 372 #define PIWAR_READ_SNOOP 0x00050000 373 #define PIWAR_WRITE_SNOOP 0x00005000 374 #define PIWAR_MEM_2G 0x0000001e 375 376 typedef struct ccsr_gpio { 377 u32 gpdir; 378 u32 gpodr; 379 u32 gpdat; 380 u32 gpier; 381 u32 gpimr; 382 u32 gpicr; 383 } ccsr_gpio_t; 384 385 /* L2 Cache Registers */ 386 typedef struct ccsr_l2cache { 387 u32 l2ctl; /* L2 configuration 0 */ 388 u8 res1[12]; 389 u32 l2cewar0; /* L2 cache external write addr 0 */ 390 u8 res2[4]; 391 u32 l2cewcr0; /* L2 cache external write control 0 */ 392 u8 res3[4]; 393 u32 l2cewar1; /* L2 cache external write addr 1 */ 394 u8 res4[4]; 395 u32 l2cewcr1; /* L2 cache external write control 1 */ 396 u8 res5[4]; 397 u32 l2cewar2; /* L2 cache external write addr 2 */ 398 u8 res6[4]; 399 u32 l2cewcr2; /* L2 cache external write control 2 */ 400 u8 res7[4]; 401 u32 l2cewar3; /* L2 cache external write addr 3 */ 402 u8 res8[4]; 403 u32 l2cewcr3; /* L2 cache external write control 3 */ 404 u8 res9[180]; 405 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ 406 u8 res10[4]; 407 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ 408 u8 res11[3316]; 409 u32 l2errinjhi; /* L2 error injection mask high */ 410 u32 l2errinjlo; /* L2 error injection mask low */ 411 u32 l2errinjctl; /* L2 error injection tag/ECC control */ 412 u8 res12[20]; 413 u32 l2captdatahi; /* L2 error data high capture */ 414 u32 l2captdatalo; /* L2 error data low capture */ 415 u32 l2captecc; /* L2 error ECC capture */ 416 u8 res13[20]; 417 u32 l2errdet; /* L2 error detect */ 418 u32 l2errdis; /* L2 error disable */ 419 u32 l2errinten; /* L2 error interrupt enable */ 420 u32 l2errattr; /* L2 error attributes capture */ 421 u32 l2erraddr; /* L2 error addr capture */ 422 u8 res14[4]; 423 u32 l2errctl; /* L2 error control */ 424 u8 res15[420]; 425 } ccsr_l2cache_t; 426 427 #define MPC85xx_L2CTL_L2E 0x80000000 428 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 429 #define MPC85xx_L2ERRDIS_MBECC 0x00000008 430 #define MPC85xx_L2ERRDIS_SBECC 0x00000004 431 432 /* DMA Registers */ 433 typedef struct ccsr_dma { 434 u8 res1[256]; 435 struct fsl_dma dma[4]; 436 u32 dgsr; /* DMA General Status */ 437 u8 res2[11516]; 438 } ccsr_dma_t; 439 440 /* tsec */ 441 typedef struct ccsr_tsec { 442 u8 res1[16]; 443 u32 ievent; /* IRQ Event */ 444 u32 imask; /* IRQ Mask */ 445 u32 edis; /* Error Disabled */ 446 u8 res2[4]; 447 u32 ecntrl; /* Ethernet Control */ 448 u32 minflr; /* Minimum Frame Len */ 449 u32 ptv; /* Pause Time Value */ 450 u32 dmactrl; /* DMA Control */ 451 u32 tbipa; /* TBI PHY Addr */ 452 u8 res3[88]; 453 u32 fifo_tx_thr; /* FIFO transmit threshold */ 454 u8 res4[8]; 455 u32 fifo_tx_starve; /* FIFO transmit starve */ 456 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ 457 u8 res5[96]; 458 u32 tctrl; /* TX Control */ 459 u32 tstat; /* TX Status */ 460 u8 res6[4]; 461 u32 tbdlen; /* TX Buffer Desc Data Len */ 462 u8 res7[16]; 463 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ 464 u32 ctbptr; /* Current TX Buffer Desc Ptr */ 465 u8 res8[88]; 466 u32 tbptrh; /* TX Buffer Desc Ptr High */ 467 u32 tbptr; /* TX Buffer Desc Ptr Low */ 468 u8 res9[120]; 469 u32 tbaseh; /* TX Desc Base Addr High */ 470 u32 tbase; /* TX Desc Base Addr */ 471 u8 res10[168]; 472 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ 473 u32 ostbdp; /* OOS TX Data Buffer Ptr */ 474 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ 475 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ 476 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ 477 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ 478 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ 479 u8 res11[52]; 480 u32 rctrl; /* RX Control */ 481 u32 rstat; /* RX Status */ 482 u8 res12[4]; 483 u32 rbdlen; /* RxBD Data Len */ 484 u8 res13[16]; 485 u32 crbptrh; /* Current RX Buffer Desc Ptr High */ 486 u32 crbptr; /* Current RX Buffer Desc Ptr */ 487 u8 res14[24]; 488 u32 mrblr; /* Maximum RX Buffer Len */ 489 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ 490 u8 res15[56]; 491 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ 492 u32 rbptr; /* RX Buffer Desc Ptr */ 493 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ 494 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ 495 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ 496 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ 497 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ 498 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ 499 u8 res16[96]; 500 u32 rbaseh; /* RX Desc Base Addr High 0 */ 501 u32 rbase; /* RX Desc Base Addr */ 502 u32 rbaseh1; /* RX Desc Base Addr High 1 */ 503 u32 rbasel1; /* RX Desc Base Addr Low 1 */ 504 u32 rbaseh2; /* RX Desc Base Addr High 2 */ 505 u32 rbasel2; /* RX Desc Base Addr Low 2 */ 506 u32 rbaseh3; /* RX Desc Base Addr High 3 */ 507 u32 rbasel3; /* RX Desc Base Addr Low 3 */ 508 u8 res17[224]; 509 u32 maccfg1; /* MAC Configuration 1 */ 510 u32 maccfg2; /* MAC Configuration 2 */ 511 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 512 u32 hafdup; /* Half Duplex */ 513 u32 maxfrm; /* Maximum Frame Len */ 514 u8 res18[12]; 515 u32 miimcfg; /* MII Management Configuration */ 516 u32 miimcom; /* MII Management Cmd */ 517 u32 miimadd; /* MII Management Addr */ 518 u32 miimcon; /* MII Management Control */ 519 u32 miimstat; /* MII Management Status */ 520 u32 miimind; /* MII Management Indicator */ 521 u8 res19[4]; 522 u32 ifstat; /* Interface Status */ 523 u32 macstnaddr1; /* Station Addr Part 1 */ 524 u32 macstnaddr2; /* Station Addr Part 2 */ 525 u8 res20[312]; 526 u32 tr64; /* TX & RX 64-byte Frame Counter */ 527 u32 tr127; /* TX & RX 65-127 byte Frame Counter */ 528 u32 tr255; /* TX & RX 128-255 byte Frame Counter */ 529 u32 tr511; /* TX & RX 256-511 byte Frame Counter */ 530 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ 531 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ 532 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ 533 u32 rbyt; /* RX Byte Counter */ 534 u32 rpkt; /* RX Packet Counter */ 535 u32 rfcs; /* RX FCS Error Counter */ 536 u32 rmca; /* RX Multicast Packet Counter */ 537 u32 rbca; /* RX Broadcast Packet Counter */ 538 u32 rxcf; /* RX Control Frame Packet Counter */ 539 u32 rxpf; /* RX Pause Frame Packet Counter */ 540 u32 rxuo; /* RX Unknown OP Code Counter */ 541 u32 raln; /* RX Alignment Error Counter */ 542 u32 rflr; /* RX Frame Len Error Counter */ 543 u32 rcde; /* RX Code Error Counter */ 544 u32 rcse; /* RX Carrier Sense Error Counter */ 545 u32 rund; /* RX Undersize Packet Counter */ 546 u32 rovr; /* RX Oversize Packet Counter */ 547 u32 rfrg; /* RX Fragments Counter */ 548 u32 rjbr; /* RX Jabber Counter */ 549 u32 rdrp; /* RX Drop Counter */ 550 u32 tbyt; /* TX Byte Counter Counter */ 551 u32 tpkt; /* TX Packet Counter */ 552 u32 tmca; /* TX Multicast Packet Counter */ 553 u32 tbca; /* TX Broadcast Packet Counter */ 554 u32 txpf; /* TX Pause Control Frame Counter */ 555 u32 tdfr; /* TX Deferral Packet Counter */ 556 u32 tedf; /* TX Excessive Deferral Packet Counter */ 557 u32 tscl; /* TX Single Collision Packet Counter */ 558 u32 tmcl; /* TX Multiple Collision Packet Counter */ 559 u32 tlcl; /* TX Late Collision Packet Counter */ 560 u32 txcl; /* TX Excessive Collision Packet Counter */ 561 u32 tncl; /* TX Total Collision Counter */ 562 u8 res21[4]; 563 u32 tdrp; /* TX Drop Frame Counter */ 564 u32 tjbr; /* TX Jabber Frame Counter */ 565 u32 tfcs; /* TX FCS Error Counter */ 566 u32 txcf; /* TX Control Frame Counter */ 567 u32 tovr; /* TX Oversize Frame Counter */ 568 u32 tund; /* TX Undersize Frame Counter */ 569 u32 tfrg; /* TX Fragments Frame Counter */ 570 u32 car1; /* Carry One */ 571 u32 car2; /* Carry Two */ 572 u32 cam1; /* Carry Mask One */ 573 u32 cam2; /* Carry Mask Two */ 574 u8 res22[192]; 575 u32 iaddr0; /* Indivdual addr 0 */ 576 u32 iaddr1; /* Indivdual addr 1 */ 577 u32 iaddr2; /* Indivdual addr 2 */ 578 u32 iaddr3; /* Indivdual addr 3 */ 579 u32 iaddr4; /* Indivdual addr 4 */ 580 u32 iaddr5; /* Indivdual addr 5 */ 581 u32 iaddr6; /* Indivdual addr 6 */ 582 u32 iaddr7; /* Indivdual addr 7 */ 583 u8 res23[96]; 584 u32 gaddr0; /* Global addr 0 */ 585 u32 gaddr1; /* Global addr 1 */ 586 u32 gaddr2; /* Global addr 2 */ 587 u32 gaddr3; /* Global addr 3 */ 588 u32 gaddr4; /* Global addr 4 */ 589 u32 gaddr5; /* Global addr 5 */ 590 u32 gaddr6; /* Global addr 6 */ 591 u32 gaddr7; /* Global addr 7 */ 592 u8 res24[96]; 593 u32 pmd0; /* Pattern Match Data */ 594 u8 res25[4]; 595 u32 pmask0; /* Pattern Mask */ 596 u8 res26[4]; 597 u32 pcntrl0; /* Pattern Match Control */ 598 u8 res27[4]; 599 u32 pattrb0; /* Pattern Match Attrs */ 600 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ 601 u32 pmd1; /* Pattern Match Data */ 602 u8 res28[4]; 603 u32 pmask1; /* Pattern Mask */ 604 u8 res29[4]; 605 u32 pcntrl1; /* Pattern Match Control */ 606 u8 res30[4]; 607 u32 pattrb1; /* Pattern Match Attrs */ 608 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ 609 u32 pmd2; /* Pattern Match Data */ 610 u8 res31[4]; 611 u32 pmask2; /* Pattern Mask */ 612 u8 res32[4]; 613 u32 pcntrl2; /* Pattern Match Control */ 614 u8 res33[4]; 615 u32 pattrb2; /* Pattern Match Attrs */ 616 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ 617 u32 pmd3; /* Pattern Match Data */ 618 u8 res34[4]; 619 u32 pmask3; /* Pattern Mask */ 620 u8 res35[4]; 621 u32 pcntrl3; /* Pattern Match Control */ 622 u8 res36[4]; 623 u32 pattrb3; /* Pattern Match Attrs */ 624 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ 625 u32 pmd4; /* Pattern Match Data */ 626 u8 res37[4]; 627 u32 pmask4; /* Pattern Mask */ 628 u8 res38[4]; 629 u32 pcntrl4; /* Pattern Match Control */ 630 u8 res39[4]; 631 u32 pattrb4; /* Pattern Match Attrs */ 632 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ 633 u32 pmd5; /* Pattern Match Data */ 634 u8 res40[4]; 635 u32 pmask5; /* Pattern Mask */ 636 u8 res41[4]; 637 u32 pcntrl5; /* Pattern Match Control */ 638 u8 res42[4]; 639 u32 pattrb5; /* Pattern Match Attrs */ 640 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ 641 u32 pmd6; /* Pattern Match Data */ 642 u8 res43[4]; 643 u32 pmask6; /* Pattern Mask */ 644 u8 res44[4]; 645 u32 pcntrl6; /* Pattern Match Control */ 646 u8 res45[4]; 647 u32 pattrb6; /* Pattern Match Attrs */ 648 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ 649 u32 pmd7; /* Pattern Match Data */ 650 u8 res46[4]; 651 u32 pmask7; /* Pattern Mask */ 652 u8 res47[4]; 653 u32 pcntrl7; /* Pattern Match Control */ 654 u8 res48[4]; 655 u32 pattrb7; /* Pattern Match Attrs */ 656 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ 657 u32 pmd8; /* Pattern Match Data */ 658 u8 res49[4]; 659 u32 pmask8; /* Pattern Mask */ 660 u8 res50[4]; 661 u32 pcntrl8; /* Pattern Match Control */ 662 u8 res51[4]; 663 u32 pattrb8; /* Pattern Match Attrs */ 664 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ 665 u32 pmd9; /* Pattern Match Data */ 666 u8 res52[4]; 667 u32 pmask9; /* Pattern Mask */ 668 u8 res53[4]; 669 u32 pcntrl9; /* Pattern Match Control */ 670 u8 res54[4]; 671 u32 pattrb9; /* Pattern Match Attrs */ 672 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ 673 u32 pmd10; /* Pattern Match Data */ 674 u8 res55[4]; 675 u32 pmask10; /* Pattern Mask */ 676 u8 res56[4]; 677 u32 pcntrl10; /* Pattern Match Control */ 678 u8 res57[4]; 679 u32 pattrb10; /* Pattern Match Attrs */ 680 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ 681 u32 pmd11; /* Pattern Match Data */ 682 u8 res58[4]; 683 u32 pmask11; /* Pattern Mask */ 684 u8 res59[4]; 685 u32 pcntrl11; /* Pattern Match Control */ 686 u8 res60[4]; 687 u32 pattrb11; /* Pattern Match Attrs */ 688 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ 689 u32 pmd12; /* Pattern Match Data */ 690 u8 res61[4]; 691 u32 pmask12; /* Pattern Mask */ 692 u8 res62[4]; 693 u32 pcntrl12; /* Pattern Match Control */ 694 u8 res63[4]; 695 u32 pattrb12; /* Pattern Match Attrs */ 696 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ 697 u32 pmd13; /* Pattern Match Data */ 698 u8 res64[4]; 699 u32 pmask13; /* Pattern Mask */ 700 u8 res65[4]; 701 u32 pcntrl13; /* Pattern Match Control */ 702 u8 res66[4]; 703 u32 pattrb13; /* Pattern Match Attrs */ 704 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ 705 u32 pmd14; /* Pattern Match Data */ 706 u8 res67[4]; 707 u32 pmask14; /* Pattern Mask */ 708 u8 res68[4]; 709 u32 pcntrl14; /* Pattern Match Control */ 710 u8 res69[4]; 711 u32 pattrb14; /* Pattern Match Attrs */ 712 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ 713 u32 pmd15; /* Pattern Match Data */ 714 u8 res70[4]; 715 u32 pmask15; /* Pattern Mask */ 716 u8 res71[4]; 717 u32 pcntrl15; /* Pattern Match Control */ 718 u8 res72[4]; 719 u32 pattrb15; /* Pattern Match Attrs */ 720 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ 721 u8 res73[248]; 722 u32 attr; /* Attrs */ 723 u32 attreli; /* Attrs Extract Len & Idx */ 724 u8 res74[1024]; 725 } ccsr_tsec_t; 726 727 /* PIC Registers */ 728 typedef struct ccsr_pic { 729 u8 res1[64]; 730 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ 731 u8 res2[12]; 732 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ 733 u8 res3[12]; 734 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ 735 u8 res4[12]; 736 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ 737 u8 res5[12]; 738 u32 ctpr; /* Current Task Priority */ 739 u8 res6[12]; 740 u32 whoami; /* Who Am I */ 741 u8 res7[12]; 742 u32 iack; /* IRQ Acknowledge */ 743 u8 res8[12]; 744 u32 eoi; /* End Of IRQ */ 745 u8 res9[3916]; 746 u32 frr; /* Feature Reporting */ 747 u8 res10[28]; 748 u32 gcr; /* Global Configuration */ 749 #define MPC85xx_PICGCR_RST 0x80000000 750 #define MPC85xx_PICGCR_M 0x20000000 751 u8 res11[92]; 752 u32 vir; /* Vendor Identification */ 753 u8 res12[12]; 754 u32 pir; /* Processor Initialization */ 755 u8 res13[12]; 756 u32 ipivpr0; /* IPI Vector/Priority 0 */ 757 u8 res14[12]; 758 u32 ipivpr1; /* IPI Vector/Priority 1 */ 759 u8 res15[12]; 760 u32 ipivpr2; /* IPI Vector/Priority 2 */ 761 u8 res16[12]; 762 u32 ipivpr3; /* IPI Vector/Priority 3 */ 763 u8 res17[12]; 764 u32 svr; /* Spurious Vector */ 765 u8 res18[12]; 766 u32 tfrr; /* Timer Frequency Reporting */ 767 u8 res19[12]; 768 u32 gtccr0; /* Global Timer Current Count 0 */ 769 u8 res20[12]; 770 u32 gtbcr0; /* Global Timer Base Count 0 */ 771 u8 res21[12]; 772 u32 gtvpr0; /* Global Timer Vector/Priority 0 */ 773 u8 res22[12]; 774 u32 gtdr0; /* Global Timer Destination 0 */ 775 u8 res23[12]; 776 u32 gtccr1; /* Global Timer Current Count 1 */ 777 u8 res24[12]; 778 u32 gtbcr1; /* Global Timer Base Count 1 */ 779 u8 res25[12]; 780 u32 gtvpr1; /* Global Timer Vector/Priority 1 */ 781 u8 res26[12]; 782 u32 gtdr1; /* Global Timer Destination 1 */ 783 u8 res27[12]; 784 u32 gtccr2; /* Global Timer Current Count 2 */ 785 u8 res28[12]; 786 u32 gtbcr2; /* Global Timer Base Count 2 */ 787 u8 res29[12]; 788 u32 gtvpr2; /* Global Timer Vector/Priority 2 */ 789 u8 res30[12]; 790 u32 gtdr2; /* Global Timer Destination 2 */ 791 u8 res31[12]; 792 u32 gtccr3; /* Global Timer Current Count 3 */ 793 u8 res32[12]; 794 u32 gtbcr3; /* Global Timer Base Count 3 */ 795 u8 res33[12]; 796 u32 gtvpr3; /* Global Timer Vector/Priority 3 */ 797 u8 res34[12]; 798 u32 gtdr3; /* Global Timer Destination 3 */ 799 u8 res35[268]; 800 u32 tcr; /* Timer Control */ 801 u8 res36[12]; 802 u32 irqsr0; /* IRQ_OUT Summary 0 */ 803 u8 res37[12]; 804 u32 irqsr1; /* IRQ_OUT Summary 1 */ 805 u8 res38[12]; 806 u32 cisr0; /* Critical IRQ Summary 0 */ 807 u8 res39[12]; 808 u32 cisr1; /* Critical IRQ Summary 1 */ 809 u8 res40[188]; 810 u32 msgr0; /* Message 0 */ 811 u8 res41[12]; 812 u32 msgr1; /* Message 1 */ 813 u8 res42[12]; 814 u32 msgr2; /* Message 2 */ 815 u8 res43[12]; 816 u32 msgr3; /* Message 3 */ 817 u8 res44[204]; 818 u32 mer; /* Message Enable */ 819 u8 res45[12]; 820 u32 msr; /* Message Status */ 821 u8 res46[60140]; 822 u32 eivpr0; /* External IRQ Vector/Priority 0 */ 823 u8 res47[12]; 824 u32 eidr0; /* External IRQ Destination 0 */ 825 u8 res48[12]; 826 u32 eivpr1; /* External IRQ Vector/Priority 1 */ 827 u8 res49[12]; 828 u32 eidr1; /* External IRQ Destination 1 */ 829 u8 res50[12]; 830 u32 eivpr2; /* External IRQ Vector/Priority 2 */ 831 u8 res51[12]; 832 u32 eidr2; /* External IRQ Destination 2 */ 833 u8 res52[12]; 834 u32 eivpr3; /* External IRQ Vector/Priority 3 */ 835 u8 res53[12]; 836 u32 eidr3; /* External IRQ Destination 3 */ 837 u8 res54[12]; 838 u32 eivpr4; /* External IRQ Vector/Priority 4 */ 839 u8 res55[12]; 840 u32 eidr4; /* External IRQ Destination 4 */ 841 u8 res56[12]; 842 u32 eivpr5; /* External IRQ Vector/Priority 5 */ 843 u8 res57[12]; 844 u32 eidr5; /* External IRQ Destination 5 */ 845 u8 res58[12]; 846 u32 eivpr6; /* External IRQ Vector/Priority 6 */ 847 u8 res59[12]; 848 u32 eidr6; /* External IRQ Destination 6 */ 849 u8 res60[12]; 850 u32 eivpr7; /* External IRQ Vector/Priority 7 */ 851 u8 res61[12]; 852 u32 eidr7; /* External IRQ Destination 7 */ 853 u8 res62[12]; 854 u32 eivpr8; /* External IRQ Vector/Priority 8 */ 855 u8 res63[12]; 856 u32 eidr8; /* External IRQ Destination 8 */ 857 u8 res64[12]; 858 u32 eivpr9; /* External IRQ Vector/Priority 9 */ 859 u8 res65[12]; 860 u32 eidr9; /* External IRQ Destination 9 */ 861 u8 res66[12]; 862 u32 eivpr10; /* External IRQ Vector/Priority 10 */ 863 u8 res67[12]; 864 u32 eidr10; /* External IRQ Destination 10 */ 865 u8 res68[12]; 866 u32 eivpr11; /* External IRQ Vector/Priority 11 */ 867 u8 res69[12]; 868 u32 eidr11; /* External IRQ Destination 11 */ 869 u8 res70[140]; 870 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ 871 u8 res71[12]; 872 u32 iidr0; /* Internal IRQ Destination 0 */ 873 u8 res72[12]; 874 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ 875 u8 res73[12]; 876 u32 iidr1; /* Internal IRQ Destination 1 */ 877 u8 res74[12]; 878 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ 879 u8 res75[12]; 880 u32 iidr2; /* Internal IRQ Destination 2 */ 881 u8 res76[12]; 882 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ 883 u8 res77[12]; 884 u32 iidr3; /* Internal IRQ Destination 3 */ 885 u8 res78[12]; 886 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ 887 u8 res79[12]; 888 u32 iidr4; /* Internal IRQ Destination 4 */ 889 u8 res80[12]; 890 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ 891 u8 res81[12]; 892 u32 iidr5; /* Internal IRQ Destination 5 */ 893 u8 res82[12]; 894 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ 895 u8 res83[12]; 896 u32 iidr6; /* Internal IRQ Destination 6 */ 897 u8 res84[12]; 898 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ 899 u8 res85[12]; 900 u32 iidr7; /* Internal IRQ Destination 7 */ 901 u8 res86[12]; 902 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ 903 u8 res87[12]; 904 u32 iidr8; /* Internal IRQ Destination 8 */ 905 u8 res88[12]; 906 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ 907 u8 res89[12]; 908 u32 iidr9; /* Internal IRQ Destination 9 */ 909 u8 res90[12]; 910 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ 911 u8 res91[12]; 912 u32 iidr10; /* Internal IRQ Destination 10 */ 913 u8 res92[12]; 914 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ 915 u8 res93[12]; 916 u32 iidr11; /* Internal IRQ Destination 11 */ 917 u8 res94[12]; 918 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ 919 u8 res95[12]; 920 u32 iidr12; /* Internal IRQ Destination 12 */ 921 u8 res96[12]; 922 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ 923 u8 res97[12]; 924 u32 iidr13; /* Internal IRQ Destination 13 */ 925 u8 res98[12]; 926 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ 927 u8 res99[12]; 928 u32 iidr14; /* Internal IRQ Destination 14 */ 929 u8 res100[12]; 930 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ 931 u8 res101[12]; 932 u32 iidr15; /* Internal IRQ Destination 15 */ 933 u8 res102[12]; 934 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ 935 u8 res103[12]; 936 u32 iidr16; /* Internal IRQ Destination 16 */ 937 u8 res104[12]; 938 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ 939 u8 res105[12]; 940 u32 iidr17; /* Internal IRQ Destination 17 */ 941 u8 res106[12]; 942 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ 943 u8 res107[12]; 944 u32 iidr18; /* Internal IRQ Destination 18 */ 945 u8 res108[12]; 946 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ 947 u8 res109[12]; 948 u32 iidr19; /* Internal IRQ Destination 19 */ 949 u8 res110[12]; 950 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ 951 u8 res111[12]; 952 u32 iidr20; /* Internal IRQ Destination 20 */ 953 u8 res112[12]; 954 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ 955 u8 res113[12]; 956 u32 iidr21; /* Internal IRQ Destination 21 */ 957 u8 res114[12]; 958 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ 959 u8 res115[12]; 960 u32 iidr22; /* Internal IRQ Destination 22 */ 961 u8 res116[12]; 962 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ 963 u8 res117[12]; 964 u32 iidr23; /* Internal IRQ Destination 23 */ 965 u8 res118[12]; 966 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ 967 u8 res119[12]; 968 u32 iidr24; /* Internal IRQ Destination 24 */ 969 u8 res120[12]; 970 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ 971 u8 res121[12]; 972 u32 iidr25; /* Internal IRQ Destination 25 */ 973 u8 res122[12]; 974 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ 975 u8 res123[12]; 976 u32 iidr26; /* Internal IRQ Destination 26 */ 977 u8 res124[12]; 978 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ 979 u8 res125[12]; 980 u32 iidr27; /* Internal IRQ Destination 27 */ 981 u8 res126[12]; 982 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ 983 u8 res127[12]; 984 u32 iidr28; /* Internal IRQ Destination 28 */ 985 u8 res128[12]; 986 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ 987 u8 res129[12]; 988 u32 iidr29; /* Internal IRQ Destination 29 */ 989 u8 res130[12]; 990 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ 991 u8 res131[12]; 992 u32 iidr30; /* Internal IRQ Destination 30 */ 993 u8 res132[12]; 994 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ 995 u8 res133[12]; 996 u32 iidr31; /* Internal IRQ Destination 31 */ 997 u8 res134[4108]; 998 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ 999 u8 res135[12]; 1000 u32 midr0; /* Messaging IRQ Destination 0 */ 1001 u8 res136[12]; 1002 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ 1003 u8 res137[12]; 1004 u32 midr1; /* Messaging IRQ Destination 1 */ 1005 u8 res138[12]; 1006 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ 1007 u8 res139[12]; 1008 u32 midr2; /* Messaging IRQ Destination 2 */ 1009 u8 res140[12]; 1010 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ 1011 u8 res141[12]; 1012 u32 midr3; /* Messaging IRQ Destination 3 */ 1013 u8 res142[59852]; 1014 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ 1015 u8 res143[12]; 1016 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ 1017 u8 res144[12]; 1018 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ 1019 u8 res145[12]; 1020 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ 1021 u8 res146[12]; 1022 u32 ctpr0; /* Current Task Priority for Processor 0 */ 1023 u8 res147[12]; 1024 u32 whoami0; /* Who Am I for Processor 0 */ 1025 u8 res148[12]; 1026 u32 iack0; /* IRQ Acknowledge for Processor 0 */ 1027 u8 res149[12]; 1028 u32 eoi0; /* End Of IRQ for Processor 0 */ 1029 u8 res150[130892]; 1030 } ccsr_pic_t; 1031 1032 /* CPM Block */ 1033 #ifndef CONFIG_CPM2 1034 typedef struct ccsr_cpm { 1035 u8 res[262144]; 1036 } ccsr_cpm_t; 1037 #else 1038 /* 1039 * DPARM 1040 * General SIU 1041 */ 1042 typedef struct ccsr_cpm_siu { 1043 u8 res1[80]; 1044 u32 smaer; 1045 u32 smser; 1046 u32 smevr; 1047 u8 res2[4]; 1048 u32 lmaer; 1049 u32 lmser; 1050 u32 lmevr; 1051 u8 res3[2964]; 1052 } ccsr_cpm_siu_t; 1053 1054 /* IRQ Controller */ 1055 typedef struct ccsr_cpm_intctl { 1056 u16 sicr; 1057 u8 res1[2]; 1058 u32 sivec; 1059 u32 sipnrh; 1060 u32 sipnrl; 1061 u32 siprr; 1062 u32 scprrh; 1063 u32 scprrl; 1064 u32 simrh; 1065 u32 simrl; 1066 u32 siexr; 1067 u8 res2[88]; 1068 u32 sccr; 1069 u8 res3[124]; 1070 } ccsr_cpm_intctl_t; 1071 1072 /* input/output port */ 1073 typedef struct ccsr_cpm_iop { 1074 u32 pdira; 1075 u32 ppara; 1076 u32 psora; 1077 u32 podra; 1078 u32 pdata; 1079 u8 res1[12]; 1080 u32 pdirb; 1081 u32 pparb; 1082 u32 psorb; 1083 u32 podrb; 1084 u32 pdatb; 1085 u8 res2[12]; 1086 u32 pdirc; 1087 u32 pparc; 1088 u32 psorc; 1089 u32 podrc; 1090 u32 pdatc; 1091 u8 res3[12]; 1092 u32 pdird; 1093 u32 ppard; 1094 u32 psord; 1095 u32 podrd; 1096 u32 pdatd; 1097 u8 res4[12]; 1098 } ccsr_cpm_iop_t; 1099 1100 /* CPM timers */ 1101 typedef struct ccsr_cpm_timer { 1102 u8 tgcr1; 1103 u8 res1[3]; 1104 u8 tgcr2; 1105 u8 res2[11]; 1106 u16 tmr1; 1107 u16 tmr2; 1108 u16 trr1; 1109 u16 trr2; 1110 u16 tcr1; 1111 u16 tcr2; 1112 u16 tcn1; 1113 u16 tcn2; 1114 u16 tmr3; 1115 u16 tmr4; 1116 u16 trr3; 1117 u16 trr4; 1118 u16 tcr3; 1119 u16 tcr4; 1120 u16 tcn3; 1121 u16 tcn4; 1122 u16 ter1; 1123 u16 ter2; 1124 u16 ter3; 1125 u16 ter4; 1126 u8 res3[608]; 1127 } ccsr_cpm_timer_t; 1128 1129 /* SDMA */ 1130 typedef struct ccsr_cpm_sdma { 1131 u8 sdsr; 1132 u8 res1[3]; 1133 u8 sdmr; 1134 u8 res2[739]; 1135 } ccsr_cpm_sdma_t; 1136 1137 /* FCC1 */ 1138 typedef struct ccsr_cpm_fcc1 { 1139 u32 gfmr; 1140 u32 fpsmr; 1141 u16 ftodr; 1142 u8 res1[2]; 1143 u16 fdsr; 1144 u8 res2[2]; 1145 u16 fcce; 1146 u8 res3[2]; 1147 u16 fccm; 1148 u8 res4[2]; 1149 u8 fccs; 1150 u8 res5[3]; 1151 u8 ftirr_phy[4]; 1152 } ccsr_cpm_fcc1_t; 1153 1154 /* FCC2 */ 1155 typedef struct ccsr_cpm_fcc2 { 1156 u32 gfmr; 1157 u32 fpsmr; 1158 u16 ftodr; 1159 u8 res1[2]; 1160 u16 fdsr; 1161 u8 res2[2]; 1162 u16 fcce; 1163 u8 res3[2]; 1164 u16 fccm; 1165 u8 res4[2]; 1166 u8 fccs; 1167 u8 res5[3]; 1168 u8 ftirr_phy[4]; 1169 } ccsr_cpm_fcc2_t; 1170 1171 /* FCC3 */ 1172 typedef struct ccsr_cpm_fcc3 { 1173 u32 gfmr; 1174 u32 fpsmr; 1175 u16 ftodr; 1176 u8 res1[2]; 1177 u16 fdsr; 1178 u8 res2[2]; 1179 u16 fcce; 1180 u8 res3[2]; 1181 u16 fccm; 1182 u8 res4[2]; 1183 u8 fccs; 1184 u8 res5[3]; 1185 u8 res[36]; 1186 } ccsr_cpm_fcc3_t; 1187 1188 /* FCC1 extended */ 1189 typedef struct ccsr_cpm_fcc1_ext { 1190 u32 firper; 1191 u32 firer; 1192 u32 firsr_h; 1193 u32 firsr_l; 1194 u8 gfemr; 1195 u8 res[15]; 1196 1197 } ccsr_cpm_fcc1_ext_t; 1198 1199 /* FCC2 extended */ 1200 typedef struct ccsr_cpm_fcc2_ext { 1201 u32 firper; 1202 u32 firer; 1203 u32 firsr_h; 1204 u32 firsr_l; 1205 u8 gfemr; 1206 u8 res[31]; 1207 } ccsr_cpm_fcc2_ext_t; 1208 1209 /* FCC3 extended */ 1210 typedef struct ccsr_cpm_fcc3_ext { 1211 u8 gfemr; 1212 u8 res[47]; 1213 } ccsr_cpm_fcc3_ext_t; 1214 1215 /* TC layers */ 1216 typedef struct ccsr_cpm_tmp1 { 1217 u8 res[496]; 1218 } ccsr_cpm_tmp1_t; 1219 1220 /* BRGs:5,6,7,8 */ 1221 typedef struct ccsr_cpm_brg2 { 1222 u32 brgc5; 1223 u32 brgc6; 1224 u32 brgc7; 1225 u32 brgc8; 1226 u8 res[608]; 1227 } ccsr_cpm_brg2_t; 1228 1229 /* I2C */ 1230 typedef struct ccsr_cpm_i2c { 1231 u8 i2mod; 1232 u8 res1[3]; 1233 u8 i2add; 1234 u8 res2[3]; 1235 u8 i2brg; 1236 u8 res3[3]; 1237 u8 i2com; 1238 u8 res4[3]; 1239 u8 i2cer; 1240 u8 res5[3]; 1241 u8 i2cmr; 1242 u8 res6[331]; 1243 } ccsr_cpm_i2c_t; 1244 1245 /* CPM core */ 1246 typedef struct ccsr_cpm_cp { 1247 u32 cpcr; 1248 u32 rccr; 1249 u8 res1[14]; 1250 u16 rter; 1251 u8 res2[2]; 1252 u16 rtmr; 1253 u16 rtscr; 1254 u8 res3[2]; 1255 u32 rtsr; 1256 u8 res4[12]; 1257 } ccsr_cpm_cp_t; 1258 1259 /* BRGs:1,2,3,4 */ 1260 typedef struct ccsr_cpm_brg1 { 1261 u32 brgc1; 1262 u32 brgc2; 1263 u32 brgc3; 1264 u32 brgc4; 1265 } ccsr_cpm_brg1_t; 1266 1267 /* SCC1-SCC4 */ 1268 typedef struct ccsr_cpm_scc { 1269 u32 gsmrl; 1270 u32 gsmrh; 1271 u16 psmr; 1272 u8 res1[2]; 1273 u16 todr; 1274 u16 dsr; 1275 u16 scce; 1276 u8 res2[2]; 1277 u16 sccm; 1278 u8 res3; 1279 u8 sccs; 1280 u8 res4[8]; 1281 } ccsr_cpm_scc_t; 1282 1283 typedef struct ccsr_cpm_tmp2 { 1284 u8 res[32]; 1285 } ccsr_cpm_tmp2_t; 1286 1287 /* SPI */ 1288 typedef struct ccsr_cpm_spi { 1289 u16 spmode; 1290 u8 res1[4]; 1291 u8 spie; 1292 u8 res2[3]; 1293 u8 spim; 1294 u8 res3[2]; 1295 u8 spcom; 1296 u8 res4[82]; 1297 } ccsr_cpm_spi_t; 1298 1299 /* CPM MUX */ 1300 typedef struct ccsr_cpm_mux { 1301 u8 cmxsi1cr; 1302 u8 res1; 1303 u8 cmxsi2cr; 1304 u8 res2; 1305 u32 cmxfcr; 1306 u32 cmxscr; 1307 u8 res3[2]; 1308 u16 cmxuar; 1309 u8 res4[16]; 1310 } ccsr_cpm_mux_t; 1311 1312 /* SI,MCC,etc */ 1313 typedef struct ccsr_cpm_tmp3 { 1314 u8 res[58592]; 1315 } ccsr_cpm_tmp3_t; 1316 1317 typedef struct ccsr_cpm_iram { 1318 u32 iram[8192]; 1319 u8 res[98304]; 1320 } ccsr_cpm_iram_t; 1321 1322 typedef struct ccsr_cpm { 1323 /* Some references are into the unique & known dpram spaces, 1324 * others are from the generic base. 1325 */ 1326 #define im_dprambase im_dpram1 1327 u8 im_dpram1[16*1024]; 1328 u8 res1[16*1024]; 1329 u8 im_dpram2[16*1024]; 1330 u8 res2[16*1024]; 1331 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ 1332 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ 1333 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ 1334 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ 1335 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ 1336 ccsr_cpm_fcc1_t im_cpm_fcc1; 1337 ccsr_cpm_fcc2_t im_cpm_fcc2; 1338 ccsr_cpm_fcc3_t im_cpm_fcc3; 1339 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; 1340 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; 1341 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; 1342 ccsr_cpm_tmp1_t im_cpm_tmp1; 1343 ccsr_cpm_brg2_t im_cpm_brg2; 1344 ccsr_cpm_i2c_t im_cpm_i2c; 1345 ccsr_cpm_cp_t im_cpm_cp; 1346 ccsr_cpm_brg1_t im_cpm_brg1; 1347 ccsr_cpm_scc_t im_cpm_scc[4]; 1348 ccsr_cpm_tmp2_t im_cpm_tmp2; 1349 ccsr_cpm_spi_t im_cpm_spi; 1350 ccsr_cpm_mux_t im_cpm_mux; 1351 ccsr_cpm_tmp3_t im_cpm_tmp3; 1352 ccsr_cpm_iram_t im_cpm_iram; 1353 } ccsr_cpm_t; 1354 #endif 1355 1356 #ifdef CONFIG_SYS_SRIO 1357 /* Architectural regsiters */ 1358 struct rio_arch { 1359 u32 didcar; /* Device Identity CAR */ 1360 u32 dicar; /* Device Information CAR */ 1361 u32 aidcar; /* Assembly Identity CAR */ 1362 u32 aicar; /* Assembly Information CAR */ 1363 u32 pefcar; /* Processing Element Features CAR */ 1364 u8 res0[4]; 1365 u32 socar; /* Source Operations CAR */ 1366 u32 docar; /* Destination Operations CAR */ 1367 u8 res1[32]; 1368 u32 mcsr; /* Mailbox CSR */ 1369 u32 pwdcsr; /* Port-Write and Doorbell CSR */ 1370 u8 res2[4]; 1371 u32 pellccsr; /* Processing Element Logic Layer CCSR */ 1372 u8 res3[12]; 1373 u32 lcsbacsr; /* Local Configuration Space BACSR */ 1374 u32 bdidcsr; /* Base Device ID CSR */ 1375 u8 res4[4]; 1376 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ 1377 u32 ctcsr; /* Component Tag CSR */ 1378 }; 1379 1380 /* Extended Features Space: 1x/4x LP-Serial Port registers */ 1381 struct rio_lp_serial_port { 1382 u32 plmreqcsr; /* Port Link Maintenance Request CSR */ 1383 u32 plmrespcsr; /* Port Link Maintenance Response CS */ 1384 u32 plascsr; /* Port Local Ackid Status CSR */ 1385 u8 res0[12]; 1386 u32 pescsr; /* Port Error and Status CSR */ 1387 u32 pccsr; /* Port Control CSR */ 1388 }; 1389 1390 /* Extended Features Space: 1x/4x LP-Serial registers */ 1391 struct rio_lp_serial { 1392 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ 1393 u8 res0[28]; 1394 u32 pltoccsr; /* Port Link Time-out CCSR */ 1395 u32 prtoccsr; /* Port Response Time-out CCSR */ 1396 u8 res1[20]; 1397 u32 pgccsr; /* Port General CSR */ 1398 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1399 }; 1400 1401 /* Logical error reporting registers */ 1402 struct rio_logical_err { 1403 u32 erbh; /* Error Reporting Block Header Register */ 1404 u8 res0[4]; 1405 u32 ltledcsr; /* Logical/Transport layer error DCSR */ 1406 u32 ltleecsr; /* Logical/Transport layer error ECSR */ 1407 u8 res1[4]; 1408 u32 ltlaccsr; /* Logical/Transport layer ACCSR */ 1409 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ 1410 u32 ltlcccsr; /* Logical/Transport layer control CCSR */ 1411 }; 1412 1413 /* Physical error reporting port registers */ 1414 struct rio_phys_err_port { 1415 u32 edcsr; /* Port error detect CSR */ 1416 u32 erecsr; /* Port error rate enable CSR */ 1417 u32 ecacsr; /* Port error capture attributes CSR */ 1418 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ 1419 u32 peccsr[3]; /* Port error capture CSR */ 1420 u8 res0[12]; 1421 u32 ercsr; /* Port error rate CSR */ 1422 u32 ertcsr; /* Port error rate threshold CSR */ 1423 u8 res1[16]; 1424 }; 1425 1426 /* Physical error reporting registers */ 1427 struct rio_phys_err { 1428 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1429 }; 1430 1431 /* Implementation Space: General Port-Common */ 1432 struct rio_impl_common { 1433 u8 res0[4]; 1434 u32 llcr; /* Logical Layer Configuration Register */ 1435 u8 res1[8]; 1436 u32 epwisr; /* Error / Port-Write Interrupt SR */ 1437 u8 res2[12]; 1438 u32 lretcr; /* Logical Retry Error Threshold CR */ 1439 u8 res3[92]; 1440 u32 pretcr; /* Physical Retry Erorr Threshold CR */ 1441 u8 res4[124]; 1442 }; 1443 1444 /* Implementation Space: Port Specific */ 1445 struct rio_impl_port_spec { 1446 u32 adidcsr; /* Port Alt. Device ID CSR */ 1447 u8 res0[28]; 1448 u32 ptaacr; /* Port Pass-Through/Accept-All CR */ 1449 u32 lopttlcr; 1450 u8 res1[8]; 1451 u32 iecsr; /* Port Implementation Error CSR */ 1452 u8 res2[12]; 1453 u32 pcr; /* Port Phsyical Configuration Register */ 1454 u8 res3[20]; 1455 u32 slcsr; /* Port Serial Link CSR */ 1456 u8 res4[4]; 1457 u32 sleicr; /* Port Serial Link Error Injection */ 1458 u32 a0txcr; /* Port Arbitration 0 Tx CR */ 1459 u32 a1txcr; /* Port Arbitration 1 Tx CR */ 1460 u32 a2txcr; /* Port Arbitration 2 Tx CR */ 1461 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ 1462 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ 1463 }; 1464 1465 /* Implementation Space: register */ 1466 struct rio_implement { 1467 struct rio_impl_common com; 1468 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1469 }; 1470 1471 /* Revision Control Register */ 1472 struct rio_rev_ctrl { 1473 u32 ipbrr[2]; /* IP Block Revision Register */ 1474 }; 1475 1476 struct rio_atmu_row { 1477 u32 rowtar; /* RapidIO Outbound Window TAR */ 1478 u32 rowtear; /* RapidIO Outbound Window TEAR */ 1479 u32 rowbar; 1480 u8 res0[4]; 1481 u32 rowar; /* RapidIO Outbound Attributes Register */ 1482 u32 rowsr[3]; /* Port RapidIO outbound window segment register */ 1483 }; 1484 1485 struct rio_atmu_riw { 1486 u32 riwtar; /* RapidIO Inbound Window Translation AR */ 1487 u8 res0[4]; 1488 u32 riwbar; /* RapidIO Inbound Window Base AR */ 1489 u8 res1[4]; 1490 u32 riwar; /* RapidIO Inbound Attributes Register */ 1491 u8 res2[12]; 1492 }; 1493 1494 /* ATMU window registers */ 1495 struct rio_atmu_win { 1496 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; 1497 u8 res0[64]; 1498 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; 1499 }; 1500 1501 struct rio_atmu { 1502 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1503 }; 1504 1505 #ifdef CONFIG_SYS_FSL_RMU 1506 struct rio_msg { 1507 u32 omr; /* Outbound Mode Register */ 1508 u32 osr; /* Outbound Status Register */ 1509 u32 eodqdpar; /* Extended Outbound DQ DPAR */ 1510 u32 odqdpar; /* Outbound Descriptor Queue DPAR */ 1511 u32 eosar; /* Extended Outbound Unit Source AR */ 1512 u32 osar; /* Outbound Unit Source AR */ 1513 u32 odpr; /* Outbound Destination Port Register */ 1514 u32 odatr; /* Outbound Destination Attributes Register */ 1515 u32 odcr; /* Outbound Doubleword Count Register */ 1516 u32 eodqepar; /* Extended Outbound DQ EPAR */ 1517 u32 odqepar; /* Outbound Descriptor Queue EPAR */ 1518 u32 oretr; /* Outbound Retry Error Threshold Register */ 1519 u32 omgr; /* Outbound Multicast Group Register */ 1520 u32 omlr; /* Outbound Multicast List Register */ 1521 u8 res0[40]; 1522 u32 imr; /* Outbound Mode Register */ 1523 u32 isr; /* Inbound Status Register */ 1524 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ 1525 u32 idqdpar; /* Inbound Descriptor Queue DPAR */ 1526 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ 1527 u32 ifqepar; /* Inbound Frame Queue EPAR */ 1528 u32 imirir; /* Inbound Maximum Interrutp RIR */ 1529 u8 res1[4]; 1530 u32 eihqepar; /* Extended inbound message header queue EPAR */ 1531 u32 ihqepar; /* Inbound message header queue EPAR */ 1532 u8 res2[120]; 1533 }; 1534 1535 struct rio_dbell { 1536 u32 odmr; /* Outbound Doorbell Mode Register */ 1537 u32 odsr; /* Outbound Doorbell Status Register */ 1538 u8 res0[16]; 1539 u32 oddpr; /* Outbound Doorbell Destination Port */ 1540 u32 oddatr; /* Outbound Doorbell Destination AR */ 1541 u8 res1[12]; 1542 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ 1543 u8 res2[48]; 1544 u32 idmr; /* Inbound Doorbell Mode Register */ 1545 u32 idsr; /* Inbound Doorbell Status Register */ 1546 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ 1547 u32 iqdpar; /* Inbound Doorbell Queue DPAR */ 1548 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ 1549 u32 idqepar; /* Inbound Doorbell Queue EPAR */ 1550 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ 1551 }; 1552 1553 struct rio_pw { 1554 u32 pwmr; /* Port-Write Mode Register */ 1555 u32 pwsr; /* Port-Write Status Register */ 1556 u32 epwqbar; /* Extended Port-Write Queue BAR */ 1557 u32 pwqbar; /* Port-Write Queue Base Address Register */ 1558 }; 1559 #endif 1560 1561 /* RapidIO Registers */ 1562 struct ccsr_rio { 1563 struct rio_arch arch; 1564 u8 res0[144]; 1565 struct rio_lp_serial lp_serial; 1566 u8 res1[1152]; 1567 struct rio_logical_err logical_err; 1568 u8 res2[32]; 1569 struct rio_phys_err phys_err; 1570 u8 res3[63808]; 1571 struct rio_implement impl; 1572 u8 res4[2552]; 1573 struct rio_rev_ctrl rev; 1574 struct rio_atmu atmu; 1575 #ifdef CONFIG_SYS_FSL_RMU 1576 u8 res5[8192]; 1577 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; 1578 u8 res6[512]; 1579 struct rio_dbell dbell; 1580 u8 res7[100]; 1581 struct rio_pw pw; 1582 #endif 1583 }; 1584 #endif 1585 1586 /* Quick Engine Block Pin Muxing Registers */ 1587 typedef struct par_io { 1588 u32 cpodr; 1589 u32 cpdat; 1590 u32 cpdir1; 1591 u32 cpdir2; 1592 u32 cppar1; 1593 u32 cppar2; 1594 u8 res[8]; 1595 } par_io_t; 1596 1597 #ifdef CONFIG_SYS_FSL_CPC 1598 /* 1599 * Define a single offset that is the start of all the CPC register 1600 * blocks - if there is more than one CPC, we expect these to be 1601 * contiguous 4k regions 1602 */ 1603 1604 typedef struct cpc_corenet { 1605 u32 cpccsr0; /* Config/status reg */ 1606 u32 res1; 1607 u32 cpccfg0; /* Configuration register */ 1608 u32 res2; 1609 u32 cpcewcr0; /* External Write reg 0 */ 1610 u32 cpcewabr0; /* External write base reg 0 */ 1611 u32 res3[2]; 1612 u32 cpcewcr1; /* External Write reg 1 */ 1613 u32 cpcewabr1; /* External write base reg 1 */ 1614 u32 res4[54]; 1615 u32 cpcsrcr1; /* SRAM control reg 1 */ 1616 u32 cpcsrcr0; /* SRAM control reg 0 */ 1617 u32 res5[62]; 1618 struct { 1619 u32 id; /* partition ID */ 1620 u32 res; 1621 u32 alloc; /* partition allocation */ 1622 u32 way; /* partition way */ 1623 } partition_regs[16]; 1624 u32 res6[704]; 1625 u32 cpcerrinjhi; /* Error injection high */ 1626 u32 cpcerrinjlo; /* Error injection lo */ 1627 u32 cpcerrinjctl; /* Error injection control */ 1628 u32 res7[5]; 1629 u32 cpccaptdatahi; /* capture data high */ 1630 u32 cpccaptdatalo; /* capture data low */ 1631 u32 cpcaptecc; /* capture ECC */ 1632 u32 res8[5]; 1633 u32 cpcerrdet; /* error detect */ 1634 u32 cpcerrdis; /* error disable */ 1635 u32 cpcerrinten; /* errir interrupt enable */ 1636 u32 cpcerrattr; /* error attribute */ 1637 u32 cpcerreaddr; /* error extended address */ 1638 u32 cpcerraddr; /* error address */ 1639 u32 cpcerrctl; /* error control */ 1640 u32 res9[41]; /* pad out to 4k */ 1641 u32 cpchdbcr0; /* hardware debug control register 0 */ 1642 u32 res10[63]; /* pad out to 4k */ 1643 } cpc_corenet_t; 1644 1645 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ 1646 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */ 1647 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ 1648 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */ 1649 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ 1650 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ 1651 #define CPC_CFG0_SZ_MASK 0x00003fff 1652 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) 1653 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) 1654 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) 1655 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff 1656 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ 1657 & CPC_SRCR1_SRBARU_MASK) 1658 #define CPC_SRCR0_SRBARL_MASK 0xffff8000 1659 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) 1660 #define CPC_SRCR0_INTLVEN 0x00000100 1661 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 1662 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 1663 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 1664 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 1665 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 1666 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a 1667 #define CPC_SRCR0_SRAMEN 0x00000001 1668 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ 1669 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 1670 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 1671 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 1672 #endif /* CONFIG_SYS_FSL_CPC */ 1673 1674 /* Global Utilities Block */ 1675 #ifdef CONFIG_FSL_CORENET 1676 typedef struct ccsr_gur { 1677 u32 porsr1; /* POR status */ 1678 u8 res1[28]; 1679 u32 gpporcr1; /* General-purpose POR configuration */ 1680 u8 res2[12]; 1681 u32 gpiocr; /* GPIO control */ 1682 u8 res3[12]; 1683 u32 gpoutdr; /* General-purpose output data */ 1684 u8 res4[12]; 1685 u32 gpindr; /* General-purpose input data */ 1686 u8 res5[12]; 1687 u32 alt_pmuxcr; /* Alt function signal multiplex control */ 1688 u8 res6[12]; 1689 u32 devdisr; /* Device disable control */ 1690 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 1691 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 1692 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 1693 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000 1694 #define FSL_CORENET_DEVDISR_RMU 0x08000000 1695 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000 1696 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000 1697 #define FSL_CORENET_DEVDISR_DMA1 0x00400000 1698 #define FSL_CORENET_DEVDISR_DMA2 0x00200000 1699 #define FSL_CORENET_DEVDISR_DDR1 0x00100000 1700 #define FSL_CORENET_DEVDISR_DDR2 0x00080000 1701 #define FSL_CORENET_DEVDISR_DBG 0x00010000 1702 #define FSL_CORENET_DEVDISR_NAL 0x00008000 1703 #define FSL_CORENET_DEVDISR_SATA1 0x00004000 1704 #define FSL_CORENET_DEVDISR_SATA2 0x00002000 1705 #define FSL_CORENET_DEVDISR_ELBC 0x00001000 1706 #define FSL_CORENET_DEVDISR_USB1 0x00000800 1707 #define FSL_CORENET_DEVDISR_USB2 0x00000400 1708 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100 1709 #define FSL_CORENET_DEVDISR_GPIO 0x00000080 1710 #define FSL_CORENET_DEVDISR_ESPI 0x00000040 1711 #define FSL_CORENET_DEVDISR_I2C1 0x00000020 1712 #define FSL_CORENET_DEVDISR_I2C2 0x00000010 1713 #define FSL_CORENET_DEVDISR_DUART1 0x00000002 1714 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 1715 u32 devdisr2; /* Device disable control 2 */ 1716 #define FSL_CORENET_DEVDISR2_PME 0x80000000 1717 #define FSL_CORENET_DEVDISR2_SEC 0x40000000 1718 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000 1719 #define FSL_CORENET_DEVDISR2_FM1 0x02000000 1720 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000 1721 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000 1722 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 1723 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 1724 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 1725 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000 1726 #define FSL_CORENET_DEVDISR2_FM2 0x00020000 1727 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 1728 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 1729 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 1730 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 1731 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 1732 #define FSL_CORENET_NUM_DEVDISR 2 1733 u8 res7[8]; 1734 u32 powmgtcsr; /* Power management status & control */ 1735 u8 res8[12]; 1736 u32 coredisru; /* uppper portion for support of 64 cores */ 1737 u32 coredisrl; /* lower portion for support of 64 cores */ 1738 u8 res9[8]; 1739 u32 pvr; /* Processor version */ 1740 u32 svr; /* System version */ 1741 u8 res10[8]; 1742 u32 rstcr; /* Reset control */ 1743 u32 rstrqpblsr; /* Reset request preboot loader status */ 1744 u8 res11[8]; 1745 u32 rstrqmr1; /* Reset request mask */ 1746 u8 res12[4]; 1747 u32 rstrqsr1; /* Reset request status */ 1748 u8 res13[4]; 1749 u8 res14[4]; 1750 u32 rstrqwdtmrl; /* Reset request WDT mask */ 1751 u8 res15[4]; 1752 u32 rstrqwdtsrl; /* Reset request WDT status */ 1753 u8 res16[4]; 1754 u32 brrl; /* Boot release */ 1755 u8 res17[24]; 1756 u32 rcwsr[16]; /* Reset control word status */ 1757 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 1758 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 1759 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 1760 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 1761 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ 1762 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ 1763 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 1764 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 1765 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 1766 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ 1767 #if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060) 1768 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 1769 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 1770 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ 1771 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 1772 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 1773 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 1774 #endif 1775 #if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \ 1776 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) 1777 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 1778 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 1779 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 1780 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 1781 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000 1782 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 1783 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 1784 #endif 1785 u8 res18[192]; 1786 u32 scratchrw[4]; /* Scratch Read/Write */ 1787 u8 res19[240]; 1788 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 1789 u8 res20[240]; 1790 u32 scrtsr[8]; /* Core reset status */ 1791 u8 res21[224]; 1792 u32 pex1liodnr; /* PCI Express 1 LIODN */ 1793 u32 pex2liodnr; /* PCI Express 2 LIODN */ 1794 u32 pex3liodnr; /* PCI Express 3 LIODN */ 1795 u32 pex4liodnr; /* PCI Express 4 LIODN */ 1796 u32 rio1liodnr; /* RIO 1 LIODN */ 1797 u32 rio2liodnr; /* RIO 2 LIODN */ 1798 u32 rio3liodnr; /* RIO 3 LIODN */ 1799 u32 rio4liodnr; /* RIO 4 LIODN */ 1800 u32 usb1liodnr; /* USB 1 LIODN */ 1801 u32 usb2liodnr; /* USB 2 LIODN */ 1802 u32 usb3liodnr; /* USB 3 LIODN */ 1803 u32 usb4liodnr; /* USB 4 LIODN */ 1804 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ 1805 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ 1806 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ 1807 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ 1808 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */ 1809 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */ 1810 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */ 1811 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */ 1812 u32 sata1liodnr; /* SATA 1 LIODN */ 1813 u32 sata2liodnr; /* SATA 2 LIODN */ 1814 u32 sata3liodnr; /* SATA 3 LIODN */ 1815 u32 sata4liodnr; /* SATA 4 LIODN */ 1816 u8 res22[32]; 1817 u32 dma1liodnr; /* DMA 1 LIODN */ 1818 u32 dma2liodnr; /* DMA 2 LIODN */ 1819 u32 dma3liodnr; /* DMA 3 LIODN */ 1820 u32 dma4liodnr; /* DMA 4 LIODN */ 1821 u8 res23[48]; 1822 u8 res24[64]; 1823 u32 pblsr; /* Preboot loader status */ 1824 u32 pamubypenr; /* PAMU bypass enable */ 1825 u32 dmacr1; /* DMA control */ 1826 u8 res25[4]; 1827 u32 gensr1; /* General status */ 1828 u8 res26[12]; 1829 u32 gencr1; /* General control */ 1830 u8 res27[12]; 1831 u8 res28[4]; 1832 u32 cgensrl; /* Core general status */ 1833 u8 res29[8]; 1834 u8 res30[4]; 1835 u32 cgencrl; /* Core general control */ 1836 u8 res31[184]; 1837 u32 sriopstecr; /* SRIO prescaler timer enable control */ 1838 u32 dcsrcr; /* DCSR Control register */ 1839 u8 res32[1784]; 1840 u32 pmuxcr; /* Pin multiplexing control */ 1841 u8 res33[60]; 1842 u32 iovselsr; /* I/O voltage selection status */ 1843 u8 res34[28]; 1844 u32 ddrclkdr; /* DDR clock disable */ 1845 u8 res35; 1846 u32 elbcclkdr; /* eLBC clock disable */ 1847 u8 res36[20]; 1848 u32 sdhcpcr; /* eSDHC polarity configuration */ 1849 u8 res37[380]; 1850 } ccsr_gur_t; 1851 1852 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003 1853 #define FSL_CORENET_DCSR_SZ_4M 0x0 1854 #define FSL_CORENET_DCSR_SZ_1G 0x3 1855 1856 /* 1857 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance 1858 * everything after has RMan thus msg unit LIODN is used for maintenance 1859 */ 1860 #define rmuliodnr rio1maintliodnr 1861 1862 typedef struct ccsr_clk { 1863 u32 clkc0csr; /* Core 0 Clock control/status */ 1864 u8 res1[0x1c]; 1865 u32 clkc1csr; /* Core 1 Clock control/status */ 1866 u8 res2[0x1c]; 1867 u32 clkc2csr; /* Core 2 Clock control/status */ 1868 u8 res3[0x1c]; 1869 u32 clkc3csr; /* Core 3 Clock control/status */ 1870 u8 res4[0x1c]; 1871 u32 clkc4csr; /* Core 4 Clock control/status */ 1872 u8 res5[0x1c]; 1873 u32 clkc5csr; /* Core 5 Clock control/status */ 1874 u8 res6[0x1c]; 1875 u32 clkc6csr; /* Core 6 Clock control/status */ 1876 u8 res7[0x1c]; 1877 u32 clkc7csr; /* Core 7 Clock control/status */ 1878 u8 res8[0x71c]; 1879 u32 pllc1gsr; /* Cluster PLL 1 General Status */ 1880 u8 res10[0x1c]; 1881 u32 pllc2gsr; /* Cluster PLL 2 General Status */ 1882 u8 res11[0x1c]; 1883 u32 pllc3gsr; /* Cluster PLL 3 General Status */ 1884 u8 res12[0x1c]; 1885 u32 pllc4gsr; /* Cluster PLL 4 General Status */ 1886 u8 res13[0x39c]; 1887 u32 pllpgsr; /* Platform PLL General Status */ 1888 u8 res14[0x1c]; 1889 u32 plldgsr; /* DDR PLL General Status */ 1890 u8 res15[0x3dc]; 1891 } ccsr_clk_t; 1892 1893 typedef struct ccsr_rcpm { 1894 u8 res1[4]; 1895 u32 cdozsrl; /* Core Doze Status */ 1896 u8 res2[4]; 1897 u32 cdozcrl; /* Core Doze Control */ 1898 u8 res3[4]; 1899 u32 cnapsrl; /* Core Nap Status */ 1900 u8 res4[4]; 1901 u32 cnapcrl; /* Core Nap Control */ 1902 u8 res5[4]; 1903 u32 cdozpsrl; /* Core Doze Previous Status */ 1904 u8 res6[4]; 1905 u32 cdozpcrl; /* Core Doze Previous Control */ 1906 u8 res7[4]; 1907 u32 cwaitsrl; /* Core Wait Status */ 1908 u8 res8[8]; 1909 u32 powmgtcsr; /* Power Mangement Control & Status */ 1910 u8 res9[12]; 1911 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ 1912 u8 res10[12]; 1913 u8 res11[4]; 1914 u32 cpmimrl; /* Core PM IRQ Masking */ 1915 u8 res12[4]; 1916 u32 cpmcimrl; /* Core PM Critical IRQ Masking */ 1917 u8 res13[4]; 1918 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ 1919 u8 res14[4]; 1920 u32 cpmnmimrl; /* Core PM NMI Masking */ 1921 u8 res15[4]; 1922 u32 ctbenrl; /* Core Time Base Enable */ 1923 u8 res16[4]; 1924 u32 ctbclkselrl; /* Core Time Base Clock Select */ 1925 u8 res17[4]; 1926 u32 ctbhltcrl; /* Core Time Base Halt Control */ 1927 u8 res18[0xf68]; 1928 } ccsr_rcpm_t; 1929 1930 #else 1931 typedef struct ccsr_gur { 1932 u32 porpllsr; /* POR PLL ratio status */ 1933 #ifdef CONFIG_MPC8536 1934 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 1935 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 1936 #else 1937 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 1938 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 1939 #endif 1940 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 1941 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 1942 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e 1943 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 1944 u32 porbmsr; /* POR boot mode status */ 1945 #define MPC85xx_PORBMSR_HA 0x00070000 1946 #define MPC85xx_PORBMSR_HA_SHIFT 16 1947 u32 porimpscr; /* POR I/O impedance status & control */ 1948 u32 pordevsr; /* POR I/O device status regsiter */ 1949 #if defined(CONFIG_P1017) || defined(CONFIG_P1023) 1950 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 1951 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 1952 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 1953 #else 1954 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 1955 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 1956 #endif 1957 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 1958 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 1959 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 1960 #define MPC85xx_PORDEVSR_PCI1 0x00800000 1961 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 1962 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 1963 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 1964 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023) 1965 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 1966 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 1967 #else 1968 #if defined(CONFIG_P1010) 1969 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 1970 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 1971 #else 1972 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 1973 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 1974 #endif /* if defined(CONFIG_P1010) */ 1975 #endif 1976 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 1977 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 1978 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 1979 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 1980 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 1981 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 1982 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 1983 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 1984 u32 pordbgmsr; /* POR debug mode status */ 1985 u32 pordevsr2; /* POR I/O device status 2 */ 1986 /* The 8544 RM says this is bit 26, but it's really bit 24 */ 1987 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 1988 u8 res1[8]; 1989 u32 gpporcr; /* General-purpose POR configuration */ 1990 u8 res2[12]; 1991 #if defined(CONFIG_MPC8536) 1992 u32 gencfgr; /* General Configuration Register */ 1993 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 1994 #else 1995 u32 gpiocr; /* GPIO control */ 1996 #endif 1997 u8 res3[12]; 1998 #if defined(CONFIG_MPC8569) 1999 u32 plppar1; /* Platform port pin assignment 1 */ 2000 u32 plppar2; /* Platform port pin assignment 2 */ 2001 u32 plpdir1; /* Platform port pin direction 1 */ 2002 u32 plpdir2; /* Platform port pin direction 2 */ 2003 #else 2004 u32 gpoutdr; /* General-purpose output data */ 2005 u8 res4[12]; 2006 #endif 2007 u32 gpindr; /* General-purpose input data */ 2008 u8 res5[12]; 2009 u32 pmuxcr; /* Alt. function signal multiplex control */ 2010 #if defined(CONFIG_P1010) || defined(CONFIG_P1014) 2011 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 2012 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 2013 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 2014 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 2015 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 2016 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 2017 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 2018 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 2019 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 2020 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 2021 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 2022 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 2023 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 2024 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 2025 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 2026 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 2027 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 2028 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 2029 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 2030 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 2031 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 2032 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 2033 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 2034 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 2035 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 2036 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 2037 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 2038 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 2039 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 2040 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 2041 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 2042 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 2043 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 2044 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040 2045 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080 2046 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 2047 #define MPC85xx_PMUXCR_SPI_RES 0x00000030 2048 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 2049 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004 2050 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 2051 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C 2052 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001 2053 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 2054 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 2055 #endif 2056 #if defined(CONFIG_P1017) || defined(CONFIG_P1023) 2057 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000 2058 #else 2059 #define MPC85xx_PMUXCR_SD_DATA 0x80000000 2060 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 2061 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 2062 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 2063 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000 2064 #define MPC85xx_PMUXCR_QE0 0x00008000 2065 #define MPC85xx_PMUXCR_QE1 0x00004000 2066 #define MPC85xx_PMUXCR_QE2 0x00002000 2067 #define MPC85xx_PMUXCR_QE3 0x00001000 2068 #define MPC85xx_PMUXCR_QE4 0x00000800 2069 #define MPC85xx_PMUXCR_QE5 0x00000400 2070 #define MPC85xx_PMUXCR_QE6 0x00000200 2071 #define MPC85xx_PMUXCR_QE7 0x00000100 2072 #define MPC85xx_PMUXCR_QE8 0x00000080 2073 #define MPC85xx_PMUXCR_QE9 0x00000040 2074 #define MPC85xx_PMUXCR_QE10 0x00000020 2075 #define MPC85xx_PMUXCR_QE11 0x00000010 2076 #define MPC85xx_PMUXCR_QE12 0x00000008 2077 #endif 2078 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2079 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 2080 #define MPC85xx_PMUXCR_TDM 0x00014800 2081 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 2082 #define MPC85xx_PMUXCR_SPI 0x00000000 2083 #endif 2084 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ 2085 #if defined(CONFIG_P1010) || defined(CONFIG_P1014) 2086 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 2087 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000 2088 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000 2089 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 2090 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 2091 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 2092 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 2093 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 2094 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 2095 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 2096 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 2097 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 2098 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 2099 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 2100 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 2101 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 2102 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 2103 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 2104 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 2105 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 2106 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 2107 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 2108 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 2109 #endif 2110 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2111 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 2112 #define MPC85xx_PMUXCR2_USB 0x00150000 2113 #endif 2114 u8 res6[8]; 2115 u32 devdisr; /* Device disable control */ 2116 #define MPC85xx_DEVDISR_PCI1 0x80000000 2117 #define MPC85xx_DEVDISR_PCI2 0x40000000 2118 #define MPC85xx_DEVDISR_PCIE 0x20000000 2119 #define MPC85xx_DEVDISR_LBC 0x08000000 2120 #define MPC85xx_DEVDISR_PCIE2 0x04000000 2121 #define MPC85xx_DEVDISR_PCIE3 0x02000000 2122 #define MPC85xx_DEVDISR_SEC 0x01000000 2123 #define MPC85xx_DEVDISR_SRIO 0x00080000 2124 #define MPC85xx_DEVDISR_RMSG 0x00040000 2125 #define MPC85xx_DEVDISR_DDR 0x00010000 2126 #define MPC85xx_DEVDISR_CPU 0x00008000 2127 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU 2128 #define MPC85xx_DEVDISR_TB 0x00004000 2129 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB 2130 #define MPC85xx_DEVDISR_CPU1 0x00002000 2131 #define MPC85xx_DEVDISR_TB1 0x00001000 2132 #define MPC85xx_DEVDISR_DMA 0x00000400 2133 #define MPC85xx_DEVDISR_TSEC1 0x00000080 2134 #define MPC85xx_DEVDISR_TSEC2 0x00000040 2135 #define MPC85xx_DEVDISR_TSEC3 0x00000020 2136 #define MPC85xx_DEVDISR_TSEC4 0x00000010 2137 #define MPC85xx_DEVDISR_I2C 0x00000004 2138 #define MPC85xx_DEVDISR_DUART 0x00000002 2139 u8 res7[12]; 2140 u32 powmgtcsr; /* Power management status & control */ 2141 u8 res8[12]; 2142 u32 mcpsumr; /* Machine check summary */ 2143 u8 res9[12]; 2144 u32 pvr; /* Processor version */ 2145 u32 svr; /* System version */ 2146 u8 res10[8]; 2147 u32 rstcr; /* Reset control */ 2148 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) 2149 u8 res11a[76]; 2150 par_io_t qe_par_io[7]; 2151 u8 res11b[1600]; 2152 #elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ 2153 defined(CONFIG_P1021) || defined(CONFIG_P1025) 2154 u8 res11a[12]; 2155 u32 iovselsr; 2156 u8 res11b[60]; 2157 par_io_t qe_par_io[3]; 2158 u8 res11c[1496]; 2159 #else 2160 u8 res11a[1868]; 2161 #endif 2162 u32 clkdvdr; /* Clock Divide register */ 2163 u8 res12[1532]; 2164 u32 clkocr; /* Clock out select */ 2165 u8 res13[12]; 2166 u32 ddrdllcr; /* DDR DLL control */ 2167 u8 res14[12]; 2168 u32 lbcdllcr; /* LBC DLL control */ 2169 u8 res15[248]; 2170 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ 2171 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ 2172 u32 ddrioovcr; /* DDR IO Override Control */ 2173 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ 2174 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ 2175 u8 res16[52]; 2176 u32 sdhcdcr; /* SDHC debug control register */ 2177 u8 res17[61592]; 2178 } ccsr_gur_t; 2179 #endif 2180 2181 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */ 2182 2183 typedef struct serdes_corenet { 2184 struct { 2185 u32 rstctl; /* Reset Control Register */ 2186 #define SRDS_RSTCTL_RST 0x80000000 2187 #define SRDS_RSTCTL_RSTDONE 0x40000000 2188 #define SRDS_RSTCTL_RSTERR 0x20000000 2189 #define SRDS_RSTCTL_SDPD 0x00000020 2190 u32 pllcr0; /* PLL Control Register 0 */ 2191 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000 2192 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 2193 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 2194 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2195 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2196 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 2197 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 2198 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 2199 u32 pllcr1; /* PLL Control Register 1 */ 2200 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 2201 u32 res[5]; 2202 } bank[3]; 2203 u32 res1[12]; 2204 u32 srdstcalcr; /* TX Calibration Control */ 2205 u32 res2[3]; 2206 u32 srdsrcalcr; /* RX Calibration Control */ 2207 u32 res3[3]; 2208 u32 srdsgr0; /* General Register 0 */ 2209 u32 res4[11]; 2210 u32 srdspccr0; /* Protocol Converter Config 0 */ 2211 u32 srdspccr1; /* Protocol Converter Config 1 */ 2212 u32 srdspccr2; /* Protocol Converter Config 2 */ 2213 #define SRDS_PCCR2_RST_XGMII1 0x00800000 2214 #define SRDS_PCCR2_RST_XGMII2 0x00400000 2215 u32 res5[197]; 2216 struct { 2217 u32 gcr0; /* General Control Register 0 */ 2218 #define SRDS_GCR0_RRST 0x00400000 2219 #define SRDS_GCR0_1STLANE 0x00010000 2220 u32 gcr1; /* General Control Register 1 */ 2221 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 2222 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 2223 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 2224 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 2225 #define SRDS_GCR1_OPAD_CTL 0x04000000 2226 u32 res1[4]; 2227 u32 tecr0; /* TX Equalization Control Reg 0 */ 2228 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 2229 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 2230 u32 res3; 2231 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ 2232 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 2233 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000 2234 #define SRDS_TTLCR0_PM_DIS 0x00004000 2235 u32 res4[7]; 2236 } lane[24]; 2237 u32 res6[384]; 2238 } serdes_corenet_t; 2239 2240 enum { 2241 FSL_SRDS_B1_LANE_A = 0, 2242 FSL_SRDS_B1_LANE_B = 1, 2243 FSL_SRDS_B1_LANE_C = 2, 2244 FSL_SRDS_B1_LANE_D = 3, 2245 FSL_SRDS_B1_LANE_E = 4, 2246 FSL_SRDS_B1_LANE_F = 5, 2247 FSL_SRDS_B1_LANE_G = 6, 2248 FSL_SRDS_B1_LANE_H = 7, 2249 FSL_SRDS_B1_LANE_I = 8, 2250 FSL_SRDS_B1_LANE_J = 9, 2251 FSL_SRDS_B2_LANE_A = 16, 2252 FSL_SRDS_B2_LANE_B = 17, 2253 FSL_SRDS_B2_LANE_C = 18, 2254 FSL_SRDS_B2_LANE_D = 19, 2255 FSL_SRDS_B3_LANE_A = 20, 2256 FSL_SRDS_B3_LANE_B = 21, 2257 FSL_SRDS_B3_LANE_C = 22, 2258 FSL_SRDS_B3_LANE_D = 23, 2259 }; 2260 2261 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ 2262 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 2263 typedef struct ccsr_sec { 2264 u32 res0; 2265 u32 mcfgr; /* Master CFG Register */ 2266 u8 res1[0x8]; 2267 struct { 2268 u32 ms; /* Job Ring LIODN Register, MS */ 2269 u32 ls; /* Job Ring LIODN Register, LS */ 2270 } jrliodnr[4]; 2271 u8 res2[0x30]; 2272 struct { 2273 u32 ms; /* RTIC LIODN Register, MS */ 2274 u32 ls; /* RTIC LIODN Register, LS */ 2275 } rticliodnr[4]; 2276 u8 res3[0x1c]; 2277 u32 decorr; /* DECO Request Register */ 2278 struct { 2279 u32 ms; /* DECO LIODN Register, MS */ 2280 u32 ls; /* DECO LIODN Register, LS */ 2281 } decoliodnr[5]; 2282 u8 res4[0x58]; 2283 u32 dar; /* DECO Avail Register */ 2284 u32 drr; /* DECO Reset Register */ 2285 u8 res5[0xe78]; 2286 u32 crnr_ms; /* CHA Revision Number Register, MS */ 2287 u32 crnr_ls; /* CHA Revision Number Register, LS */ 2288 u32 ctpr_ms; /* Compile Time Parameters Register, MS */ 2289 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ 2290 u8 res6[0x10]; 2291 u32 far_ms; /* Fault Address Register, MS */ 2292 u32 far_ls; /* Fault Address Register, LS */ 2293 u32 falr; /* Fault Address LIODN Register */ 2294 u32 fadr; /* Fault Address Detail Register */ 2295 u8 res7[0x4]; 2296 u32 csta; /* CAAM Status Register */ 2297 u8 res8[0x8]; 2298 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ 2299 u32 ccbvid; /* CHA Cluster Block Version ID Register */ 2300 u32 chavid_ms; /* CHA Version ID Register, MS */ 2301 u32 chavid_ls; /* CHA Version ID Register, LS */ 2302 u32 chanum_ms; /* CHA Number Register, MS */ 2303 u32 chanum_ls; /* CHA Number Register, LS */ 2304 u32 secvid_ms; /* SEC Version ID Register, MS */ 2305 u32 secvid_ls; /* SEC Version ID Register, LS */ 2306 u8 res9[0x6020]; 2307 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ 2308 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ 2309 u8 res10[0x8fd8]; 2310 } ccsr_sec_t; 2311 2312 #define SEC_CTPR_MS_AXI_LIODN 0x08000000 2313 #define SEC_CTPR_MS_QI 0x02000000 2314 #define SEC_RVID_MA 0x0f000000 2315 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 2316 #define SEC_CHANUM_MS_JRNUM_SHIFT 28 2317 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 2318 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 2319 #endif 2320 2321 typedef struct ccsr_qman { 2322 struct { 2323 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 2324 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 2325 u32 res; 2326 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */ 2327 } qcsp[32]; 2328 2329 /* Not actually reserved, but irrelevant to u-boot */ 2330 u8 res[0xbf8 - 0x200]; 2331 u32 ip_rev_1; 2332 u32 ip_rev_2; 2333 u32 fqd_bare; /* FQD Extended Base Addr Register */ 2334 u32 fqd_bar; /* FQD Base Addr Register */ 2335 u8 res1[0x8]; 2336 u32 fqd_ar; /* FQD Attributes Register */ 2337 u8 res2[0xc]; 2338 u32 pfdr_bare; /* PFDR Extended Base Addr Register */ 2339 u32 pfdr_bar; /* PFDR Base Addr Register */ 2340 u8 res3[0x8]; 2341 u32 pfdr_ar; /* PFDR Attributes Register */ 2342 u8 res4[0x4c]; 2343 u32 qcsp_bare; /* QCSP Extended Base Addr Register */ 2344 u32 qcsp_bar; /* QCSP Base Addr Register */ 2345 u8 res5[0x78]; 2346 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ 2347 u32 srcidr; /* Source ID Register */ 2348 u32 liodnr; /* LIODN Register */ 2349 u8 res6[4]; 2350 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ 2351 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ 2352 u8 res7[0x2e8]; 2353 } ccsr_qman_t; 2354 2355 typedef struct ccsr_bman { 2356 /* Not actually reserved, but irrelevant to u-boot */ 2357 u8 res[0xbf8]; 2358 u32 ip_rev_1; 2359 u32 ip_rev_2; 2360 u32 fbpr_bare; /* FBPR Extended Base Addr Register */ 2361 u32 fbpr_bar; /* FBPR Base Addr Register */ 2362 u8 res1[0x8]; 2363 u32 fbpr_ar; /* FBPR Attributes Register */ 2364 u8 res2[0xf0]; 2365 u32 srcidr; /* Source ID Register */ 2366 u32 liodnr; /* LIODN Register */ 2367 u8 res7[0x2f4]; 2368 } ccsr_bman_t; 2369 2370 typedef struct ccsr_pme { 2371 u8 res0[0x804]; 2372 u32 liodnbr; /* LIODN Base Register */ 2373 u8 res1[0x1f8]; 2374 u32 srcidr; /* Source ID Register */ 2375 u8 res2[8]; 2376 u32 liodnr; /* LIODN Register */ 2377 u8 res3[0x1e8]; 2378 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/ 2379 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/ 2380 u8 res4[0x400]; 2381 } ccsr_pme_t; 2382 2383 typedef struct ccsr_usb_phy { 2384 u8 res0[0x18]; 2385 u32 usb_enable_override; 2386 u8 res[0xe4]; 2387 } ccsr_usb_phy_t; 2388 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 2389 2390 #ifdef CONFIG_SYS_FSL_RAID_ENGINE 2391 struct ccsr_raide { 2392 u8 res0[0x543]; 2393 u32 liodnbr; /* LIODN Base Register */ 2394 u8 res1[0xab8]; 2395 struct { 2396 struct { 2397 u32 cfg0; /* cfg register 0 */ 2398 u32 cfg1; /* cfg register 1 */ 2399 u8 res1[0x3f8]; 2400 } ring[2]; 2401 u8 res[0x800]; 2402 } jq[2]; 2403 }; 2404 #endif 2405 2406 #ifdef CONFIG_SYS_DPAA_RMAN 2407 struct ccsr_rman { 2408 u8 res0[0xf64]; 2409 u32 mmliodnbr; /* Message Manager LIODN Base Register */ 2410 u32 mmitar; /* RMAN Inbound Translation Address Register */ 2411 u32 mmitdr; /* RMAN Inbound Translation Data Register */ 2412 u8 res4[0x1f090]; 2413 }; 2414 #endif 2415 2416 #ifdef CONFIG_FSL_CORENET 2417 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 2418 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 2419 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 2420 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 2421 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 2422 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 2423 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 2424 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 2425 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 2426 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET 2427 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 2428 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 2429 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 2430 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 2431 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 2432 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 2433 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 2434 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 2435 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 2436 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 2437 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 2438 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET 2439 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 2440 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 2441 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 2442 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 2443 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 2444 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 2445 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 2446 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 2447 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 2448 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 2449 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 2450 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 2451 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 2452 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 2453 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 2454 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 2455 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 2456 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 2457 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 2458 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 2459 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 2460 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 2461 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 2462 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 2463 #else 2464 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 2465 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 2466 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 2467 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 2468 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 2469 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 2470 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 2471 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 2472 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 2473 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 2474 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 2475 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) 2476 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 2477 #else 2478 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 2479 #endif 2480 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 2481 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 2482 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 2483 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 2484 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 2485 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 2486 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 2487 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 2488 #ifdef CONFIG_TSECV2 2489 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 2490 #else 2491 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 2492 #endif 2493 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 2494 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 2495 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 2496 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 2497 #define CONFIG_SYS_SNVS_OFFSET 0xE6000 2498 #define CONFIG_SYS_SFP_OFFSET 0xE7000 2499 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 2500 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 2501 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 2502 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 2503 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 2504 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 2505 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 2506 #endif 2507 2508 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 2509 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 2510 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 2511 2512 #define CONFIG_SYS_FSL_CPC_ADDR \ 2513 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) 2514 #define CONFIG_SYS_FSL_QMAN_ADDR \ 2515 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) 2516 #define CONFIG_SYS_FSL_BMAN_ADDR \ 2517 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) 2518 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ 2519 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) 2520 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ 2521 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) 2522 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ 2523 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) 2524 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ 2525 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) 2526 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ 2527 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) 2528 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ 2529 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) 2530 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ 2531 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) 2532 #define CONFIG_SYS_MPC85xx_ECM_ADDR \ 2533 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) 2534 #define CONFIG_SYS_MPC85xx_DDR_ADDR \ 2535 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) 2536 #define CONFIG_SYS_MPC85xx_DDR2_ADDR \ 2537 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) 2538 #define CONFIG_SYS_LBC_ADDR \ 2539 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) 2540 #define CONFIG_SYS_IFC_ADDR \ 2541 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) 2542 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ 2543 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) 2544 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ 2545 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) 2546 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ 2547 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) 2548 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \ 2549 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) 2550 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \ 2551 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) 2552 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \ 2553 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) 2554 #define CONFIG_SYS_MPC85xx_L2_ADDR \ 2555 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) 2556 #define CONFIG_SYS_MPC85xx_DMA_ADDR \ 2557 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) 2558 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ 2559 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) 2560 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \ 2561 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) 2562 #define CONFIG_SYS_MPC85xx_CPM_ADDR \ 2563 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) 2564 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ 2565 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET) 2566 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ 2567 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 2568 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ 2569 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) 2570 #define CONFIG_SYS_MPC85xx_USB_ADDR \ 2571 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) 2572 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ 2573 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) 2574 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ 2575 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) 2576 #define CONFIG_SYS_FSL_SEC_ADDR \ 2577 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 2578 #define CONFIG_SYS_FSL_FM1_ADDR \ 2579 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 2580 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 2581 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 2582 #define CONFIG_SYS_FSL_FM2_ADDR \ 2583 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) 2584 #define CONFIG_SYS_FSL_SRIO_ADDR \ 2585 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) 2586 2587 #define CONFIG_SYS_PCI1_ADDR \ 2588 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) 2589 #define CONFIG_SYS_PCI2_ADDR \ 2590 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) 2591 #define CONFIG_SYS_PCIE1_ADDR \ 2592 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) 2593 #define CONFIG_SYS_PCIE2_ADDR \ 2594 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) 2595 #define CONFIG_SYS_PCIE3_ADDR \ 2596 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) 2597 #define CONFIG_SYS_PCIE4_ADDR \ 2598 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) 2599 2600 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 2601 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 2602 2603 #endif /*__IMMAP_85xx__*/ 2604