1 /* 2 * MPC85xx Internal Memory Map 3 * 4 * Copyright 2007-2012 Freescale Semiconductor, Inc. 5 * 6 * Copyright(c) 2002,2003 Motorola Inc. 7 * Xianghua Xiao (x.xiao@motorola.com) 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __IMMAP_85xx__ 13 #define __IMMAP_85xx__ 14 15 #include <asm/types.h> 16 #include <asm/fsl_dma.h> 17 #include <asm/fsl_i2c.h> 18 #include <fsl_ifc.h> 19 #include <fsl_sec.h> 20 #include <fsl_sfp.h> 21 #include <asm/fsl_lbc.h> 22 #include <fsl_fman.h> 23 #include <fsl_immap.h> 24 25 typedef struct ccsr_local { 26 u32 ccsrbarh; /* CCSR Base Addr High */ 27 u32 ccsrbarl; /* CCSR Base Addr Low */ 28 u32 ccsrar; /* CCSR Attr */ 29 #define CCSRAR_C 0x80000000 /* Commit */ 30 u8 res1[4]; 31 u32 altcbarh; /* Alternate Configuration Base Addr High */ 32 u32 altcbarl; /* Alternate Configuration Base Addr Low */ 33 u32 altcar; /* Alternate Configuration Attr */ 34 u8 res2[4]; 35 u32 bstrh; /* Boot space translation high */ 36 u32 bstrl; /* Boot space translation Low */ 37 u32 bstrar; /* Boot space translation attributes */ 38 u8 res3[0xbd4]; 39 struct { 40 u32 lawbarh; /* LAWn base addr high */ 41 u32 lawbarl; /* LAWn base addr low */ 42 u32 lawar; /* LAWn attributes */ 43 u8 res4[4]; 44 } law[32]; 45 u8 res35[0x204]; 46 } ccsr_local_t; 47 48 /* Local-Access Registers & ECM Registers */ 49 typedef struct ccsr_local_ecm { 50 u32 ccsrbar; /* CCSR Base Addr */ 51 u8 res1[4]; 52 u32 altcbar; /* Alternate Configuration Base Addr */ 53 u8 res2[4]; 54 u32 altcar; /* Alternate Configuration Attr */ 55 u8 res3[12]; 56 u32 bptr; /* Boot Page Translation */ 57 u8 res4[3044]; 58 u32 lawbar0; /* Local Access Window 0 Base Addr */ 59 u8 res5[4]; 60 u32 lawar0; /* Local Access Window 0 Attrs */ 61 u8 res6[20]; 62 u32 lawbar1; /* Local Access Window 1 Base Addr */ 63 u8 res7[4]; 64 u32 lawar1; /* Local Access Window 1 Attrs */ 65 u8 res8[20]; 66 u32 lawbar2; /* Local Access Window 2 Base Addr */ 67 u8 res9[4]; 68 u32 lawar2; /* Local Access Window 2 Attrs */ 69 u8 res10[20]; 70 u32 lawbar3; /* Local Access Window 3 Base Addr */ 71 u8 res11[4]; 72 u32 lawar3; /* Local Access Window 3 Attrs */ 73 u8 res12[20]; 74 u32 lawbar4; /* Local Access Window 4 Base Addr */ 75 u8 res13[4]; 76 u32 lawar4; /* Local Access Window 4 Attrs */ 77 u8 res14[20]; 78 u32 lawbar5; /* Local Access Window 5 Base Addr */ 79 u8 res15[4]; 80 u32 lawar5; /* Local Access Window 5 Attrs */ 81 u8 res16[20]; 82 u32 lawbar6; /* Local Access Window 6 Base Addr */ 83 u8 res17[4]; 84 u32 lawar6; /* Local Access Window 6 Attrs */ 85 u8 res18[20]; 86 u32 lawbar7; /* Local Access Window 7 Base Addr */ 87 u8 res19[4]; 88 u32 lawar7; /* Local Access Window 7 Attrs */ 89 u8 res19_8a[20]; 90 u32 lawbar8; /* Local Access Window 8 Base Addr */ 91 u8 res19_8b[4]; 92 u32 lawar8; /* Local Access Window 8 Attrs */ 93 u8 res19_9a[20]; 94 u32 lawbar9; /* Local Access Window 9 Base Addr */ 95 u8 res19_9b[4]; 96 u32 lawar9; /* Local Access Window 9 Attrs */ 97 u8 res19_10a[20]; 98 u32 lawbar10; /* Local Access Window 10 Base Addr */ 99 u8 res19_10b[4]; 100 u32 lawar10; /* Local Access Window 10 Attrs */ 101 u8 res19_11a[20]; 102 u32 lawbar11; /* Local Access Window 11 Base Addr */ 103 u8 res19_11b[4]; 104 u32 lawar11; /* Local Access Window 11 Attrs */ 105 u8 res20[652]; 106 u32 eebacr; /* ECM CCB Addr Configuration */ 107 u8 res21[12]; 108 u32 eebpcr; /* ECM CCB Port Configuration */ 109 u8 res22[3564]; 110 u32 eedr; /* ECM Error Detect */ 111 u8 res23[4]; 112 u32 eeer; /* ECM Error Enable */ 113 u32 eeatr; /* ECM Error Attrs Capture */ 114 u32 eeadr; /* ECM Error Addr Capture */ 115 u8 res24[492]; 116 } ccsr_local_ecm_t; 117 118 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ 119 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ 120 121 /* I2C Registers */ 122 typedef struct ccsr_i2c { 123 struct fsl_i2c i2c[1]; 124 u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; 125 } ccsr_i2c_t; 126 127 #if defined(CONFIG_MPC8540) \ 128 || defined(CONFIG_MPC8541) \ 129 || defined(CONFIG_MPC8548) \ 130 || defined(CONFIG_MPC8555) 131 /* DUART Registers */ 132 typedef struct ccsr_duart { 133 u8 res1[1280]; 134 /* URBR1, UTHR1, UDLB1 with the same addr */ 135 u8 urbr1_uthr1_udlb1; 136 /* UIER1, UDMB1 with the same addr01 */ 137 u8 uier1_udmb1; 138 /* UIIR1, UFCR1, UAFR1 with the same addr */ 139 u8 uiir1_ufcr1_uafr1; 140 u8 ulcr1; /* UART1 Line Control */ 141 u8 umcr1; /* UART1 Modem Control */ 142 u8 ulsr1; /* UART1 Line Status */ 143 u8 umsr1; /* UART1 Modem Status */ 144 u8 uscr1; /* UART1 Scratch */ 145 u8 res2[8]; 146 u8 udsr1; /* UART1 DMA Status */ 147 u8 res3[239]; 148 /* URBR2, UTHR2, UDLB2 with the same addr */ 149 u8 urbr2_uthr2_udlb2; 150 /* UIER2, UDMB2 with the same addr */ 151 u8 uier2_udmb2; 152 /* UIIR2, UFCR2, UAFR2 with the same addr */ 153 u8 uiir2_ufcr2_uafr2; 154 u8 ulcr2; /* UART2 Line Control */ 155 u8 umcr2; /* UART2 Modem Control */ 156 u8 ulsr2; /* UART2 Line Status */ 157 u8 umsr2; /* UART2 Modem Status */ 158 u8 uscr2; /* UART2 Scratch */ 159 u8 res4[8]; 160 u8 udsr2; /* UART2 DMA Status */ 161 u8 res5[2543]; 162 } ccsr_duart_t; 163 #else /* MPC8560 uses UART on its CPM */ 164 typedef struct ccsr_duart { 165 u8 res[4096]; 166 } ccsr_duart_t; 167 #endif 168 169 /* eSPI Registers */ 170 typedef struct ccsr_espi { 171 u32 mode; /* eSPI mode */ 172 u32 event; /* eSPI event */ 173 u32 mask; /* eSPI mask */ 174 u32 com; /* eSPI command */ 175 u32 tx; /* eSPI transmit FIFO access */ 176 u32 rx; /* eSPI receive FIFO access */ 177 u8 res1[8]; /* reserved */ 178 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ 179 u8 res2[4048]; /* fill up to 0x1000 */ 180 } ccsr_espi_t; 181 182 /* PCI Registers */ 183 typedef struct ccsr_pcix { 184 u32 cfg_addr; /* PCIX Configuration Addr */ 185 u32 cfg_data; /* PCIX Configuration Data */ 186 u32 int_ack; /* PCIX IRQ Acknowledge */ 187 u8 res000c[52]; 188 u32 liodn_base; /* PCIX LIODN base register */ 189 u8 res0044[2996]; 190 u32 ipver1; /* PCIX IP block revision register 1 */ 191 u32 ipver2; /* PCIX IP block revision register 2 */ 192 u32 potar0; /* PCIX Outbound Transaction Addr 0 */ 193 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ 194 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ 195 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ 196 u32 powar0; /* PCIX Outbound Window Attrs 0 */ 197 u8 res2[12]; 198 u32 potar1; /* PCIX Outbound Transaction Addr 1 */ 199 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ 200 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ 201 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ 202 u32 powar1; /* PCIX Outbound Window Attrs 1 */ 203 u8 res3[12]; 204 u32 potar2; /* PCIX Outbound Transaction Addr 2 */ 205 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ 206 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ 207 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ 208 u32 powar2; /* PCIX Outbound Window Attrs 2 */ 209 u8 res4[12]; 210 u32 potar3; /* PCIX Outbound Transaction Addr 3 */ 211 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ 212 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ 213 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ 214 u32 powar3; /* PCIX Outbound Window Attrs 3 */ 215 u8 res5[12]; 216 u32 potar4; /* PCIX Outbound Transaction Addr 4 */ 217 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ 218 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ 219 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ 220 u32 powar4; /* PCIX Outbound Window Attrs 4 */ 221 u8 res6[268]; 222 u32 pitar3; /* PCIX Inbound Translation Addr 3 */ 223 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ 224 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ 225 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ 226 u32 piwar3; /* PCIX Inbound Window Attrs 3 */ 227 u8 res7[12]; 228 u32 pitar2; /* PCIX Inbound Translation Addr 2 */ 229 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ 230 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ 231 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ 232 u32 piwar2; /* PCIX Inbound Window Attrs 2 */ 233 u8 res8[12]; 234 u32 pitar1; /* PCIX Inbound Translation Addr 1 */ 235 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ 236 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ 237 u8 res9[4]; 238 u32 piwar1; /* PCIX Inbound Window Attrs 1 */ 239 u8 res10[12]; 240 u32 pedr; /* PCIX Error Detect */ 241 u32 pecdr; /* PCIX Error Capture Disable */ 242 u32 peer; /* PCIX Error Enable */ 243 u32 peattrcr; /* PCIX Error Attrs Capture */ 244 u32 peaddrcr; /* PCIX Error Addr Capture */ 245 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ 246 u32 pedlcr; /* PCIX Error Data Low Capture */ 247 u32 pedhcr; /* PCIX Error Error Data High Capture */ 248 u32 gas_timr; /* PCIX Gasket Timer */ 249 u8 res11[476]; 250 } ccsr_pcix_t; 251 252 #define PCIX_COMMAND 0x62 253 #define POWAR_EN 0x80000000 254 #define POWAR_IO_READ 0x00080000 255 #define POWAR_MEM_READ 0x00040000 256 #define POWAR_IO_WRITE 0x00008000 257 #define POWAR_MEM_WRITE 0x00004000 258 #define POWAR_MEM_512M 0x0000001c 259 #define POWAR_IO_1M 0x00000013 260 261 #define PIWAR_EN 0x80000000 262 #define PIWAR_PF 0x20000000 263 #define PIWAR_LOCAL 0x00f00000 264 #define PIWAR_READ_SNOOP 0x00050000 265 #define PIWAR_WRITE_SNOOP 0x00005000 266 #define PIWAR_MEM_2G 0x0000001e 267 268 typedef struct ccsr_gpio { 269 u32 gpdir; 270 u32 gpodr; 271 u32 gpdat; 272 u32 gpier; 273 u32 gpimr; 274 u32 gpicr; 275 } ccsr_gpio_t; 276 277 /* L2 Cache Registers */ 278 typedef struct ccsr_l2cache { 279 u32 l2ctl; /* L2 configuration 0 */ 280 u8 res1[12]; 281 u32 l2cewar0; /* L2 cache external write addr 0 */ 282 u8 res2[4]; 283 u32 l2cewcr0; /* L2 cache external write control 0 */ 284 u8 res3[4]; 285 u32 l2cewar1; /* L2 cache external write addr 1 */ 286 u8 res4[4]; 287 u32 l2cewcr1; /* L2 cache external write control 1 */ 288 u8 res5[4]; 289 u32 l2cewar2; /* L2 cache external write addr 2 */ 290 u8 res6[4]; 291 u32 l2cewcr2; /* L2 cache external write control 2 */ 292 u8 res7[4]; 293 u32 l2cewar3; /* L2 cache external write addr 3 */ 294 u8 res8[4]; 295 u32 l2cewcr3; /* L2 cache external write control 3 */ 296 u8 res9[180]; 297 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ 298 u8 res10[4]; 299 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ 300 u8 res11[3316]; 301 u32 l2errinjhi; /* L2 error injection mask high */ 302 u32 l2errinjlo; /* L2 error injection mask low */ 303 u32 l2errinjctl; /* L2 error injection tag/ECC control */ 304 u8 res12[20]; 305 u32 l2captdatahi; /* L2 error data high capture */ 306 u32 l2captdatalo; /* L2 error data low capture */ 307 u32 l2captecc; /* L2 error ECC capture */ 308 u8 res13[20]; 309 u32 l2errdet; /* L2 error detect */ 310 u32 l2errdis; /* L2 error disable */ 311 u32 l2errinten; /* L2 error interrupt enable */ 312 u32 l2errattr; /* L2 error attributes capture */ 313 u32 l2erraddr; /* L2 error addr capture */ 314 u8 res14[4]; 315 u32 l2errctl; /* L2 error control */ 316 u8 res15[420]; 317 } ccsr_l2cache_t; 318 319 #define MPC85xx_L2CTL_L2E 0x80000000 320 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 321 #define MPC85xx_L2ERRDIS_MBECC 0x00000008 322 #define MPC85xx_L2ERRDIS_SBECC 0x00000004 323 324 /* DMA Registers */ 325 typedef struct ccsr_dma { 326 u8 res1[256]; 327 struct fsl_dma dma[4]; 328 u32 dgsr; /* DMA General Status */ 329 u8 res2[11516]; 330 } ccsr_dma_t; 331 332 /* tsec */ 333 typedef struct ccsr_tsec { 334 u8 res1[16]; 335 u32 ievent; /* IRQ Event */ 336 u32 imask; /* IRQ Mask */ 337 u32 edis; /* Error Disabled */ 338 u8 res2[4]; 339 u32 ecntrl; /* Ethernet Control */ 340 u32 minflr; /* Minimum Frame Len */ 341 u32 ptv; /* Pause Time Value */ 342 u32 dmactrl; /* DMA Control */ 343 u32 tbipa; /* TBI PHY Addr */ 344 u8 res3[88]; 345 u32 fifo_tx_thr; /* FIFO transmit threshold */ 346 u8 res4[8]; 347 u32 fifo_tx_starve; /* FIFO transmit starve */ 348 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ 349 u8 res5[96]; 350 u32 tctrl; /* TX Control */ 351 u32 tstat; /* TX Status */ 352 u8 res6[4]; 353 u32 tbdlen; /* TX Buffer Desc Data Len */ 354 u8 res7[16]; 355 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ 356 u32 ctbptr; /* Current TX Buffer Desc Ptr */ 357 u8 res8[88]; 358 u32 tbptrh; /* TX Buffer Desc Ptr High */ 359 u32 tbptr; /* TX Buffer Desc Ptr Low */ 360 u8 res9[120]; 361 u32 tbaseh; /* TX Desc Base Addr High */ 362 u32 tbase; /* TX Desc Base Addr */ 363 u8 res10[168]; 364 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ 365 u32 ostbdp; /* OOS TX Data Buffer Ptr */ 366 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ 367 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ 368 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ 369 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ 370 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ 371 u8 res11[52]; 372 u32 rctrl; /* RX Control */ 373 u32 rstat; /* RX Status */ 374 u8 res12[4]; 375 u32 rbdlen; /* RxBD Data Len */ 376 u8 res13[16]; 377 u32 crbptrh; /* Current RX Buffer Desc Ptr High */ 378 u32 crbptr; /* Current RX Buffer Desc Ptr */ 379 u8 res14[24]; 380 u32 mrblr; /* Maximum RX Buffer Len */ 381 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ 382 u8 res15[56]; 383 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ 384 u32 rbptr; /* RX Buffer Desc Ptr */ 385 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ 386 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ 387 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ 388 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ 389 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ 390 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ 391 u8 res16[96]; 392 u32 rbaseh; /* RX Desc Base Addr High 0 */ 393 u32 rbase; /* RX Desc Base Addr */ 394 u32 rbaseh1; /* RX Desc Base Addr High 1 */ 395 u32 rbasel1; /* RX Desc Base Addr Low 1 */ 396 u32 rbaseh2; /* RX Desc Base Addr High 2 */ 397 u32 rbasel2; /* RX Desc Base Addr Low 2 */ 398 u32 rbaseh3; /* RX Desc Base Addr High 3 */ 399 u32 rbasel3; /* RX Desc Base Addr Low 3 */ 400 u8 res17[224]; 401 u32 maccfg1; /* MAC Configuration 1 */ 402 u32 maccfg2; /* MAC Configuration 2 */ 403 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 404 u32 hafdup; /* Half Duplex */ 405 u32 maxfrm; /* Maximum Frame Len */ 406 u8 res18[12]; 407 u32 miimcfg; /* MII Management Configuration */ 408 u32 miimcom; /* MII Management Cmd */ 409 u32 miimadd; /* MII Management Addr */ 410 u32 miimcon; /* MII Management Control */ 411 u32 miimstat; /* MII Management Status */ 412 u32 miimind; /* MII Management Indicator */ 413 u8 res19[4]; 414 u32 ifstat; /* Interface Status */ 415 u32 macstnaddr1; /* Station Addr Part 1 */ 416 u32 macstnaddr2; /* Station Addr Part 2 */ 417 u8 res20[312]; 418 u32 tr64; /* TX & RX 64-byte Frame Counter */ 419 u32 tr127; /* TX & RX 65-127 byte Frame Counter */ 420 u32 tr255; /* TX & RX 128-255 byte Frame Counter */ 421 u32 tr511; /* TX & RX 256-511 byte Frame Counter */ 422 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ 423 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ 424 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ 425 u32 rbyt; /* RX Byte Counter */ 426 u32 rpkt; /* RX Packet Counter */ 427 u32 rfcs; /* RX FCS Error Counter */ 428 u32 rmca; /* RX Multicast Packet Counter */ 429 u32 rbca; /* RX Broadcast Packet Counter */ 430 u32 rxcf; /* RX Control Frame Packet Counter */ 431 u32 rxpf; /* RX Pause Frame Packet Counter */ 432 u32 rxuo; /* RX Unknown OP Code Counter */ 433 u32 raln; /* RX Alignment Error Counter */ 434 u32 rflr; /* RX Frame Len Error Counter */ 435 u32 rcde; /* RX Code Error Counter */ 436 u32 rcse; /* RX Carrier Sense Error Counter */ 437 u32 rund; /* RX Undersize Packet Counter */ 438 u32 rovr; /* RX Oversize Packet Counter */ 439 u32 rfrg; /* RX Fragments Counter */ 440 u32 rjbr; /* RX Jabber Counter */ 441 u32 rdrp; /* RX Drop Counter */ 442 u32 tbyt; /* TX Byte Counter Counter */ 443 u32 tpkt; /* TX Packet Counter */ 444 u32 tmca; /* TX Multicast Packet Counter */ 445 u32 tbca; /* TX Broadcast Packet Counter */ 446 u32 txpf; /* TX Pause Control Frame Counter */ 447 u32 tdfr; /* TX Deferral Packet Counter */ 448 u32 tedf; /* TX Excessive Deferral Packet Counter */ 449 u32 tscl; /* TX Single Collision Packet Counter */ 450 u32 tmcl; /* TX Multiple Collision Packet Counter */ 451 u32 tlcl; /* TX Late Collision Packet Counter */ 452 u32 txcl; /* TX Excessive Collision Packet Counter */ 453 u32 tncl; /* TX Total Collision Counter */ 454 u8 res21[4]; 455 u32 tdrp; /* TX Drop Frame Counter */ 456 u32 tjbr; /* TX Jabber Frame Counter */ 457 u32 tfcs; /* TX FCS Error Counter */ 458 u32 txcf; /* TX Control Frame Counter */ 459 u32 tovr; /* TX Oversize Frame Counter */ 460 u32 tund; /* TX Undersize Frame Counter */ 461 u32 tfrg; /* TX Fragments Frame Counter */ 462 u32 car1; /* Carry One */ 463 u32 car2; /* Carry Two */ 464 u32 cam1; /* Carry Mask One */ 465 u32 cam2; /* Carry Mask Two */ 466 u8 res22[192]; 467 u32 iaddr0; /* Indivdual addr 0 */ 468 u32 iaddr1; /* Indivdual addr 1 */ 469 u32 iaddr2; /* Indivdual addr 2 */ 470 u32 iaddr3; /* Indivdual addr 3 */ 471 u32 iaddr4; /* Indivdual addr 4 */ 472 u32 iaddr5; /* Indivdual addr 5 */ 473 u32 iaddr6; /* Indivdual addr 6 */ 474 u32 iaddr7; /* Indivdual addr 7 */ 475 u8 res23[96]; 476 u32 gaddr0; /* Global addr 0 */ 477 u32 gaddr1; /* Global addr 1 */ 478 u32 gaddr2; /* Global addr 2 */ 479 u32 gaddr3; /* Global addr 3 */ 480 u32 gaddr4; /* Global addr 4 */ 481 u32 gaddr5; /* Global addr 5 */ 482 u32 gaddr6; /* Global addr 6 */ 483 u32 gaddr7; /* Global addr 7 */ 484 u8 res24[96]; 485 u32 pmd0; /* Pattern Match Data */ 486 u8 res25[4]; 487 u32 pmask0; /* Pattern Mask */ 488 u8 res26[4]; 489 u32 pcntrl0; /* Pattern Match Control */ 490 u8 res27[4]; 491 u32 pattrb0; /* Pattern Match Attrs */ 492 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ 493 u32 pmd1; /* Pattern Match Data */ 494 u8 res28[4]; 495 u32 pmask1; /* Pattern Mask */ 496 u8 res29[4]; 497 u32 pcntrl1; /* Pattern Match Control */ 498 u8 res30[4]; 499 u32 pattrb1; /* Pattern Match Attrs */ 500 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ 501 u32 pmd2; /* Pattern Match Data */ 502 u8 res31[4]; 503 u32 pmask2; /* Pattern Mask */ 504 u8 res32[4]; 505 u32 pcntrl2; /* Pattern Match Control */ 506 u8 res33[4]; 507 u32 pattrb2; /* Pattern Match Attrs */ 508 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ 509 u32 pmd3; /* Pattern Match Data */ 510 u8 res34[4]; 511 u32 pmask3; /* Pattern Mask */ 512 u8 res35[4]; 513 u32 pcntrl3; /* Pattern Match Control */ 514 u8 res36[4]; 515 u32 pattrb3; /* Pattern Match Attrs */ 516 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ 517 u32 pmd4; /* Pattern Match Data */ 518 u8 res37[4]; 519 u32 pmask4; /* Pattern Mask */ 520 u8 res38[4]; 521 u32 pcntrl4; /* Pattern Match Control */ 522 u8 res39[4]; 523 u32 pattrb4; /* Pattern Match Attrs */ 524 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ 525 u32 pmd5; /* Pattern Match Data */ 526 u8 res40[4]; 527 u32 pmask5; /* Pattern Mask */ 528 u8 res41[4]; 529 u32 pcntrl5; /* Pattern Match Control */ 530 u8 res42[4]; 531 u32 pattrb5; /* Pattern Match Attrs */ 532 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ 533 u32 pmd6; /* Pattern Match Data */ 534 u8 res43[4]; 535 u32 pmask6; /* Pattern Mask */ 536 u8 res44[4]; 537 u32 pcntrl6; /* Pattern Match Control */ 538 u8 res45[4]; 539 u32 pattrb6; /* Pattern Match Attrs */ 540 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ 541 u32 pmd7; /* Pattern Match Data */ 542 u8 res46[4]; 543 u32 pmask7; /* Pattern Mask */ 544 u8 res47[4]; 545 u32 pcntrl7; /* Pattern Match Control */ 546 u8 res48[4]; 547 u32 pattrb7; /* Pattern Match Attrs */ 548 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ 549 u32 pmd8; /* Pattern Match Data */ 550 u8 res49[4]; 551 u32 pmask8; /* Pattern Mask */ 552 u8 res50[4]; 553 u32 pcntrl8; /* Pattern Match Control */ 554 u8 res51[4]; 555 u32 pattrb8; /* Pattern Match Attrs */ 556 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ 557 u32 pmd9; /* Pattern Match Data */ 558 u8 res52[4]; 559 u32 pmask9; /* Pattern Mask */ 560 u8 res53[4]; 561 u32 pcntrl9; /* Pattern Match Control */ 562 u8 res54[4]; 563 u32 pattrb9; /* Pattern Match Attrs */ 564 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ 565 u32 pmd10; /* Pattern Match Data */ 566 u8 res55[4]; 567 u32 pmask10; /* Pattern Mask */ 568 u8 res56[4]; 569 u32 pcntrl10; /* Pattern Match Control */ 570 u8 res57[4]; 571 u32 pattrb10; /* Pattern Match Attrs */ 572 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ 573 u32 pmd11; /* Pattern Match Data */ 574 u8 res58[4]; 575 u32 pmask11; /* Pattern Mask */ 576 u8 res59[4]; 577 u32 pcntrl11; /* Pattern Match Control */ 578 u8 res60[4]; 579 u32 pattrb11; /* Pattern Match Attrs */ 580 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ 581 u32 pmd12; /* Pattern Match Data */ 582 u8 res61[4]; 583 u32 pmask12; /* Pattern Mask */ 584 u8 res62[4]; 585 u32 pcntrl12; /* Pattern Match Control */ 586 u8 res63[4]; 587 u32 pattrb12; /* Pattern Match Attrs */ 588 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ 589 u32 pmd13; /* Pattern Match Data */ 590 u8 res64[4]; 591 u32 pmask13; /* Pattern Mask */ 592 u8 res65[4]; 593 u32 pcntrl13; /* Pattern Match Control */ 594 u8 res66[4]; 595 u32 pattrb13; /* Pattern Match Attrs */ 596 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ 597 u32 pmd14; /* Pattern Match Data */ 598 u8 res67[4]; 599 u32 pmask14; /* Pattern Mask */ 600 u8 res68[4]; 601 u32 pcntrl14; /* Pattern Match Control */ 602 u8 res69[4]; 603 u32 pattrb14; /* Pattern Match Attrs */ 604 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ 605 u32 pmd15; /* Pattern Match Data */ 606 u8 res70[4]; 607 u32 pmask15; /* Pattern Mask */ 608 u8 res71[4]; 609 u32 pcntrl15; /* Pattern Match Control */ 610 u8 res72[4]; 611 u32 pattrb15; /* Pattern Match Attrs */ 612 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ 613 u8 res73[248]; 614 u32 attr; /* Attrs */ 615 u32 attreli; /* Attrs Extract Len & Idx */ 616 u8 res74[1024]; 617 } ccsr_tsec_t; 618 619 /* PIC Registers */ 620 typedef struct ccsr_pic { 621 u8 res1[64]; 622 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ 623 u8 res2[12]; 624 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ 625 u8 res3[12]; 626 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ 627 u8 res4[12]; 628 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ 629 u8 res5[12]; 630 u32 ctpr; /* Current Task Priority */ 631 u8 res6[12]; 632 u32 whoami; /* Who Am I */ 633 u8 res7[12]; 634 u32 iack; /* IRQ Acknowledge */ 635 u8 res8[12]; 636 u32 eoi; /* End Of IRQ */ 637 u8 res9[3916]; 638 u32 frr; /* Feature Reporting */ 639 u8 res10[28]; 640 u32 gcr; /* Global Configuration */ 641 #define MPC85xx_PICGCR_RST 0x80000000 642 #define MPC85xx_PICGCR_M 0x20000000 643 u8 res11[92]; 644 u32 vir; /* Vendor Identification */ 645 u8 res12[12]; 646 u32 pir; /* Processor Initialization */ 647 u8 res13[12]; 648 u32 ipivpr0; /* IPI Vector/Priority 0 */ 649 u8 res14[12]; 650 u32 ipivpr1; /* IPI Vector/Priority 1 */ 651 u8 res15[12]; 652 u32 ipivpr2; /* IPI Vector/Priority 2 */ 653 u8 res16[12]; 654 u32 ipivpr3; /* IPI Vector/Priority 3 */ 655 u8 res17[12]; 656 u32 svr; /* Spurious Vector */ 657 u8 res18[12]; 658 u32 tfrr; /* Timer Frequency Reporting */ 659 u8 res19[12]; 660 u32 gtccr0; /* Global Timer Current Count 0 */ 661 u8 res20[12]; 662 u32 gtbcr0; /* Global Timer Base Count 0 */ 663 u8 res21[12]; 664 u32 gtvpr0; /* Global Timer Vector/Priority 0 */ 665 u8 res22[12]; 666 u32 gtdr0; /* Global Timer Destination 0 */ 667 u8 res23[12]; 668 u32 gtccr1; /* Global Timer Current Count 1 */ 669 u8 res24[12]; 670 u32 gtbcr1; /* Global Timer Base Count 1 */ 671 u8 res25[12]; 672 u32 gtvpr1; /* Global Timer Vector/Priority 1 */ 673 u8 res26[12]; 674 u32 gtdr1; /* Global Timer Destination 1 */ 675 u8 res27[12]; 676 u32 gtccr2; /* Global Timer Current Count 2 */ 677 u8 res28[12]; 678 u32 gtbcr2; /* Global Timer Base Count 2 */ 679 u8 res29[12]; 680 u32 gtvpr2; /* Global Timer Vector/Priority 2 */ 681 u8 res30[12]; 682 u32 gtdr2; /* Global Timer Destination 2 */ 683 u8 res31[12]; 684 u32 gtccr3; /* Global Timer Current Count 3 */ 685 u8 res32[12]; 686 u32 gtbcr3; /* Global Timer Base Count 3 */ 687 u8 res33[12]; 688 u32 gtvpr3; /* Global Timer Vector/Priority 3 */ 689 u8 res34[12]; 690 u32 gtdr3; /* Global Timer Destination 3 */ 691 u8 res35[268]; 692 u32 tcr; /* Timer Control */ 693 u8 res36[12]; 694 u32 irqsr0; /* IRQ_OUT Summary 0 */ 695 u8 res37[12]; 696 u32 irqsr1; /* IRQ_OUT Summary 1 */ 697 u8 res38[12]; 698 u32 cisr0; /* Critical IRQ Summary 0 */ 699 u8 res39[12]; 700 u32 cisr1; /* Critical IRQ Summary 1 */ 701 u8 res40[188]; 702 u32 msgr0; /* Message 0 */ 703 u8 res41[12]; 704 u32 msgr1; /* Message 1 */ 705 u8 res42[12]; 706 u32 msgr2; /* Message 2 */ 707 u8 res43[12]; 708 u32 msgr3; /* Message 3 */ 709 u8 res44[204]; 710 u32 mer; /* Message Enable */ 711 u8 res45[12]; 712 u32 msr; /* Message Status */ 713 u8 res46[60140]; 714 u32 eivpr0; /* External IRQ Vector/Priority 0 */ 715 u8 res47[12]; 716 u32 eidr0; /* External IRQ Destination 0 */ 717 u8 res48[12]; 718 u32 eivpr1; /* External IRQ Vector/Priority 1 */ 719 u8 res49[12]; 720 u32 eidr1; /* External IRQ Destination 1 */ 721 u8 res50[12]; 722 u32 eivpr2; /* External IRQ Vector/Priority 2 */ 723 u8 res51[12]; 724 u32 eidr2; /* External IRQ Destination 2 */ 725 u8 res52[12]; 726 u32 eivpr3; /* External IRQ Vector/Priority 3 */ 727 u8 res53[12]; 728 u32 eidr3; /* External IRQ Destination 3 */ 729 u8 res54[12]; 730 u32 eivpr4; /* External IRQ Vector/Priority 4 */ 731 u8 res55[12]; 732 u32 eidr4; /* External IRQ Destination 4 */ 733 u8 res56[12]; 734 u32 eivpr5; /* External IRQ Vector/Priority 5 */ 735 u8 res57[12]; 736 u32 eidr5; /* External IRQ Destination 5 */ 737 u8 res58[12]; 738 u32 eivpr6; /* External IRQ Vector/Priority 6 */ 739 u8 res59[12]; 740 u32 eidr6; /* External IRQ Destination 6 */ 741 u8 res60[12]; 742 u32 eivpr7; /* External IRQ Vector/Priority 7 */ 743 u8 res61[12]; 744 u32 eidr7; /* External IRQ Destination 7 */ 745 u8 res62[12]; 746 u32 eivpr8; /* External IRQ Vector/Priority 8 */ 747 u8 res63[12]; 748 u32 eidr8; /* External IRQ Destination 8 */ 749 u8 res64[12]; 750 u32 eivpr9; /* External IRQ Vector/Priority 9 */ 751 u8 res65[12]; 752 u32 eidr9; /* External IRQ Destination 9 */ 753 u8 res66[12]; 754 u32 eivpr10; /* External IRQ Vector/Priority 10 */ 755 u8 res67[12]; 756 u32 eidr10; /* External IRQ Destination 10 */ 757 u8 res68[12]; 758 u32 eivpr11; /* External IRQ Vector/Priority 11 */ 759 u8 res69[12]; 760 u32 eidr11; /* External IRQ Destination 11 */ 761 u8 res70[140]; 762 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ 763 u8 res71[12]; 764 u32 iidr0; /* Internal IRQ Destination 0 */ 765 u8 res72[12]; 766 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ 767 u8 res73[12]; 768 u32 iidr1; /* Internal IRQ Destination 1 */ 769 u8 res74[12]; 770 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ 771 u8 res75[12]; 772 u32 iidr2; /* Internal IRQ Destination 2 */ 773 u8 res76[12]; 774 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ 775 u8 res77[12]; 776 u32 iidr3; /* Internal IRQ Destination 3 */ 777 u8 res78[12]; 778 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ 779 u8 res79[12]; 780 u32 iidr4; /* Internal IRQ Destination 4 */ 781 u8 res80[12]; 782 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ 783 u8 res81[12]; 784 u32 iidr5; /* Internal IRQ Destination 5 */ 785 u8 res82[12]; 786 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ 787 u8 res83[12]; 788 u32 iidr6; /* Internal IRQ Destination 6 */ 789 u8 res84[12]; 790 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ 791 u8 res85[12]; 792 u32 iidr7; /* Internal IRQ Destination 7 */ 793 u8 res86[12]; 794 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ 795 u8 res87[12]; 796 u32 iidr8; /* Internal IRQ Destination 8 */ 797 u8 res88[12]; 798 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ 799 u8 res89[12]; 800 u32 iidr9; /* Internal IRQ Destination 9 */ 801 u8 res90[12]; 802 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ 803 u8 res91[12]; 804 u32 iidr10; /* Internal IRQ Destination 10 */ 805 u8 res92[12]; 806 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ 807 u8 res93[12]; 808 u32 iidr11; /* Internal IRQ Destination 11 */ 809 u8 res94[12]; 810 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ 811 u8 res95[12]; 812 u32 iidr12; /* Internal IRQ Destination 12 */ 813 u8 res96[12]; 814 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ 815 u8 res97[12]; 816 u32 iidr13; /* Internal IRQ Destination 13 */ 817 u8 res98[12]; 818 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ 819 u8 res99[12]; 820 u32 iidr14; /* Internal IRQ Destination 14 */ 821 u8 res100[12]; 822 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ 823 u8 res101[12]; 824 u32 iidr15; /* Internal IRQ Destination 15 */ 825 u8 res102[12]; 826 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ 827 u8 res103[12]; 828 u32 iidr16; /* Internal IRQ Destination 16 */ 829 u8 res104[12]; 830 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ 831 u8 res105[12]; 832 u32 iidr17; /* Internal IRQ Destination 17 */ 833 u8 res106[12]; 834 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ 835 u8 res107[12]; 836 u32 iidr18; /* Internal IRQ Destination 18 */ 837 u8 res108[12]; 838 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ 839 u8 res109[12]; 840 u32 iidr19; /* Internal IRQ Destination 19 */ 841 u8 res110[12]; 842 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ 843 u8 res111[12]; 844 u32 iidr20; /* Internal IRQ Destination 20 */ 845 u8 res112[12]; 846 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ 847 u8 res113[12]; 848 u32 iidr21; /* Internal IRQ Destination 21 */ 849 u8 res114[12]; 850 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ 851 u8 res115[12]; 852 u32 iidr22; /* Internal IRQ Destination 22 */ 853 u8 res116[12]; 854 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ 855 u8 res117[12]; 856 u32 iidr23; /* Internal IRQ Destination 23 */ 857 u8 res118[12]; 858 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ 859 u8 res119[12]; 860 u32 iidr24; /* Internal IRQ Destination 24 */ 861 u8 res120[12]; 862 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ 863 u8 res121[12]; 864 u32 iidr25; /* Internal IRQ Destination 25 */ 865 u8 res122[12]; 866 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ 867 u8 res123[12]; 868 u32 iidr26; /* Internal IRQ Destination 26 */ 869 u8 res124[12]; 870 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ 871 u8 res125[12]; 872 u32 iidr27; /* Internal IRQ Destination 27 */ 873 u8 res126[12]; 874 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ 875 u8 res127[12]; 876 u32 iidr28; /* Internal IRQ Destination 28 */ 877 u8 res128[12]; 878 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ 879 u8 res129[12]; 880 u32 iidr29; /* Internal IRQ Destination 29 */ 881 u8 res130[12]; 882 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ 883 u8 res131[12]; 884 u32 iidr30; /* Internal IRQ Destination 30 */ 885 u8 res132[12]; 886 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ 887 u8 res133[12]; 888 u32 iidr31; /* Internal IRQ Destination 31 */ 889 u8 res134[4108]; 890 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ 891 u8 res135[12]; 892 u32 midr0; /* Messaging IRQ Destination 0 */ 893 u8 res136[12]; 894 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ 895 u8 res137[12]; 896 u32 midr1; /* Messaging IRQ Destination 1 */ 897 u8 res138[12]; 898 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ 899 u8 res139[12]; 900 u32 midr2; /* Messaging IRQ Destination 2 */ 901 u8 res140[12]; 902 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ 903 u8 res141[12]; 904 u32 midr3; /* Messaging IRQ Destination 3 */ 905 u8 res142[59852]; 906 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ 907 u8 res143[12]; 908 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ 909 u8 res144[12]; 910 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ 911 u8 res145[12]; 912 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ 913 u8 res146[12]; 914 u32 ctpr0; /* Current Task Priority for Processor 0 */ 915 u8 res147[12]; 916 u32 whoami0; /* Who Am I for Processor 0 */ 917 u8 res148[12]; 918 u32 iack0; /* IRQ Acknowledge for Processor 0 */ 919 u8 res149[12]; 920 u32 eoi0; /* End Of IRQ for Processor 0 */ 921 u8 res150[130892]; 922 } ccsr_pic_t; 923 924 /* CPM Block */ 925 #ifndef CONFIG_CPM2 926 typedef struct ccsr_cpm { 927 u8 res[262144]; 928 } ccsr_cpm_t; 929 #else 930 /* 931 * DPARM 932 * General SIU 933 */ 934 typedef struct ccsr_cpm_siu { 935 u8 res1[80]; 936 u32 smaer; 937 u32 smser; 938 u32 smevr; 939 u8 res2[4]; 940 u32 lmaer; 941 u32 lmser; 942 u32 lmevr; 943 u8 res3[2964]; 944 } ccsr_cpm_siu_t; 945 946 /* IRQ Controller */ 947 typedef struct ccsr_cpm_intctl { 948 u16 sicr; 949 u8 res1[2]; 950 u32 sivec; 951 u32 sipnrh; 952 u32 sipnrl; 953 u32 siprr; 954 u32 scprrh; 955 u32 scprrl; 956 u32 simrh; 957 u32 simrl; 958 u32 siexr; 959 u8 res2[88]; 960 u32 sccr; 961 u8 res3[124]; 962 } ccsr_cpm_intctl_t; 963 964 /* input/output port */ 965 typedef struct ccsr_cpm_iop { 966 u32 pdira; 967 u32 ppara; 968 u32 psora; 969 u32 podra; 970 u32 pdata; 971 u8 res1[12]; 972 u32 pdirb; 973 u32 pparb; 974 u32 psorb; 975 u32 podrb; 976 u32 pdatb; 977 u8 res2[12]; 978 u32 pdirc; 979 u32 pparc; 980 u32 psorc; 981 u32 podrc; 982 u32 pdatc; 983 u8 res3[12]; 984 u32 pdird; 985 u32 ppard; 986 u32 psord; 987 u32 podrd; 988 u32 pdatd; 989 u8 res4[12]; 990 } ccsr_cpm_iop_t; 991 992 /* CPM timers */ 993 typedef struct ccsr_cpm_timer { 994 u8 tgcr1; 995 u8 res1[3]; 996 u8 tgcr2; 997 u8 res2[11]; 998 u16 tmr1; 999 u16 tmr2; 1000 u16 trr1; 1001 u16 trr2; 1002 u16 tcr1; 1003 u16 tcr2; 1004 u16 tcn1; 1005 u16 tcn2; 1006 u16 tmr3; 1007 u16 tmr4; 1008 u16 trr3; 1009 u16 trr4; 1010 u16 tcr3; 1011 u16 tcr4; 1012 u16 tcn3; 1013 u16 tcn4; 1014 u16 ter1; 1015 u16 ter2; 1016 u16 ter3; 1017 u16 ter4; 1018 u8 res3[608]; 1019 } ccsr_cpm_timer_t; 1020 1021 /* SDMA */ 1022 typedef struct ccsr_cpm_sdma { 1023 u8 sdsr; 1024 u8 res1[3]; 1025 u8 sdmr; 1026 u8 res2[739]; 1027 } ccsr_cpm_sdma_t; 1028 1029 /* FCC1 */ 1030 typedef struct ccsr_cpm_fcc1 { 1031 u32 gfmr; 1032 u32 fpsmr; 1033 u16 ftodr; 1034 u8 res1[2]; 1035 u16 fdsr; 1036 u8 res2[2]; 1037 u16 fcce; 1038 u8 res3[2]; 1039 u16 fccm; 1040 u8 res4[2]; 1041 u8 fccs; 1042 u8 res5[3]; 1043 u8 ftirr_phy[4]; 1044 } ccsr_cpm_fcc1_t; 1045 1046 /* FCC2 */ 1047 typedef struct ccsr_cpm_fcc2 { 1048 u32 gfmr; 1049 u32 fpsmr; 1050 u16 ftodr; 1051 u8 res1[2]; 1052 u16 fdsr; 1053 u8 res2[2]; 1054 u16 fcce; 1055 u8 res3[2]; 1056 u16 fccm; 1057 u8 res4[2]; 1058 u8 fccs; 1059 u8 res5[3]; 1060 u8 ftirr_phy[4]; 1061 } ccsr_cpm_fcc2_t; 1062 1063 /* FCC3 */ 1064 typedef struct ccsr_cpm_fcc3 { 1065 u32 gfmr; 1066 u32 fpsmr; 1067 u16 ftodr; 1068 u8 res1[2]; 1069 u16 fdsr; 1070 u8 res2[2]; 1071 u16 fcce; 1072 u8 res3[2]; 1073 u16 fccm; 1074 u8 res4[2]; 1075 u8 fccs; 1076 u8 res5[3]; 1077 u8 res[36]; 1078 } ccsr_cpm_fcc3_t; 1079 1080 /* FCC1 extended */ 1081 typedef struct ccsr_cpm_fcc1_ext { 1082 u32 firper; 1083 u32 firer; 1084 u32 firsr_h; 1085 u32 firsr_l; 1086 u8 gfemr; 1087 u8 res[15]; 1088 1089 } ccsr_cpm_fcc1_ext_t; 1090 1091 /* FCC2 extended */ 1092 typedef struct ccsr_cpm_fcc2_ext { 1093 u32 firper; 1094 u32 firer; 1095 u32 firsr_h; 1096 u32 firsr_l; 1097 u8 gfemr; 1098 u8 res[31]; 1099 } ccsr_cpm_fcc2_ext_t; 1100 1101 /* FCC3 extended */ 1102 typedef struct ccsr_cpm_fcc3_ext { 1103 u8 gfemr; 1104 u8 res[47]; 1105 } ccsr_cpm_fcc3_ext_t; 1106 1107 /* TC layers */ 1108 typedef struct ccsr_cpm_tmp1 { 1109 u8 res[496]; 1110 } ccsr_cpm_tmp1_t; 1111 1112 /* BRGs:5,6,7,8 */ 1113 typedef struct ccsr_cpm_brg2 { 1114 u32 brgc5; 1115 u32 brgc6; 1116 u32 brgc7; 1117 u32 brgc8; 1118 u8 res[608]; 1119 } ccsr_cpm_brg2_t; 1120 1121 /* I2C */ 1122 typedef struct ccsr_cpm_i2c { 1123 u8 i2mod; 1124 u8 res1[3]; 1125 u8 i2add; 1126 u8 res2[3]; 1127 u8 i2brg; 1128 u8 res3[3]; 1129 u8 i2com; 1130 u8 res4[3]; 1131 u8 i2cer; 1132 u8 res5[3]; 1133 u8 i2cmr; 1134 u8 res6[331]; 1135 } ccsr_cpm_i2c_t; 1136 1137 /* CPM core */ 1138 typedef struct ccsr_cpm_cp { 1139 u32 cpcr; 1140 u32 rccr; 1141 u8 res1[14]; 1142 u16 rter; 1143 u8 res2[2]; 1144 u16 rtmr; 1145 u16 rtscr; 1146 u8 res3[2]; 1147 u32 rtsr; 1148 u8 res4[12]; 1149 } ccsr_cpm_cp_t; 1150 1151 /* BRGs:1,2,3,4 */ 1152 typedef struct ccsr_cpm_brg1 { 1153 u32 brgc1; 1154 u32 brgc2; 1155 u32 brgc3; 1156 u32 brgc4; 1157 } ccsr_cpm_brg1_t; 1158 1159 /* SCC1-SCC4 */ 1160 typedef struct ccsr_cpm_scc { 1161 u32 gsmrl; 1162 u32 gsmrh; 1163 u16 psmr; 1164 u8 res1[2]; 1165 u16 todr; 1166 u16 dsr; 1167 u16 scce; 1168 u8 res2[2]; 1169 u16 sccm; 1170 u8 res3; 1171 u8 sccs; 1172 u8 res4[8]; 1173 } ccsr_cpm_scc_t; 1174 1175 typedef struct ccsr_cpm_tmp2 { 1176 u8 res[32]; 1177 } ccsr_cpm_tmp2_t; 1178 1179 /* SPI */ 1180 typedef struct ccsr_cpm_spi { 1181 u16 spmode; 1182 u8 res1[4]; 1183 u8 spie; 1184 u8 res2[3]; 1185 u8 spim; 1186 u8 res3[2]; 1187 u8 spcom; 1188 u8 res4[82]; 1189 } ccsr_cpm_spi_t; 1190 1191 /* CPM MUX */ 1192 typedef struct ccsr_cpm_mux { 1193 u8 cmxsi1cr; 1194 u8 res1; 1195 u8 cmxsi2cr; 1196 u8 res2; 1197 u32 cmxfcr; 1198 u32 cmxscr; 1199 u8 res3[2]; 1200 u16 cmxuar; 1201 u8 res4[16]; 1202 } ccsr_cpm_mux_t; 1203 1204 /* SI,MCC,etc */ 1205 typedef struct ccsr_cpm_tmp3 { 1206 u8 res[58592]; 1207 } ccsr_cpm_tmp3_t; 1208 1209 typedef struct ccsr_cpm_iram { 1210 u32 iram[8192]; 1211 u8 res[98304]; 1212 } ccsr_cpm_iram_t; 1213 1214 typedef struct ccsr_cpm { 1215 /* Some references are into the unique & known dpram spaces, 1216 * others are from the generic base. 1217 */ 1218 #define im_dprambase im_dpram1 1219 u8 im_dpram1[16*1024]; 1220 u8 res1[16*1024]; 1221 u8 im_dpram2[16*1024]; 1222 u8 res2[16*1024]; 1223 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ 1224 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ 1225 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ 1226 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ 1227 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ 1228 ccsr_cpm_fcc1_t im_cpm_fcc1; 1229 ccsr_cpm_fcc2_t im_cpm_fcc2; 1230 ccsr_cpm_fcc3_t im_cpm_fcc3; 1231 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; 1232 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; 1233 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; 1234 ccsr_cpm_tmp1_t im_cpm_tmp1; 1235 ccsr_cpm_brg2_t im_cpm_brg2; 1236 ccsr_cpm_i2c_t im_cpm_i2c; 1237 ccsr_cpm_cp_t im_cpm_cp; 1238 ccsr_cpm_brg1_t im_cpm_brg1; 1239 ccsr_cpm_scc_t im_cpm_scc[4]; 1240 ccsr_cpm_tmp2_t im_cpm_tmp2; 1241 ccsr_cpm_spi_t im_cpm_spi; 1242 ccsr_cpm_mux_t im_cpm_mux; 1243 ccsr_cpm_tmp3_t im_cpm_tmp3; 1244 ccsr_cpm_iram_t im_cpm_iram; 1245 } ccsr_cpm_t; 1246 #endif 1247 1248 #ifdef CONFIG_SYS_SRIO 1249 /* Architectural regsiters */ 1250 struct rio_arch { 1251 u32 didcar; /* Device Identity CAR */ 1252 u32 dicar; /* Device Information CAR */ 1253 u32 aidcar; /* Assembly Identity CAR */ 1254 u32 aicar; /* Assembly Information CAR */ 1255 u32 pefcar; /* Processing Element Features CAR */ 1256 u8 res0[4]; 1257 u32 socar; /* Source Operations CAR */ 1258 u32 docar; /* Destination Operations CAR */ 1259 u8 res1[32]; 1260 u32 mcsr; /* Mailbox CSR */ 1261 u32 pwdcsr; /* Port-Write and Doorbell CSR */ 1262 u8 res2[4]; 1263 u32 pellccsr; /* Processing Element Logic Layer CCSR */ 1264 u8 res3[12]; 1265 u32 lcsbacsr; /* Local Configuration Space BACSR */ 1266 u32 bdidcsr; /* Base Device ID CSR */ 1267 u8 res4[4]; 1268 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ 1269 u32 ctcsr; /* Component Tag CSR */ 1270 }; 1271 1272 /* Extended Features Space: 1x/4x LP-Serial Port registers */ 1273 struct rio_lp_serial_port { 1274 u32 plmreqcsr; /* Port Link Maintenance Request CSR */ 1275 u32 plmrespcsr; /* Port Link Maintenance Response CS */ 1276 u32 plascsr; /* Port Local Ackid Status CSR */ 1277 u8 res0[12]; 1278 u32 pescsr; /* Port Error and Status CSR */ 1279 u32 pccsr; /* Port Control CSR */ 1280 }; 1281 1282 /* Extended Features Space: 1x/4x LP-Serial registers */ 1283 struct rio_lp_serial { 1284 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ 1285 u8 res0[28]; 1286 u32 pltoccsr; /* Port Link Time-out CCSR */ 1287 u32 prtoccsr; /* Port Response Time-out CCSR */ 1288 u8 res1[20]; 1289 u32 pgccsr; /* Port General CSR */ 1290 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1291 }; 1292 1293 /* Logical error reporting registers */ 1294 struct rio_logical_err { 1295 u32 erbh; /* Error Reporting Block Header Register */ 1296 u8 res0[4]; 1297 u32 ltledcsr; /* Logical/Transport layer error DCSR */ 1298 u32 ltleecsr; /* Logical/Transport layer error ECSR */ 1299 u8 res1[4]; 1300 u32 ltlaccsr; /* Logical/Transport layer ACCSR */ 1301 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ 1302 u32 ltlcccsr; /* Logical/Transport layer control CCSR */ 1303 }; 1304 1305 /* Physical error reporting port registers */ 1306 struct rio_phys_err_port { 1307 u32 edcsr; /* Port error detect CSR */ 1308 u32 erecsr; /* Port error rate enable CSR */ 1309 u32 ecacsr; /* Port error capture attributes CSR */ 1310 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ 1311 u32 peccsr[3]; /* Port error capture CSR */ 1312 u8 res0[12]; 1313 u32 ercsr; /* Port error rate CSR */ 1314 u32 ertcsr; /* Port error rate threshold CSR */ 1315 u8 res1[16]; 1316 }; 1317 1318 /* Physical error reporting registers */ 1319 struct rio_phys_err { 1320 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1321 }; 1322 1323 /* Implementation Space: General Port-Common */ 1324 struct rio_impl_common { 1325 u8 res0[4]; 1326 u32 llcr; /* Logical Layer Configuration Register */ 1327 u8 res1[8]; 1328 u32 epwisr; /* Error / Port-Write Interrupt SR */ 1329 u8 res2[12]; 1330 u32 lretcr; /* Logical Retry Error Threshold CR */ 1331 u8 res3[92]; 1332 u32 pretcr; /* Physical Retry Erorr Threshold CR */ 1333 u8 res4[124]; 1334 }; 1335 1336 /* Implementation Space: Port Specific */ 1337 struct rio_impl_port_spec { 1338 u32 adidcsr; /* Port Alt. Device ID CSR */ 1339 u8 res0[28]; 1340 u32 ptaacr; /* Port Pass-Through/Accept-All CR */ 1341 u32 lopttlcr; 1342 u8 res1[8]; 1343 u32 iecsr; /* Port Implementation Error CSR */ 1344 u8 res2[12]; 1345 u32 pcr; /* Port Phsyical Configuration Register */ 1346 u8 res3[20]; 1347 u32 slcsr; /* Port Serial Link CSR */ 1348 u8 res4[4]; 1349 u32 sleicr; /* Port Serial Link Error Injection */ 1350 u32 a0txcr; /* Port Arbitration 0 Tx CR */ 1351 u32 a1txcr; /* Port Arbitration 1 Tx CR */ 1352 u32 a2txcr; /* Port Arbitration 2 Tx CR */ 1353 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ 1354 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ 1355 }; 1356 1357 /* Implementation Space: register */ 1358 struct rio_implement { 1359 struct rio_impl_common com; 1360 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1361 }; 1362 1363 /* Revision Control Register */ 1364 struct rio_rev_ctrl { 1365 u32 ipbrr[2]; /* IP Block Revision Register */ 1366 }; 1367 1368 struct rio_atmu_row { 1369 u32 rowtar; /* RapidIO Outbound Window TAR */ 1370 u32 rowtear; /* RapidIO Outbound Window TEAR */ 1371 u32 rowbar; 1372 u8 res0[4]; 1373 u32 rowar; /* RapidIO Outbound Attributes Register */ 1374 u32 rowsr[3]; /* Port RapidIO outbound window segment register */ 1375 }; 1376 1377 struct rio_atmu_riw { 1378 u32 riwtar; /* RapidIO Inbound Window Translation AR */ 1379 u8 res0[4]; 1380 u32 riwbar; /* RapidIO Inbound Window Base AR */ 1381 u8 res1[4]; 1382 u32 riwar; /* RapidIO Inbound Attributes Register */ 1383 u8 res2[12]; 1384 }; 1385 1386 /* ATMU window registers */ 1387 struct rio_atmu_win { 1388 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; 1389 u8 res0[64]; 1390 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; 1391 }; 1392 1393 struct rio_atmu { 1394 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1395 }; 1396 1397 #ifdef CONFIG_SYS_FSL_RMU 1398 struct rio_msg { 1399 u32 omr; /* Outbound Mode Register */ 1400 u32 osr; /* Outbound Status Register */ 1401 u32 eodqdpar; /* Extended Outbound DQ DPAR */ 1402 u32 odqdpar; /* Outbound Descriptor Queue DPAR */ 1403 u32 eosar; /* Extended Outbound Unit Source AR */ 1404 u32 osar; /* Outbound Unit Source AR */ 1405 u32 odpr; /* Outbound Destination Port Register */ 1406 u32 odatr; /* Outbound Destination Attributes Register */ 1407 u32 odcr; /* Outbound Doubleword Count Register */ 1408 u32 eodqepar; /* Extended Outbound DQ EPAR */ 1409 u32 odqepar; /* Outbound Descriptor Queue EPAR */ 1410 u32 oretr; /* Outbound Retry Error Threshold Register */ 1411 u32 omgr; /* Outbound Multicast Group Register */ 1412 u32 omlr; /* Outbound Multicast List Register */ 1413 u8 res0[40]; 1414 u32 imr; /* Outbound Mode Register */ 1415 u32 isr; /* Inbound Status Register */ 1416 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ 1417 u32 idqdpar; /* Inbound Descriptor Queue DPAR */ 1418 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ 1419 u32 ifqepar; /* Inbound Frame Queue EPAR */ 1420 u32 imirir; /* Inbound Maximum Interrutp RIR */ 1421 u8 res1[4]; 1422 u32 eihqepar; /* Extended inbound message header queue EPAR */ 1423 u32 ihqepar; /* Inbound message header queue EPAR */ 1424 u8 res2[120]; 1425 }; 1426 1427 struct rio_dbell { 1428 u32 odmr; /* Outbound Doorbell Mode Register */ 1429 u32 odsr; /* Outbound Doorbell Status Register */ 1430 u8 res0[16]; 1431 u32 oddpr; /* Outbound Doorbell Destination Port */ 1432 u32 oddatr; /* Outbound Doorbell Destination AR */ 1433 u8 res1[12]; 1434 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ 1435 u8 res2[48]; 1436 u32 idmr; /* Inbound Doorbell Mode Register */ 1437 u32 idsr; /* Inbound Doorbell Status Register */ 1438 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ 1439 u32 iqdpar; /* Inbound Doorbell Queue DPAR */ 1440 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ 1441 u32 idqepar; /* Inbound Doorbell Queue EPAR */ 1442 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ 1443 }; 1444 1445 struct rio_pw { 1446 u32 pwmr; /* Port-Write Mode Register */ 1447 u32 pwsr; /* Port-Write Status Register */ 1448 u32 epwqbar; /* Extended Port-Write Queue BAR */ 1449 u32 pwqbar; /* Port-Write Queue Base Address Register */ 1450 }; 1451 #endif 1452 1453 #ifdef CONFIG_SYS_FSL_SRIO_LIODN 1454 struct rio_liodn { 1455 u32 plbr; 1456 u8 res0[28]; 1457 u32 plaor; 1458 u8 res1[12]; 1459 u32 pludr; 1460 u32 plldr; 1461 u8 res2[456]; 1462 }; 1463 #endif 1464 1465 /* RapidIO Registers */ 1466 struct ccsr_rio { 1467 struct rio_arch arch; 1468 u8 res0[144]; 1469 struct rio_lp_serial lp_serial; 1470 u8 res1[1152]; 1471 struct rio_logical_err logical_err; 1472 u8 res2[32]; 1473 struct rio_phys_err phys_err; 1474 u8 res3[63808]; 1475 struct rio_implement impl; 1476 u8 res4[2552]; 1477 struct rio_rev_ctrl rev; 1478 struct rio_atmu atmu; 1479 #ifdef CONFIG_SYS_FSL_RMU 1480 u8 res5[8192]; 1481 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; 1482 u8 res6[512]; 1483 struct rio_dbell dbell; 1484 u8 res7[100]; 1485 struct rio_pw pw; 1486 #endif 1487 #ifdef CONFIG_SYS_FSL_SRIO_LIODN 1488 u8 res5[8192]; 1489 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1490 #endif 1491 }; 1492 #endif 1493 1494 /* Quick Engine Block Pin Muxing Registers */ 1495 typedef struct par_io { 1496 u32 cpodr; 1497 u32 cpdat; 1498 u32 cpdir1; 1499 u32 cpdir2; 1500 u32 cppar1; 1501 u32 cppar2; 1502 u8 res[8]; 1503 } par_io_t; 1504 1505 #ifdef CONFIG_SYS_FSL_CPC 1506 /* 1507 * Define a single offset that is the start of all the CPC register 1508 * blocks - if there is more than one CPC, we expect these to be 1509 * contiguous 4k regions 1510 */ 1511 1512 typedef struct cpc_corenet { 1513 u32 cpccsr0; /* Config/status reg */ 1514 u32 res1; 1515 u32 cpccfg0; /* Configuration register */ 1516 u32 res2; 1517 u32 cpcewcr0; /* External Write reg 0 */ 1518 u32 cpcewabr0; /* External write base reg 0 */ 1519 u32 res3[2]; 1520 u32 cpcewcr1; /* External Write reg 1 */ 1521 u32 cpcewabr1; /* External write base reg 1 */ 1522 u32 res4[54]; 1523 u32 cpcsrcr1; /* SRAM control reg 1 */ 1524 u32 cpcsrcr0; /* SRAM control reg 0 */ 1525 u32 res5[62]; 1526 struct { 1527 u32 id; /* partition ID */ 1528 u32 res; 1529 u32 alloc; /* partition allocation */ 1530 u32 way; /* partition way */ 1531 } partition_regs[16]; 1532 u32 res6[704]; 1533 u32 cpcerrinjhi; /* Error injection high */ 1534 u32 cpcerrinjlo; /* Error injection lo */ 1535 u32 cpcerrinjctl; /* Error injection control */ 1536 u32 res7[5]; 1537 u32 cpccaptdatahi; /* capture data high */ 1538 u32 cpccaptdatalo; /* capture data low */ 1539 u32 cpcaptecc; /* capture ECC */ 1540 u32 res8[5]; 1541 u32 cpcerrdet; /* error detect */ 1542 u32 cpcerrdis; /* error disable */ 1543 u32 cpcerrinten; /* errir interrupt enable */ 1544 u32 cpcerrattr; /* error attribute */ 1545 u32 cpcerreaddr; /* error extended address */ 1546 u32 cpcerraddr; /* error address */ 1547 u32 cpcerrctl; /* error control */ 1548 u32 res9[41]; /* pad out to 4k */ 1549 u32 cpchdbcr0; /* hardware debug control register 0 */ 1550 u32 res10[63]; /* pad out to 4k */ 1551 } cpc_corenet_t; 1552 1553 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ 1554 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */ 1555 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ 1556 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */ 1557 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ 1558 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ 1559 #define CPC_CFG0_SZ_MASK 0x00003fff 1560 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) 1561 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) 1562 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) 1563 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff 1564 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ 1565 & CPC_SRCR1_SRBARU_MASK) 1566 #define CPC_SRCR0_SRBARL_MASK 0xffff8000 1567 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) 1568 #define CPC_SRCR0_INTLVEN 0x00000100 1569 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 1570 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 1571 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 1572 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 1573 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 1574 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a 1575 #define CPC_SRCR0_SRAMEN 0x00000001 1576 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ 1577 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 1578 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 1579 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 1580 #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 1581 #endif /* CONFIG_SYS_FSL_CPC */ 1582 1583 /* Global Utilities Block */ 1584 #ifdef CONFIG_FSL_CORENET 1585 typedef struct ccsr_gur { 1586 u32 porsr1; /* POR status 1 */ 1587 u32 porsr2; /* POR status 2 */ 1588 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 1589 #define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15 1590 #define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1 1591 #define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1 1592 #define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0 1593 #endif 1594 u8 res_008[0x20-0x8]; 1595 u32 gpporcr1; /* General-purpose POR configuration */ 1596 u32 gpporcr2; /* General-purpose POR configuration 2 */ 1597 u32 dcfg_fusesr; /* Fuse status register */ 1598 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25 1599 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F 1600 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20 1601 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F 1602 u8 res_02c[0x70-0x2c]; 1603 u32 devdisr; /* Device disable control */ 1604 u32 devdisr2; /* Device disable control 2 */ 1605 u32 devdisr3; /* Device disable control 3 */ 1606 u32 devdisr4; /* Device disable control 4 */ 1607 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1608 u32 devdisr5; /* Device disable control 5 */ 1609 #define FSL_CORENET_DEVDISR_PBL 0x80000000 1610 #define FSL_CORENET_DEVDISR_PMAN 0x40000000 1611 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000 1612 #define FSL_CORENET_DEVDISR_DMA1 0x00800000 1613 #define FSL_CORENET_DEVDISR_DMA2 0x00400000 1614 #define FSL_CORENET_DEVDISR_USB1 0x00080000 1615 #define FSL_CORENET_DEVDISR_USB2 0x00040000 1616 #define FSL_CORENET_DEVDISR_SATA1 0x00008000 1617 #define FSL_CORENET_DEVDISR_SATA2 0x00004000 1618 #define FSL_CORENET_DEVDISR_PME 0x00000800 1619 #define FSL_CORENET_DEVDISR_SEC 0x00000200 1620 #define FSL_CORENET_DEVDISR_RMU 0x00000080 1621 #define FSL_CORENET_DEVDISR_DCE 0x00000040 1622 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000 1623 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000 1624 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000 1625 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000 1626 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000 1627 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 1628 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 1629 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 1630 #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 1631 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000 1632 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000 1633 #else 1634 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 1635 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 1636 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 1637 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 1638 #endif 1639 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 1640 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 1641 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 1642 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000 1643 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000 1644 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000 1645 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800 1646 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400 1647 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800 1648 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400 1649 #define FSL_CORENET_DEVDISR2_FM1 0x00000080 1650 #define FSL_CORENET_DEVDISR2_FM2 0x00000040 1651 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008 1652 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000 1653 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000 1654 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000 1655 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000 1656 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000 1657 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000 1658 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000 1659 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000 1660 #define FSL_CORENET_DEVDISR3_LA1 0x00008000 1661 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800 1662 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400 1663 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200 1664 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000 1665 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000 1666 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000 1667 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000 1668 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000 1669 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000 1670 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000 1671 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000 1672 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000 1673 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000 1674 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000 1675 #define FSL_CORENET_DEVDISR5_IFC 0x00800000 1676 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000 1677 #define FSL_CORENET_DEVDISR5_DBG 0x00200000 1678 #define FSL_CORENET_DEVDISR5_NAL 0x00100000 1679 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000 1680 #define FSL_CORENET_NUM_DEVDISR 5 1681 #else 1682 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 1683 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 1684 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 1685 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000 1686 #define FSL_CORENET_DEVDISR_RMU 0x08000000 1687 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000 1688 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000 1689 #define FSL_CORENET_DEVDISR_DMA1 0x00400000 1690 #define FSL_CORENET_DEVDISR_DMA2 0x00200000 1691 #define FSL_CORENET_DEVDISR_DDR1 0x00100000 1692 #define FSL_CORENET_DEVDISR_DDR2 0x00080000 1693 #define FSL_CORENET_DEVDISR_DBG 0x00010000 1694 #define FSL_CORENET_DEVDISR_NAL 0x00008000 1695 #define FSL_CORENET_DEVDISR_SATA1 0x00004000 1696 #define FSL_CORENET_DEVDISR_SATA2 0x00002000 1697 #define FSL_CORENET_DEVDISR_ELBC 0x00001000 1698 #define FSL_CORENET_DEVDISR_USB1 0x00000800 1699 #define FSL_CORENET_DEVDISR_USB2 0x00000400 1700 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100 1701 #define FSL_CORENET_DEVDISR_GPIO 0x00000080 1702 #define FSL_CORENET_DEVDISR_ESPI 0x00000040 1703 #define FSL_CORENET_DEVDISR_I2C1 0x00000020 1704 #define FSL_CORENET_DEVDISR_I2C2 0x00000010 1705 #define FSL_CORENET_DEVDISR_DUART1 0x00000002 1706 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 1707 #define FSL_CORENET_DEVDISR2_PME 0x80000000 1708 #define FSL_CORENET_DEVDISR2_SEC 0x40000000 1709 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000 1710 #define FSL_CORENET_DEVDISR2_FM1 0x02000000 1711 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000 1712 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000 1713 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 1714 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 1715 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 1716 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000 1717 #define FSL_CORENET_DEVDISR2_FM2 0x00020000 1718 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 1719 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 1720 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 1721 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 1722 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 1723 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800 1724 #define FSL_CORENET_NUM_DEVDISR 2 1725 u32 powmgtcsr; /* Power management status & control */ 1726 #endif 1727 u8 res8[12]; 1728 u32 coredisru; /* uppper portion for support of 64 cores */ 1729 u32 coredisrl; /* lower portion for support of 64 cores */ 1730 u8 res9[8]; 1731 u32 pvr; /* Processor version */ 1732 u32 svr; /* System version */ 1733 u8 res10[8]; 1734 u32 rstcr; /* Reset control */ 1735 u32 rstrqpblsr; /* Reset request preboot loader status */ 1736 u8 res11[8]; 1737 u32 rstrqmr1; /* Reset request mask */ 1738 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1739 #define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800 1740 #endif 1741 u8 res12[4]; 1742 u32 rstrqsr1; /* Reset request status */ 1743 u8 res13[4]; 1744 u8 res14[4]; 1745 u32 rstrqwdtmrl; /* Reset request WDT mask */ 1746 u8 res15[4]; 1747 u32 rstrqwdtsrl; /* Reset request WDT status */ 1748 u8 res16[4]; 1749 u32 brrl; /* Boot release */ 1750 u8 res17[24]; 1751 u32 rcwsr[16]; /* Reset control word status */ 1752 1753 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1754 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 1755 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ 1756 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 1757 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f 1758 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 1759 defined(CONFIG_PPC_T4080) 1760 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 1761 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 1762 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 1763 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 1764 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800 1765 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 1766 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 1767 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 1768 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1769 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 1770 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 1771 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 1772 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 1773 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 1774 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1775 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 1776 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 1777 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 1778 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 1779 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 1780 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 1781 #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ 1782 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000 1783 #define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000 1784 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 1785 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ 1786 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 1787 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 1788 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 1789 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 1790 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 1791 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 1792 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 1793 #define PXCKEN_MASK 0x80000000 1794 #define PXCK_MASK 0x00FF0000 1795 #define PXCK_BITS_START 16 1796 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \ 1797 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 1798 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 1799 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 1800 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1801 #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ 1802 #define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000 1803 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000 1804 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 1805 #define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000 1806 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 1807 #define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00 1808 #define PXCKEN_MASK 0x80000000 1809 #define PXCK_MASK 0x00FF0000 1810 #define PXCK_BITS_START 16 1811 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 1812 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 1813 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 1814 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 1815 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 1816 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1817 #endif 1818 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 1819 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 1820 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000 1821 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000 1822 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000 1823 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 1824 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 1825 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 1826 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 1827 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011 1828 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 1829 1830 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 1831 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 1832 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f 1833 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 1834 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 1835 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 1836 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 1837 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000 1838 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1839 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ 1840 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ 1841 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 1842 1843 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 1844 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 1845 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 1846 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ 1847 #ifdef CONFIG_PPC_P4080 1848 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 1849 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 1850 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ 1851 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 1852 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 1853 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 1854 #endif 1855 #if defined(CONFIG_PPC_P2041) \ 1856 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) 1857 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 1858 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 1859 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 1860 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 1861 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000 1862 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 1863 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 1864 #endif 1865 #if defined(CONFIG_PPC_P5040) 1866 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 1867 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 1868 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 1869 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 1870 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000 1871 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 1872 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 1873 #endif 1874 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 1875 defined(CONFIG_PPC_T4080) 1876 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 1877 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 1878 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 1879 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 1880 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 1881 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 1882 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 1883 #endif 1884 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 1885 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 1886 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 1887 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 1888 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 1889 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 1890 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000 1891 #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000 1892 #endif 1893 u8 res18[192]; 1894 u32 scratchrw[4]; /* Scratch Read/Write */ 1895 u8 res19[240]; 1896 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 1897 u8 res20[240]; 1898 u32 scrtsr[8]; /* Core reset status */ 1899 u8 res21[224]; 1900 u32 pex1liodnr; /* PCI Express 1 LIODN */ 1901 u32 pex2liodnr; /* PCI Express 2 LIODN */ 1902 u32 pex3liodnr; /* PCI Express 3 LIODN */ 1903 u32 pex4liodnr; /* PCI Express 4 LIODN */ 1904 u32 rio1liodnr; /* RIO 1 LIODN */ 1905 u32 rio2liodnr; /* RIO 2 LIODN */ 1906 u32 rio3liodnr; /* RIO 3 LIODN */ 1907 u32 rio4liodnr; /* RIO 4 LIODN */ 1908 u32 usb1liodnr; /* USB 1 LIODN */ 1909 u32 usb2liodnr; /* USB 2 LIODN */ 1910 u32 usb3liodnr; /* USB 3 LIODN */ 1911 u32 usb4liodnr; /* USB 4 LIODN */ 1912 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ 1913 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ 1914 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ 1915 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ 1916 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */ 1917 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */ 1918 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */ 1919 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */ 1920 u32 sata1liodnr; /* SATA 1 LIODN */ 1921 u32 sata2liodnr; /* SATA 2 LIODN */ 1922 u32 sata3liodnr; /* SATA 3 LIODN */ 1923 u32 sata4liodnr; /* SATA 4 LIODN */ 1924 u8 res22[20]; 1925 u32 tdmliodnr; /* TDM LIODN */ 1926 u32 qeliodnr; /* QE LIODN */ 1927 u8 res_57c[4]; 1928 u32 dma1liodnr; /* DMA 1 LIODN */ 1929 u32 dma2liodnr; /* DMA 2 LIODN */ 1930 u32 dma3liodnr; /* DMA 3 LIODN */ 1931 u32 dma4liodnr; /* DMA 4 LIODN */ 1932 u8 res23[48]; 1933 u8 res24[64]; 1934 u32 pblsr; /* Preboot loader status */ 1935 u32 pamubypenr; /* PAMU bypass enable */ 1936 #define FSL_CORENET_PAMU_BYPASS 0xffff0000 1937 u32 dmacr1; /* DMA control */ 1938 u8 res25[4]; 1939 u32 gensr1; /* General status */ 1940 u8 res26[12]; 1941 u32 gencr1; /* General control */ 1942 u8 res27[12]; 1943 u8 res28[4]; 1944 u32 cgensrl; /* Core general status */ 1945 u8 res29[8]; 1946 u8 res30[4]; 1947 u32 cgencrl; /* Core general control */ 1948 u8 res31[184]; 1949 u32 sriopstecr; /* SRIO prescaler timer enable control */ 1950 u32 dcsrcr; /* DCSR Control register */ 1951 u8 res31a[56]; 1952 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 1953 struct { 1954 u32 upper; 1955 u32 lower; 1956 } tp_cluster[16]; /* Core Cluster n Topology Register */ 1957 u8 res32[1344]; 1958 u32 pmuxcr; /* Pin multiplexing control */ 1959 u8 res33[60]; 1960 u32 iovselsr; /* I/O voltage selection status */ 1961 u8 res34[28]; 1962 u32 ddrclkdr; /* DDR clock disable */ 1963 u8 res35; 1964 u32 elbcclkdr; /* eLBC clock disable */ 1965 u8 res36[20]; 1966 u32 sdhcpcr; /* eSDHC polarity configuration */ 1967 u8 res37[380]; 1968 } ccsr_gur_t; 1969 1970 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 1971 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 1972 #define TP_ITYP_TYPE_OTHER 0x0 1973 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 1974 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */ 1975 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 1976 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 1977 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 1978 1979 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ 1980 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 1981 #define TP_INIT_PER_CLUSTER 4 1982 1983 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003 1984 #define FSL_CORENET_DCSR_SZ_4M 0x0 1985 #define FSL_CORENET_DCSR_SZ_1G 0x3 1986 1987 /* 1988 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance 1989 * everything after has RMan thus msg unit LIODN is used for maintenance 1990 */ 1991 #define rmuliodnr rio1maintliodnr 1992 1993 typedef struct ccsr_clk { 1994 struct { 1995 u32 clkcncsr; /* core cluster n clock control status */ 1996 u8 res_004[0x0c]; 1997 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ 1998 u8 res_014[0x0c]; 1999 } clkcsr[12]; 2000 u8 res_100[0x680]; /* 0x100 */ 2001 struct { 2002 u32 pllcngsr; 2003 u8 res10[0x1c]; 2004 } pllcgsr[12]; 2005 u8 res21[0x280]; 2006 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 2007 u8 res16[0x1c]; 2008 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 2009 u8 res17[0x3dc]; 2010 } ccsr_clk_t; 2011 2012 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 2013 typedef struct ccsr_rcpm { 2014 u8 res_00[12]; 2015 u32 tph10sr0; /* Thread PH10 Status Register */ 2016 u8 res_10[12]; 2017 u32 tph10setr0; /* Thread PH10 Set Control Register */ 2018 u8 res_20[12]; 2019 u32 tph10clrr0; /* Thread PH10 Clear Control Register */ 2020 u8 res_30[12]; 2021 u32 tph10psr0; /* Thread PH10 Previous Status Register */ 2022 u8 res_40[12]; 2023 u32 twaitsr0; /* Thread Wait Status Register */ 2024 u8 res_50[96]; 2025 u32 pcph15sr; /* Physical Core PH15 Status Register */ 2026 u32 pcph15setr; /* Physical Core PH15 Set Control Register */ 2027 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */ 2028 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */ 2029 u8 res_c0[16]; 2030 u32 pcph20sr; /* Physical Core PH20 Status Register */ 2031 u32 pcph20setr; /* Physical Core PH20 Set Control Register */ 2032 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */ 2033 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */ 2034 u32 pcpw20sr; /* Physical Core PW20 Status Register */ 2035 u8 res_e0[12]; 2036 u32 pcph30sr; /* Physical Core PH30 Status Register */ 2037 u32 pcph30setr; /* Physical Core PH30 Set Control Register */ 2038 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */ 2039 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */ 2040 u8 res_100[32]; 2041 u32 ippwrgatecr; /* IP Power Gating Control Register */ 2042 u8 res_124[12]; 2043 u32 powmgtcsr; /* Power Management Control & Status Reg */ 2044 u8 res_134[12]; 2045 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */ 2046 u8 res_150[12]; 2047 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */ 2048 u8 res_160[12]; 2049 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */ 2050 u8 res_170[12]; 2051 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */ 2052 u8 res_180[12]; 2053 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */ 2054 u8 res_190[12]; 2055 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */ 2056 u32 pctbenr; /* Physical Core Time Base Enable Reg */ 2057 u32 pctbclkselr; /* Physical Core Time Base Clock Select */ 2058 u32 tbclkdivr; /* Time Base Clock Divider Register */ 2059 u8 res_1ac[4]; 2060 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */ 2061 u32 clpcl10sr; /* Cluster PCL10 Status Register */ 2062 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */ 2063 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */ 2064 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */ 2065 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */ 2066 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */ 2067 u32 cdpwroksetr; /* Core Domain Power OK Set Register */ 2068 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */ 2069 u32 cdpwrensr; /* Core Domain Power Enable Status Register */ 2070 u32 cddslsr; /* Core Domain Deep Sleep Status Register */ 2071 u8 res_1e8[8]; 2072 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */ 2073 u8 res_300[3568]; 2074 } ccsr_rcpm_t; 2075 2076 #define ctbenrl pctbenr 2077 2078 #else 2079 typedef struct ccsr_rcpm { 2080 u8 res1[4]; 2081 u32 cdozsrl; /* Core Doze Status */ 2082 u8 res2[4]; 2083 u32 cdozcrl; /* Core Doze Control */ 2084 u8 res3[4]; 2085 u32 cnapsrl; /* Core Nap Status */ 2086 u8 res4[4]; 2087 u32 cnapcrl; /* Core Nap Control */ 2088 u8 res5[4]; 2089 u32 cdozpsrl; /* Core Doze Previous Status */ 2090 u8 res6[4]; 2091 u32 cdozpcrl; /* Core Doze Previous Control */ 2092 u8 res7[4]; 2093 u32 cwaitsrl; /* Core Wait Status */ 2094 u8 res8[8]; 2095 u32 powmgtcsr; /* Power Mangement Control & Status */ 2096 u8 res9[12]; 2097 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ 2098 u8 res10[12]; 2099 u8 res11[4]; 2100 u32 cpmimrl; /* Core PM IRQ Masking */ 2101 u8 res12[4]; 2102 u32 cpmcimrl; /* Core PM Critical IRQ Masking */ 2103 u8 res13[4]; 2104 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ 2105 u8 res14[4]; 2106 u32 cpmnmimrl; /* Core PM NMI Masking */ 2107 u8 res15[4]; 2108 u32 ctbenrl; /* Core Time Base Enable */ 2109 u8 res16[4]; 2110 u32 ctbclkselrl; /* Core Time Base Clock Select */ 2111 u8 res17[4]; 2112 u32 ctbhltcrl; /* Core Time Base Halt Control */ 2113 u8 res18[0xf68]; 2114 } ccsr_rcpm_t; 2115 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2116 2117 #else 2118 typedef struct ccsr_gur { 2119 u32 porpllsr; /* POR PLL ratio status */ 2120 #ifdef CONFIG_MPC8536 2121 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 2122 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 2123 #elif defined(CONFIG_PPC_C29X) 2124 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 2125 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ 2126 & MPC85xx_PORDEVSR2_DDR_SPD_0) \ 2127 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) 2128 #else 2129 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) 2130 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 2131 #else 2132 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 2133 #endif 2134 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 2135 #endif 2136 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 2137 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 2138 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e 2139 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 2140 u32 porbmsr; /* POR boot mode status */ 2141 #define MPC85xx_PORBMSR_HA 0x00070000 2142 #define MPC85xx_PORBMSR_HA_SHIFT 16 2143 #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24 2144 #define PORBMSR_ROMLOC_SPI 0x6 2145 #define PORBMSR_ROMLOC_SDHC 0x7 2146 #define PORBMSR_ROMLOC_NAND_2K 0x9 2147 #define PORBMSR_ROMLOC_NOR 0xf 2148 u32 porimpscr; /* POR I/O impedance status & control */ 2149 u32 pordevsr; /* POR I/O device status regsiter */ 2150 #if defined(CONFIG_P1017) || defined(CONFIG_P1023) 2151 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 2152 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 2153 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 2154 #else 2155 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 2156 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 2157 #endif 2158 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 2159 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 2160 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 2161 #define MPC85xx_PORDEVSR_PCI1 0x00800000 2162 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2163 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 2164 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 2165 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023) 2166 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 2167 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2168 #else 2169 #if defined(CONFIG_P1010) 2170 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 2171 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2172 #elif defined(CONFIG_BSC9132) 2173 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 2174 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 2175 #elif defined(CONFIG_PPC_C29X) 2176 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 2177 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2178 #else 2179 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 2180 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 2181 #endif /* if defined(CONFIG_P1010) */ 2182 #endif 2183 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 2184 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 2185 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 2186 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 2187 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 2188 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 2189 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 2190 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 2191 u32 pordbgmsr; /* POR debug mode status */ 2192 u32 pordevsr2; /* POR I/O device status 2 */ 2193 #if defined(CONFIG_PPC_C29X) 2194 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 2195 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 2196 #endif 2197 /* The 8544 RM says this is bit 26, but it's really bit 24 */ 2198 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 2199 u8 res1[8]; 2200 u32 gpporcr; /* General-purpose POR configuration */ 2201 u8 res2[12]; 2202 #if defined(CONFIG_MPC8536) 2203 u32 gencfgr; /* General Configuration Register */ 2204 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 2205 #else 2206 u32 gpiocr; /* GPIO control */ 2207 #endif 2208 u8 res3[12]; 2209 #if defined(CONFIG_MPC8569) 2210 u32 plppar1; /* Platform port pin assignment 1 */ 2211 u32 plppar2; /* Platform port pin assignment 2 */ 2212 u32 plpdir1; /* Platform port pin direction 1 */ 2213 u32 plpdir2; /* Platform port pin direction 2 */ 2214 #else 2215 u32 gpoutdr; /* General-purpose output data */ 2216 u8 res4[12]; 2217 #endif 2218 u32 gpindr; /* General-purpose input data */ 2219 u8 res5[12]; 2220 u32 pmuxcr; /* Alt. function signal multiplex control */ 2221 #if defined(CONFIG_P1010) || defined(CONFIG_P1014) 2222 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 2223 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 2224 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 2225 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 2226 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 2227 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 2228 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 2229 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 2230 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 2231 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 2232 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 2233 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 2234 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 2235 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 2236 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 2237 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 2238 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 2239 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 2240 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 2241 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 2242 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 2243 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 2244 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 2245 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 2246 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 2247 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 2248 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 2249 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 2250 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 2251 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 2252 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 2253 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 2254 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 2255 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040 2256 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080 2257 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 2258 #define MPC85xx_PMUXCR_SPI_RES 0x00000030 2259 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 2260 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004 2261 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 2262 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C 2263 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001 2264 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 2265 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 2266 #endif 2267 #if defined(CONFIG_P1017) || defined(CONFIG_P1023) 2268 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000 2269 #else 2270 #define MPC85xx_PMUXCR_SD_DATA 0x80000000 2271 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 2272 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 2273 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 2274 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000 2275 #define MPC85xx_PMUXCR_QE0 0x00008000 2276 #define MPC85xx_PMUXCR_QE1 0x00004000 2277 #define MPC85xx_PMUXCR_QE2 0x00002000 2278 #define MPC85xx_PMUXCR_QE3 0x00001000 2279 #define MPC85xx_PMUXCR_QE4 0x00000800 2280 #define MPC85xx_PMUXCR_QE5 0x00000400 2281 #define MPC85xx_PMUXCR_QE6 0x00000200 2282 #define MPC85xx_PMUXCR_QE7 0x00000100 2283 #define MPC85xx_PMUXCR_QE8 0x00000080 2284 #define MPC85xx_PMUXCR_QE9 0x00000040 2285 #define MPC85xx_PMUXCR_QE10 0x00000020 2286 #define MPC85xx_PMUXCR_QE11 0x00000010 2287 #define MPC85xx_PMUXCR_QE12 0x00000008 2288 #endif 2289 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2290 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 2291 #define MPC85xx_PMUXCR_TDM 0x00014800 2292 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 2293 #define MPC85xx_PMUXCR_SPI 0x00000000 2294 #endif 2295 #if defined(CONFIG_BSC9131) 2296 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 2297 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 2298 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 2299 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 2300 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 2301 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 2302 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 2303 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 2304 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 2305 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 2306 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 2307 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 2308 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 2309 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 2310 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 2311 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 2312 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 2313 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 2314 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 2315 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 2316 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 2317 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 2318 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 2319 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 2320 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 2321 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 2322 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 2323 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 2324 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 2325 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 2326 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 2327 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 2328 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 2329 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 2330 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 2331 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 2332 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 2333 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 2334 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C 2335 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 2336 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 2337 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 2338 #endif 2339 #ifdef CONFIG_BSC9132 2340 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 2341 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 2342 #endif 2343 #if defined(CONFIG_PPC_C29X) 2344 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300 2345 #define MPC85xx_PMUXCR_SPI 0x00000000 2346 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 2347 #endif 2348 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ 2349 #if defined(CONFIG_P1010) || defined(CONFIG_P1014) 2350 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 2351 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000 2352 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000 2353 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 2354 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 2355 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 2356 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 2357 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 2358 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 2359 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 2360 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 2361 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 2362 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 2363 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 2364 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 2365 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 2366 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 2367 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 2368 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 2369 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 2370 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 2371 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 2372 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 2373 #endif 2374 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2375 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 2376 #define MPC85xx_PMUXCR2_USB 0x00150000 2377 #endif 2378 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) 2379 #if defined(CONFIG_BSC9131) 2380 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 2381 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 2382 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 2383 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 2384 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 2385 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 2386 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 2387 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 2388 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 2389 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 2390 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 2391 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 2392 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 2393 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 2394 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 2395 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 2396 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 2397 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 2398 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 2399 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 2400 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 2401 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 2402 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 2403 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 2404 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 2405 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 2406 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 2407 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 2408 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 2409 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 2410 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 2411 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 2412 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 2413 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 2414 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 2415 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 2416 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 2417 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 2418 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 2419 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 2420 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 2421 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 2422 #endif 2423 u32 pmuxcr3; 2424 #if defined(CONFIG_BSC9131) 2425 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 2426 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 2427 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 2428 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 2429 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 2430 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 2431 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 2432 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 2433 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 2434 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 2435 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 2436 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 2437 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 2438 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 2439 #endif 2440 #ifdef CONFIG_BSC9132 2441 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00 2442 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000 2443 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000 2444 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000 2445 #endif 2446 u32 pmuxcr4; 2447 #else 2448 u8 res6[8]; 2449 #endif 2450 u32 devdisr; /* Device disable control */ 2451 #define MPC85xx_DEVDISR_PCI1 0x80000000 2452 #define MPC85xx_DEVDISR_PCI2 0x40000000 2453 #define MPC85xx_DEVDISR_PCIE 0x20000000 2454 #define MPC85xx_DEVDISR_LBC 0x08000000 2455 #define MPC85xx_DEVDISR_PCIE2 0x04000000 2456 #define MPC85xx_DEVDISR_PCIE3 0x02000000 2457 #define MPC85xx_DEVDISR_SEC 0x01000000 2458 #define MPC85xx_DEVDISR_SRIO 0x00080000 2459 #define MPC85xx_DEVDISR_RMSG 0x00040000 2460 #define MPC85xx_DEVDISR_DDR 0x00010000 2461 #define MPC85xx_DEVDISR_CPU 0x00008000 2462 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU 2463 #define MPC85xx_DEVDISR_TB 0x00004000 2464 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB 2465 #define MPC85xx_DEVDISR_CPU1 0x00002000 2466 #define MPC85xx_DEVDISR_TB1 0x00001000 2467 #define MPC85xx_DEVDISR_DMA 0x00000400 2468 #define MPC85xx_DEVDISR_TSEC1 0x00000080 2469 #define MPC85xx_DEVDISR_TSEC2 0x00000040 2470 #define MPC85xx_DEVDISR_TSEC3 0x00000020 2471 #define MPC85xx_DEVDISR_TSEC4 0x00000010 2472 #define MPC85xx_DEVDISR_I2C 0x00000004 2473 #define MPC85xx_DEVDISR_DUART 0x00000002 2474 u8 res7[12]; 2475 u32 powmgtcsr; /* Power management status & control */ 2476 u8 res8[12]; 2477 u32 mcpsumr; /* Machine check summary */ 2478 u8 res9[12]; 2479 u32 pvr; /* Processor version */ 2480 u32 svr; /* System version */ 2481 u8 res10[8]; 2482 u32 rstcr; /* Reset control */ 2483 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) 2484 u8 res11a[76]; 2485 par_io_t qe_par_io[7]; 2486 u8 res11b[1600]; 2487 #elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 2488 u8 res11a[12]; 2489 u32 iovselsr; 2490 u8 res11b[60]; 2491 par_io_t qe_par_io[3]; 2492 u8 res11c[1496]; 2493 #else 2494 u8 res11a[1868]; 2495 #endif 2496 u32 clkdvdr; /* Clock Divide register */ 2497 u8 res12[1532]; 2498 u32 clkocr; /* Clock out select */ 2499 u8 res13[12]; 2500 u32 ddrdllcr; /* DDR DLL control */ 2501 u8 res14[12]; 2502 u32 lbcdllcr; /* LBC DLL control */ 2503 #if defined(CONFIG_BSC9131) 2504 u8 res15[12]; 2505 u32 halt_req_mask; 2506 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000 2507 u8 res18[232]; 2508 #else 2509 u8 res15[248]; 2510 #endif 2511 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ 2512 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ 2513 u32 ddrioovcr; /* DDR IO Override Control */ 2514 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ 2515 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ 2516 u8 res16[52]; 2517 u32 sdhcdcr; /* SDHC debug control register */ 2518 u8 res17[61592]; 2519 } ccsr_gur_t; 2520 #endif 2521 2522 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */ 2523 2524 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 2525 #define MAX_SERDES 4 2526 #define SRDS_MAX_LANES 8 2527 #define SRDS_MAX_BANK 2 2528 typedef struct serdes_corenet { 2529 struct { 2530 u32 rstctl; /* Reset Control Register */ 2531 #define SRDS_RSTCTL_RST 0x80000000 2532 #define SRDS_RSTCTL_RSTDONE 0x40000000 2533 #define SRDS_RSTCTL_RSTERR 0x20000000 2534 #define SRDS_RSTCTL_SWRST 0x10000000 2535 #define SRDS_RSTCTL_SDEN 0x00000020 2536 #define SRDS_RSTCTL_SDRST_B 0x00000040 2537 #define SRDS_RSTCTL_PLLRST_B 0x00000080 2538 #define SRDS_RSTCTL_RSTERR_SHIFT 29 2539 u32 pllcr0; /* PLL Control Register 0 */ 2540 #define SRDS_PLLCR0_POFF 0x80000000 2541 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 2542 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 2543 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 2544 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2545 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2546 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 2547 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 2548 #define SRDS_PLLCR0_PLL_LCK 0x00800000 2549 #define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000 2550 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 2551 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 2552 #define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000 2553 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 2554 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 2555 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 2556 #define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000 2557 #define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000 2558 #define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000 2559 #define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0 2560 #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4 2561 u32 pllcr1; /* PLL Control Register 1 */ 2562 #define SRDS_PLLCR1_BCAP_EN 0x20000000 2563 #define SRDS_PLLCR1_BCAP_OVD 0x10000000 2564 #define SRDS_PLLCR1_PLL_FCAP 0x001F8000 2565 #define SRDS_PLLCR1_PLL_FCAP_SHIFT 15 2566 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 2567 #define SRDS_PLLCR1_BYP_CAL 0x02000000 2568 u32 pllsr2; /* At 0x00c, PLL Status Register 2 */ 2569 #define SRDS_PLLSR2_BCAP_EN 0x00800000 2570 #define SRDS_PLLSR2_BCAP_EN_SHIFT 23 2571 #define SRDS_PLLSR2_FCAP 0x003F0000 2572 #define SRDS_PLLSR2_FCAP_SHIFT 16 2573 #define SRDS_PLLSR2_DCBIAS 0x000F0000 2574 #define SRDS_PLLSR2_DCBIAS_SHIFT 16 2575 u32 pllcr3; 2576 u32 pllcr4; 2577 u8 res_18[0x20-0x18]; 2578 } bank[2]; 2579 u8 res_40[0x90-0x40]; 2580 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 2581 u8 res_94[0xa0-0x94]; 2582 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 2583 u8 res_a4[0xb0-0xa4]; 2584 u32 srdsgr0; /* 0xb0 General Register 0 */ 2585 u8 res_b4[0xe0-0xb4]; 2586 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 2587 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 2588 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 2589 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 2590 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 2591 u8 res_f4[0x100-0xf4]; 2592 struct { 2593 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 2594 u8 res_104[0x120-0x104]; 2595 } srdslnpssr[8]; 2596 u8 res_200[0x800-0x200]; 2597 struct { 2598 u32 gcr0; /* 0x800 General Control Register 0 */ 2599 u32 gcr1; /* 0x804 General Control Register 1 */ 2600 u32 gcr2; /* 0x808 General Control Register 2 */ 2601 u32 res_80c; 2602 u32 recr0; /* 0x810 Receive Equalization Control */ 2603 u32 res_814; 2604 u32 tecr0; /* 0x818 Transmit Equalization Control */ 2605 u32 res_81c; 2606 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 2607 u8 res_824[0x840-0x824]; 2608 } lane[8]; /* Lane A, B, C, D, E, F, G, H */ 2609 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 2610 } serdes_corenet_t; 2611 2612 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2613 2614 #define SRDS_MAX_LANES 18 2615 #define SRDS_MAX_BANK 3 2616 typedef struct serdes_corenet { 2617 struct { 2618 u32 rstctl; /* Reset Control Register */ 2619 #define SRDS_RSTCTL_RST 0x80000000 2620 #define SRDS_RSTCTL_RSTDONE 0x40000000 2621 #define SRDS_RSTCTL_RSTERR 0x20000000 2622 #define SRDS_RSTCTL_SDPD 0x00000020 2623 u32 pllcr0; /* PLL Control Register 0 */ 2624 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 2625 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000 2626 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 2627 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 2628 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2629 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2630 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 2631 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 2632 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 2633 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 2634 u32 pllcr1; /* PLL Control Register 1 */ 2635 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 2636 u32 res[5]; 2637 } bank[3]; 2638 u32 res1[12]; 2639 u32 srdstcalcr; /* TX Calibration Control */ 2640 u32 res2[3]; 2641 u32 srdsrcalcr; /* RX Calibration Control */ 2642 u32 res3[3]; 2643 u32 srdsgr0; /* General Register 0 */ 2644 u32 res4[11]; 2645 u32 srdspccr0; /* Protocol Converter Config 0 */ 2646 u32 srdspccr1; /* Protocol Converter Config 1 */ 2647 u32 srdspccr2; /* Protocol Converter Config 2 */ 2648 #define SRDS_PCCR2_RST_XGMII1 0x00800000 2649 #define SRDS_PCCR2_RST_XGMII2 0x00400000 2650 u32 res5[197]; 2651 struct serdes_lane { 2652 u32 gcr0; /* General Control Register 0 */ 2653 #define SRDS_GCR0_RRST 0x00400000 2654 #define SRDS_GCR0_1STLANE 0x00010000 2655 #define SRDS_GCR0_UOTHL 0x00100000 2656 u32 gcr1; /* General Control Register 1 */ 2657 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 2658 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 2659 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 2660 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 2661 #define SRDS_GCR1_OPAD_CTL 0x04000000 2662 u32 res1[4]; 2663 u32 tecr0; /* TX Equalization Control Reg 0 */ 2664 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 2665 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 2666 u32 res3; 2667 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ 2668 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 2669 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000 2670 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000 2671 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000 2672 #define SRDS_TTLCR0_PM_DIS 0x00004000 2673 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001 2674 u32 res4[7]; 2675 } lane[24]; 2676 u32 res6[384]; 2677 } serdes_corenet_t; 2678 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2679 2680 enum { 2681 FSL_SRDS_B1_LANE_A = 0, 2682 FSL_SRDS_B1_LANE_B = 1, 2683 FSL_SRDS_B1_LANE_C = 2, 2684 FSL_SRDS_B1_LANE_D = 3, 2685 FSL_SRDS_B1_LANE_E = 4, 2686 FSL_SRDS_B1_LANE_F = 5, 2687 FSL_SRDS_B1_LANE_G = 6, 2688 FSL_SRDS_B1_LANE_H = 7, 2689 FSL_SRDS_B1_LANE_I = 8, 2690 FSL_SRDS_B1_LANE_J = 9, 2691 FSL_SRDS_B2_LANE_A = 16, 2692 FSL_SRDS_B2_LANE_B = 17, 2693 FSL_SRDS_B2_LANE_C = 18, 2694 FSL_SRDS_B2_LANE_D = 19, 2695 FSL_SRDS_B3_LANE_A = 20, 2696 FSL_SRDS_B3_LANE_B = 21, 2697 FSL_SRDS_B3_LANE_C = 22, 2698 FSL_SRDS_B3_LANE_D = 23, 2699 }; 2700 2701 typedef struct ccsr_qman { 2702 #ifdef CONFIG_SYS_FSL_QMAN_V3 2703 u8 res0[0x200]; 2704 #else 2705 struct { 2706 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 2707 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 2708 u32 res; 2709 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */ 2710 } qcsp[32]; 2711 #endif 2712 /* Not actually reserved, but irrelevant to u-boot */ 2713 u8 res[0xbf8 - 0x200]; 2714 u32 ip_rev_1; 2715 u32 ip_rev_2; 2716 u32 fqd_bare; /* FQD Extended Base Addr Register */ 2717 u32 fqd_bar; /* FQD Base Addr Register */ 2718 u8 res1[0x8]; 2719 u32 fqd_ar; /* FQD Attributes Register */ 2720 u8 res2[0xc]; 2721 u32 pfdr_bare; /* PFDR Extended Base Addr Register */ 2722 u32 pfdr_bar; /* PFDR Base Addr Register */ 2723 u8 res3[0x8]; 2724 u32 pfdr_ar; /* PFDR Attributes Register */ 2725 u8 res4[0x4c]; 2726 u32 qcsp_bare; /* QCSP Extended Base Addr Register */ 2727 u32 qcsp_bar; /* QCSP Base Addr Register */ 2728 u8 res5[0x78]; 2729 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ 2730 u32 srcidr; /* Source ID Register */ 2731 u32 liodnr; /* LIODN Register */ 2732 u8 res6[4]; 2733 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ 2734 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ 2735 u8 res7[0x2e8]; 2736 #ifdef CONFIG_SYS_FSL_QMAN_V3 2737 struct { 2738 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 2739 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 2740 u32 res; 2741 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ 2742 } qcsp[50]; 2743 #endif 2744 } ccsr_qman_t; 2745 2746 typedef struct ccsr_bman { 2747 /* Not actually reserved, but irrelevant to u-boot */ 2748 u8 res[0xbf8]; 2749 u32 ip_rev_1; 2750 u32 ip_rev_2; 2751 u32 fbpr_bare; /* FBPR Extended Base Addr Register */ 2752 u32 fbpr_bar; /* FBPR Base Addr Register */ 2753 u8 res1[0x8]; 2754 u32 fbpr_ar; /* FBPR Attributes Register */ 2755 u8 res2[0xf0]; 2756 u32 srcidr; /* Source ID Register */ 2757 u32 liodnr; /* LIODN Register */ 2758 u8 res7[0x2f4]; 2759 } ccsr_bman_t; 2760 2761 typedef struct ccsr_pme { 2762 u8 res0[0x804]; 2763 u32 liodnbr; /* LIODN Base Register */ 2764 u8 res1[0x1f8]; 2765 u32 srcidr; /* Source ID Register */ 2766 u8 res2[8]; 2767 u32 liodnr; /* LIODN Register */ 2768 u8 res3[0x1e8]; 2769 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/ 2770 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/ 2771 u8 res4[0x400]; 2772 } ccsr_pme_t; 2773 2774 #ifdef CONFIG_SYS_FSL_RAID_ENGINE 2775 struct ccsr_raide { 2776 u8 res0[0x543]; 2777 u32 liodnbr; /* LIODN Base Register */ 2778 u8 res1[0xab8]; 2779 struct { 2780 struct { 2781 u32 cfg0; /* cfg register 0 */ 2782 u32 cfg1; /* cfg register 1 */ 2783 u8 res1[0x3f8]; 2784 } ring[2]; 2785 u8 res[0x800]; 2786 } jq[2]; 2787 }; 2788 #endif 2789 2790 #ifdef CONFIG_SYS_DPAA_RMAN 2791 struct ccsr_rman { 2792 u8 res0[0xf64]; 2793 u32 mmliodnbr; /* Message Manager LIODN Base Register */ 2794 u32 mmitar; /* RMAN Inbound Translation Address Register */ 2795 u32 mmitdr; /* RMAN Inbound Translation Data Register */ 2796 u8 res4[0x1f090]; 2797 }; 2798 #endif 2799 2800 #ifdef CONFIG_SYS_PMAN 2801 struct ccsr_pman { 2802 u8 res_00[0x40]; 2803 u32 poes1; /* PMAN Operation Error Status Register 1 */ 2804 u32 poes2; /* PMAN Operation Error Status Register 2 */ 2805 u32 poeah; /* PMAN Operation Error Address High */ 2806 u32 poeal; /* PMAN Operation Error Address Low */ 2807 u8 res_50[0x50]; 2808 u32 pr1; /* PMAN Revision Register 1 */ 2809 u32 pr2; /* PMAN Revision Register 2 */ 2810 u8 res_a8[0x8]; 2811 u32 pcap; /* PMAN Capabilities Register */ 2812 u8 res_b4[0xc]; 2813 u32 pc1; /* PMAN Control Register 1 */ 2814 u32 pc2; /* PMAN Control Register 2 */ 2815 u32 pc3; /* PMAN Control Register 3 */ 2816 u32 pc4; /* PMAN Control Register 4 */ 2817 u32 pc5; /* PMAN Control Register 5 */ 2818 u32 pc6; /* PMAN Control Register 6 */ 2819 u8 res_d8[0x8]; 2820 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */ 2821 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */ 2822 u8 res_e8[0x8]; 2823 u32 pics; /* PMAN Interrupt Control and Status */ 2824 u8 res_f4[0xf0c]; 2825 }; 2826 #endif 2827 2828 #ifdef CONFIG_FSL_CORENET 2829 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 2830 #ifdef CONFIG_SYS_PMAN 2831 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 2832 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 2833 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 2834 #endif 2835 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000 2836 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000 2837 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 2838 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 2839 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 2840 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 2841 /* In SFPv3, OSPR register is now at offset 0x200. 2842 * * So directly mapping sfp register map to this address */ 2843 #define CONFIG_SYS_OSPR_OFFSET 0x200 2844 #define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) 2845 #else 2846 #define CONFIG_SYS_SFP_OFFSET 0xE8000 2847 #endif 2848 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 2849 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 2850 #define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 2851 #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 2852 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 2853 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 2854 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 2855 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 2856 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 2857 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET 2858 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 2859 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 2860 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 2861 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 2862 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 2863 #define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000 2864 #define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 2865 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 2866 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ 2867 && !defined(CONFIG_PPC_B4420) 2868 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 2869 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 2870 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 2871 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 2872 #else 2873 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 2874 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 2875 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 2876 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 2877 #endif 2878 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 2879 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 2880 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 2881 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 2882 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 2883 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 2884 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 2885 #define CONFIG_SYS_FSL_JR0_OFFSET 0x301000 2886 #define CONFIG_SYS_SEC_MON_OFFSET 0x314000 2887 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 2888 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 2889 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 2890 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 2891 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 2892 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 2893 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 2894 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 2895 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 2896 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 2897 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 2898 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 2899 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 2900 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 2901 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 2902 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 2903 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 2904 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 2905 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 2906 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 2907 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 2908 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 2909 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 2910 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 2911 #else 2912 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 2913 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 2914 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 2915 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 2916 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 2917 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 2918 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 2919 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 2920 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 2921 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 2922 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 2923 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) 2924 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 2925 #else 2926 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 2927 #endif 2928 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 2929 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 2930 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 2931 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 2932 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 2933 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 2934 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000 2935 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 2936 #ifdef CONFIG_TSECV2 2937 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 2938 #elif defined(CONFIG_TSECV2_1) 2939 #define CONFIG_SYS_TSEC1_OFFSET 0x10000 2940 #else 2941 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 2942 #endif 2943 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 2944 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 2945 #if defined(CONFIG_PPC_C29X) 2946 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 2947 #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 2948 #else 2949 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 2950 #define CONFIG_SYS_FSL_JR0_OFFSET 0x31000 2951 #endif 2952 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 2953 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 2954 #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 2955 #define CONFIG_SYS_SFP_OFFSET 0xE7000 2956 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 2957 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 2958 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 2959 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 2960 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 2961 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 2962 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 2963 #endif 2964 2965 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 2966 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 2967 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 2968 2969 #if defined(CONFIG_BSC9132) 2970 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 2971 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ 2972 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) 2973 #endif 2974 2975 #define CONFIG_SYS_FSL_CPC_ADDR \ 2976 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) 2977 #define CONFIG_SYS_FSL_SCFG_ADDR \ 2978 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) 2979 #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ 2980 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) 2981 #define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \ 2982 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET) 2983 #define CONFIG_SYS_FSL_QMAN_ADDR \ 2984 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) 2985 #define CONFIG_SYS_FSL_BMAN_ADDR \ 2986 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) 2987 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ 2988 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) 2989 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ 2990 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) 2991 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ 2992 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) 2993 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ 2994 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) 2995 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ 2996 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) 2997 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ 2998 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) 2999 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ 3000 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) 3001 #define CONFIG_SYS_MPC85xx_ECM_ADDR \ 3002 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) 3003 #define CONFIG_SYS_FSL_DDR_ADDR \ 3004 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) 3005 #define CONFIG_SYS_FSL_DDR2_ADDR \ 3006 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) 3007 #define CONFIG_SYS_FSL_DDR3_ADDR \ 3008 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET) 3009 #define CONFIG_SYS_LBC_ADDR \ 3010 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) 3011 #define CONFIG_SYS_IFC_ADDR \ 3012 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) 3013 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ 3014 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) 3015 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ 3016 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) 3017 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ 3018 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) 3019 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \ 3020 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) 3021 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \ 3022 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) 3023 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \ 3024 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) 3025 #define CONFIG_SYS_MPC85xx_L2_ADDR \ 3026 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) 3027 #define CONFIG_SYS_MPC85xx_DMA_ADDR \ 3028 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) 3029 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ 3030 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) 3031 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \ 3032 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) 3033 #define CONFIG_SYS_MPC85xx_CPM_ADDR \ 3034 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) 3035 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ 3036 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET) 3037 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ 3038 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 3039 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ 3040 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) 3041 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ 3042 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) 3043 #define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \ 3044 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET) 3045 #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \ 3046 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET) 3047 #define CONFIG_SYS_MPC85xx_USB1_ADDR \ 3048 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) 3049 #define CONFIG_SYS_MPC85xx_USB2_ADDR \ 3050 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET) 3051 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ 3052 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) 3053 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ 3054 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) 3055 #define CONFIG_SYS_FSL_SEC_ADDR \ 3056 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 3057 #define CONFIG_SYS_FSL_JR0_ADDR \ 3058 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 3059 #define CONFIG_SYS_FSL_FM1_ADDR \ 3060 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 3061 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 3062 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 3063 #define CONFIG_SYS_FSL_FM2_ADDR \ 3064 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) 3065 #define CONFIG_SYS_FSL_SRIO_ADDR \ 3066 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) 3067 3068 #define CONFIG_SYS_PCI1_ADDR \ 3069 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) 3070 #define CONFIG_SYS_PCI2_ADDR \ 3071 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) 3072 #define CONFIG_SYS_PCIE1_ADDR \ 3073 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) 3074 #define CONFIG_SYS_PCIE2_ADDR \ 3075 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) 3076 #define CONFIG_SYS_PCIE3_ADDR \ 3077 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) 3078 #define CONFIG_SYS_PCIE4_ADDR \ 3079 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) 3080 3081 #define CONFIG_SYS_SFP_ADDR \ 3082 (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) 3083 3084 #define CONFIG_SYS_SEC_MON_ADDR \ 3085 (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET) 3086 3087 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 3088 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 3089 3090 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 3091 struct ccsr_cluster_l2 { 3092 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */ 3093 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */ 3094 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */ 3095 u8 res_0c[500];/* 0x00c - 0x1ff */ 3096 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */ 3097 u8 res_204[4]; 3098 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */ 3099 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */ 3100 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */ 3101 u8 res_214[4]; 3102 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */ 3103 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */ 3104 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */ 3105 u8 res_224[4]; 3106 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */ 3107 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */ 3108 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */ 3109 u8 res_234[4]; 3110 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */ 3111 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */ 3112 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */ 3113 u8 res244[4]; 3114 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */ 3115 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */ 3116 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */ 3117 u8 res_254[4]; 3118 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */ 3119 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */ 3120 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */ 3121 u8 res_264[4]; 3122 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */ 3123 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */ 3124 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */ 3125 u8 res274[4]; 3126 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */ 3127 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */ 3128 u8 res_280[0xb80]; /* 0x280 - 0xdff */ 3129 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */ 3130 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */ 3131 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */ 3132 u8 res_e0c[20]; /* 0xe0c - 0x01f */ 3133 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */ 3134 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */ 3135 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */ 3136 u8 res_e2c[20]; /* 0xe2c - 0xe3f */ 3137 u32 l2errdet; /* 0xe40 L2 cache error detect */ 3138 u32 l2errdis; /* 0xe44 L2 cache error disable */ 3139 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */ 3140 u32 l2errattr; /* 0xe4c L2 cache error attribute */ 3141 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */ 3142 u32 l2erraddr; /* 0xe54 L2 cache error address */ 3143 u32 l2errctl; /* 0xe58 L2 cache error control */ 3144 }; 3145 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \ 3146 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET) 3147 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 3148 3149 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 3150 struct dcsr_dcfg_regs { 3151 u8 res_0[0x520]; 3152 u32 ecccr1; 3153 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000 3154 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 3155 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ 3156 }; 3157 3158 #define CONFIG_SYS_MPC85xx_SCFG \ 3159 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET) 3160 #define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 3161 /* The supplement configuration unit register */ 3162 struct ccsr_scfg { 3163 u32 dpslpcr; /* 0x000 Deep Sleep Control register */ 3164 u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */ 3165 u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */ 3166 u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */ 3167 u32 res1[4]; 3168 u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */ 3169 u32 res2; 3170 u32 pixclkcr; /* 0x028 Pixel Clock Control register */ 3171 u32 res3[245]; 3172 u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */ 3173 u32 emiiocr; /* 0x404 EMI MDIO Control Register */ 3174 u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */ 3175 u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */ 3176 u32 res4[60]; 3177 u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ 3178 }; 3179 #endif /*__IMMAP_85xx__*/ 3180