1 /*
2  * Copyright 2004-2011 Freescale Semiconductor, Inc.
3  *
4  * MPC83xx Internal Memory Map
5  *
6  * Contributors:
7  *	Dave Liu <daveliu@freescale.com>
8  *	Tanya Jiang <tanya.jiang@freescale.com>
9  *	Mandy Lavi <mandy.lavi@freescale.com>
10  *	Eran Liberty <liberty@freescale.com>
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  *
27  */
28 #ifndef __IMMAP_83xx__
29 #define __IMMAP_83xx__
30 
31 #include <asm/types.h>
32 #include <asm/fsl_i2c.h>
33 #include <asm/mpc8xxx_spi.h>
34 #include <asm/fsl_lbc.h>
35 #include <asm/fsl_dma.h>
36 
37 /*
38  * Local Access Window
39  */
40 typedef struct law83xx {
41 	u32 bar;		/* LBIU local access window base address register */
42 	u32 ar;			/* LBIU local access window attribute register */
43 } law83xx_t;
44 
45 /*
46  * System configuration registers
47  */
48 typedef struct sysconf83xx {
49 	u32 immrbar;		/* Internal memory map base address register */
50 	u8 res0[0x04];
51 	u32 altcbar;		/* Alternate configuration base address register */
52 	u8 res1[0x14];
53 	law83xx_t lblaw[4];	/* LBIU local access window */
54 	u8 res2[0x20];
55 	law83xx_t pcilaw[2];	/* PCI local access window */
56 	u8 res3[0x10];
57 	law83xx_t pcielaw[2];	/* PCI Express local access window */
58 	u8 res4[0x10];
59 	law83xx_t ddrlaw[2];	/* DDR local access window */
60 	u8 res5[0x50];
61 	u32 sgprl;		/* System General Purpose Register Low */
62 	u32 sgprh;		/* System General Purpose Register High */
63 	u32 spridr;		/* System Part and Revision ID Register */
64 	u8 res6[0x04];
65 	u32 spcr;		/* System Priority Configuration Register */
66 	u32 sicrl;		/* System I/O Configuration Register Low */
67 	u32 sicrh;		/* System I/O Configuration Register High */
68 	u8 res7[0x04];
69 	u32 sidcr0;		/* System I/O Delay Configuration Register 0 */
70 	u32 sidcr1;		/* System I/O Delay Configuration Register 1 */
71 	u32 ddrcdr;		/* DDR Control Driver Register */
72 	u32 ddrdsr;		/* DDR Debug Status Register */
73 	u32 obir;		/* Output Buffer Impedance Register */
74 	u8 res8[0xC];
75 	u32 pecr1;		/* PCI Express control register 1 */
76 #ifdef CONFIG_MPC8308
77 	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
78 #else
79 	u32 pecr2;		/* PCI Express control register 2 */
80 #endif
81 	u8 res9[0xB8];
82 } sysconf83xx_t;
83 
84 /*
85  * Watch Dog Timer (WDT) Registers
86  */
87 typedef struct wdt83xx {
88 	u8 res0[4];
89 	u32 swcrr;		/* System watchdog control register */
90 	u32 swcnr;		/* System watchdog count register */
91 	u8 res1[2];
92 	u16 swsrr;		/* System watchdog service register */
93 	u8 res2[0xF0];
94 } wdt83xx_t;
95 
96 /*
97  * RTC/PIT Module Registers
98  */
99 typedef struct rtclk83xx {
100 	u32 cnr;		/* control register */
101 	u32 ldr;		/* load register */
102 	u32 psr;		/* prescale register */
103 	u32 ctr;		/* counter value field register */
104 	u32 evr;		/* event register */
105 	u32 alr;		/* alarm register */
106 	u8 res0[0xE8];
107 } rtclk83xx_t;
108 
109 /*
110  * Global timer module
111  */
112 typedef struct gtm83xx {
113 	u8 cfr1;		/* Timer1/2 Configuration */
114 	u8 res0[3];
115 	u8 cfr2;		/* Timer3/4 Configuration */
116 	u8 res1[11];
117 	u16 mdr1;		/* Timer1 Mode Register */
118 	u16 mdr2;		/* Timer2 Mode Register */
119 	u16 rfr1;		/* Timer1 Reference Register */
120 	u16 rfr2;		/* Timer2 Reference Register */
121 	u16 cpr1;		/* Timer1 Capture Register */
122 	u16 cpr2;		/* Timer2 Capture Register */
123 	u16 cnr1;		/* Timer1 Counter Register */
124 	u16 cnr2;		/* Timer2 Counter Register */
125 	u16 mdr3;		/* Timer3 Mode Register */
126 	u16 mdr4;		/* Timer4 Mode Register */
127 	u16 rfr3;		/* Timer3 Reference Register */
128 	u16 rfr4;		/* Timer4 Reference Register */
129 	u16 cpr3;		/* Timer3 Capture Register */
130 	u16 cpr4;		/* Timer4 Capture Register */
131 	u16 cnr3;		/* Timer3 Counter Register */
132 	u16 cnr4;		/* Timer4 Counter Register */
133 	u16 evr1;		/* Timer1 Event Register */
134 	u16 evr2;		/* Timer2 Event Register */
135 	u16 evr3;		/* Timer3 Event Register */
136 	u16 evr4;		/* Timer4 Event Register */
137 	u16 psr1;		/* Timer1 Prescaler Register */
138 	u16 psr2;		/* Timer2 Prescaler Register */
139 	u16 psr3;		/* Timer3 Prescaler Register */
140 	u16 psr4;		/* Timer4 Prescaler Register */
141 	u8 res[0xC0];
142 } gtm83xx_t;
143 
144 /*
145  * Integrated Programmable Interrupt Controller
146  */
147 typedef struct ipic83xx {
148 	u32 sicfr;		/* System Global Interrupt Configuration Register */
149 	u32 sivcr;		/* System Global Interrupt Vector Register */
150 	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
151 	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
152 	u32 siprr_a;		/* System Internal Interrupt Group A Priority Register */
153 	u8 res0[8];
154 	u32 siprr_d;		/* System Internal Interrupt Group D Priority Register */
155 	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
156 	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
157 	u8 res1[4];
158 	u32 sepnr;		/* System External Interrupt Pending Register */
159 	u32 smprr_a;		/* System Mixed Interrupt Group A Priority Register */
160 	u32 smprr_b;		/* System Mixed Interrupt Group B Priority Register */
161 	u32 semsr;		/* System External Interrupt Mask Register */
162 	u32 secnr;		/* System External Interrupt Control Register */
163 	u32 sersr;		/* System Error Status Register */
164 	u32 sermr;		/* System Error Mask Register */
165 	u32 sercr;		/* System Error Control Register */
166 	u8 res2[4];
167 	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
168 	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
169 	u32 sefcr;		/* System External Interrupt Force Register */
170 	u32 serfr;		/* System Error Force Register */
171 	u32 scvcr;		/* System Critical Interrupt Vector Register */
172 	u32 smvcr;		/* System Management Interrupt Vector Register */
173 	u8 res3[0x98];
174 } ipic83xx_t;
175 
176 /*
177  * System Arbiter Registers
178  */
179 typedef struct arbiter83xx {
180 	u32 acr;		/* Arbiter Configuration Register */
181 	u32 atr;		/* Arbiter Timers Register */
182 	u8 res[4];
183 	u32 aer;		/* Arbiter Event Register */
184 	u32 aidr;		/* Arbiter Interrupt Definition Register */
185 	u32 amr;		/* Arbiter Mask Register */
186 	u32 aeatr;		/* Arbiter Event Attributes Register */
187 	u32 aeadr;		/* Arbiter Event Address Register */
188 	u32 aerr;		/* Arbiter Event Response Register */
189 	u8 res1[0xDC];
190 } arbiter83xx_t;
191 
192 /*
193  * Reset Module
194  */
195 typedef struct reset83xx {
196 	u32 rcwl;		/* Reset Configuration Word Low Register */
197 	u32 rcwh;		/* Reset Configuration Word High Register */
198 	u8 res0[8];
199 	u32 rsr;		/* Reset Status Register */
200 	u32 rmr;		/* Reset Mode Register */
201 	u32 rpr;		/* Reset protection Register */
202 	u32 rcr;		/* Reset Control Register */
203 	u32 rcer;		/* Reset Control Enable Register */
204 	u8 res1[0xDC];
205 } reset83xx_t;
206 
207 /*
208  * Clock Module
209  */
210 typedef struct clk83xx {
211 	u32 spmr;		/* system PLL mode Register */
212 	u32 occr;		/* output clock control Register */
213 	u32 sccr;		/* system clock control Register */
214 	u8 res0[0xF4];
215 } clk83xx_t;
216 
217 /*
218  * Power Management Control Module
219  */
220 typedef struct pmc83xx {
221 	u32 pmccr;		/* PMC Configuration Register */
222 	u32 pmcer;		/* PMC Event Register */
223 	u32 pmcmr;		/* PMC Mask Register */
224 	u32 pmccr1;		/* PMC Configuration Register 1 */
225 	u32 pmccr2;		/* PMC Configuration Register 2 */
226 	u8 res0[0xEC];
227 } pmc83xx_t;
228 
229 /*
230  * General purpose I/O module
231  */
232 typedef struct gpio83xx {
233 	u32 dir;		/* direction register */
234 	u32 odr;		/* open drain register */
235 	u32 dat;		/* data register */
236 	u32 ier;		/* interrupt event register */
237 	u32 imr;		/* interrupt mask register */
238 	u32 icr;		/* external interrupt control register */
239 	u8 res0[0xE8];
240 } gpio83xx_t;
241 
242 /*
243  * QE Ports Interrupts Registers
244  */
245 typedef struct qepi83xx {
246 	u8 res0[0xC];
247 	u32 qepier;		/* QE Ports Interrupt Event Register */
248 	u32 qepimr;		/* QE Ports Interrupt Mask Register */
249 	u32 qepicr;		/* QE Ports Interrupt Control Register */
250 	u8 res1[0xE8];
251 } qepi83xx_t;
252 
253 /*
254  * QE Parallel I/O Ports
255  */
256 typedef struct gpio_n {
257 	u32 podr;		/* Open Drain Register */
258 	u32 pdat;		/* Data Register */
259 	u32 dir1;		/* direction register 1 */
260 	u32 dir2;		/* direction register 2 */
261 	u32 ppar1;		/* Pin Assignment Register 1 */
262 	u32 ppar2;		/* Pin Assignment Register 2 */
263 } gpio_n_t;
264 
265 typedef struct qegpio83xx {
266 	gpio_n_t ioport[0x7];
267 	u8 res0[0x358];
268 } qepio83xx_t;
269 
270 /*
271  * QE Secondary Bus Access Windows
272  */
273 typedef struct qesba83xx {
274 	u32 lbmcsar;		/* Local bus memory controller start address */
275 	u32 sdmcsar;		/* Secondary DDR memory controller start address */
276 	u8 res0[0x38];
277 	u32 lbmcear;		/* Local bus memory controller end address */
278 	u32 sdmcear;		/* Secondary DDR memory controller end address */
279 	u8 res1[0x38];
280 	u32 lbmcar;		/* Local bus memory controller attributes */
281 	u32 sdmcar;		/* Secondary DDR memory controller attributes */
282 	u8 res2[0x378];
283 } qesba83xx_t;
284 
285 /*
286  * DDR Memory Controller Memory Map
287  */
288 #if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
289 typedef struct ccsr_ddr {
290 	u32	cs0_bnds;		/* Chip Select 0 Memory Bounds */
291 	u8	res1[4];
292 	u32	cs1_bnds;		/* Chip Select 1 Memory Bounds */
293 	u8	res2[4];
294 	u32	cs2_bnds;		/* Chip Select 2 Memory Bounds */
295 	u8	res3[4];
296 	u32	cs3_bnds;		/* Chip Select 3 Memory Bounds */
297 	u8	res4[100];
298 	u32	cs0_config;		/* Chip Select Configuration */
299 	u32	cs1_config;		/* Chip Select Configuration */
300 	u32	cs2_config;		/* Chip Select Configuration */
301 	u32	cs3_config;		/* Chip Select Configuration */
302 	u8	res4a[48];
303 	u32	cs0_config_2;		/* Chip Select Configuration 2 */
304 	u32	cs1_config_2;		/* Chip Select Configuration 2 */
305 	u32	cs2_config_2;		/* Chip Select Configuration 2 */
306 	u32	cs3_config_2;		/* Chip Select Configuration 2 */
307 	u8	res5[48];
308 	u32	timing_cfg_3;		/* SDRAM Timing Configuration 3 */
309 	u32	timing_cfg_0;		/* SDRAM Timing Configuration 0 */
310 	u32	timing_cfg_1;		/* SDRAM Timing Configuration 1 */
311 	u32	timing_cfg_2;		/* SDRAM Timing Configuration 2 */
312 	u32	sdram_cfg;		/* SDRAM Control Configuration */
313 	u32	sdram_cfg_2;		/* SDRAM Control Configuration 2 */
314 	u32	sdram_mode;		/* SDRAM Mode Configuration */
315 	u32	sdram_mode_2;		/* SDRAM Mode Configuration 2 */
316 	u32	sdram_md_cntl;		/* SDRAM Mode Control */
317 	u32	sdram_interval;		/* SDRAM Interval Configuration */
318 	u32	sdram_data_init;	/* SDRAM Data initialization */
319 	u8	res6[4];
320 	u32	sdram_clk_cntl;		/* SDRAM Clock Control */
321 	u8	res7[20];
322 	u32	init_addr;		/* training init addr */
323 	u32	init_ext_addr;		/* training init extended addr */
324 	u8	res8_1[16];
325 	u32	timing_cfg_4;		/* SDRAM Timing Configuration 4 */
326 	u32	timing_cfg_5;		/* SDRAM Timing Configuration 5 */
327 	u8	reg8_1a[8];
328 	u32	ddr_zq_cntl;		/* ZQ calibration control*/
329 	u32	ddr_wrlvl_cntl;		/* write leveling control*/
330 	u8	reg8_1aa[4];
331 	u32	ddr_sr_cntr;		/* self refresh counter */
332 	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
333 	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
334 	u8	reg_1ab[8];
335 	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
336 	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
337 	u8	res8_1b[104];
338 	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
339 	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
340 	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
341 	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
342 	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
343 	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
344 	u8	res8_1ba[0x908];
345 	u32	ddr_dsr1;		/* Debug Status 1 */
346 	u32	ddr_dsr2;		/* Debug Status 2 */
347 	u32	ddr_cdr1;		/* Control Driver 1 */
348 	u32	ddr_cdr2;		/* Control Driver 2 */
349 	u8	res8_1c[200];
350 	u32	ip_rev1;		/* IP Block Revision 1 */
351 	u32	ip_rev2;		/* IP Block Revision 2 */
352 	u32	eor;			/* Enhanced Optimization Register */
353 	u8	res8_2[252];
354 	u32	mtcr;			/* Memory Test Control Register */
355 	u8	res8_3[28];
356 	u32	mtp1;			/* Memory Test Pattern 1 */
357 	u32	mtp2;			/* Memory Test Pattern 2 */
358 	u32	mtp3;			/* Memory Test Pattern 3 */
359 	u32	mtp4;			/* Memory Test Pattern 4 */
360 	u32	mtp5;			/* Memory Test Pattern 5 */
361 	u32	mtp6;			/* Memory Test Pattern 6 */
362 	u32	mtp7;			/* Memory Test Pattern 7 */
363 	u32	mtp8;			/* Memory Test Pattern 8 */
364 	u32	mtp9;			/* Memory Test Pattern 9 */
365 	u32	mtp10;			/* Memory Test Pattern 10 */
366 	u8	res8_4[184];
367 	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
368 	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
369 	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
370 	u8	res9[20];
371 	u32	capture_data_hi;	/* Data Path Read Capture High */
372 	u32	capture_data_lo;	/* Data Path Read Capture Low */
373 	u32	capture_ecc;		/* Data Path Read Capture ECC */
374 	u8	res10[20];
375 	u32	err_detect;		/* Error Detect */
376 	u32	err_disable;		/* Error Disable */
377 	u32	err_int_en;
378 	u32	capture_attributes;	/* Error Attrs Capture */
379 	u32	capture_address;	/* Error Addr Capture */
380 	u32	capture_ext_address;	/* Error Extended Addr Capture */
381 	u32	err_sbe;		/* Single-Bit ECC Error Management */
382 	u8	res11[164];
383 	u32	debug[32];		/* debug_1 to debug_32 */
384 	u8	res12[128];
385 } ccsr_ddr_t;
386 #else
387 typedef struct ddr_cs_bnds {
388 	u32 csbnds;
389 	u8 res0[4];
390 } ddr_cs_bnds_t;
391 
392 typedef struct ddr83xx {
393 	ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
394 	u8 res0[0x60];
395 	u32 cs_config[4];	/* Chip Select x Configuration */
396 	u8 res1[0x70];
397 	u32 timing_cfg_3;	/* SDRAM Timing Configuration 3 */
398 	u32 timing_cfg_0;	/* SDRAM Timing Configuration 0 */
399 	u32 timing_cfg_1;	/* SDRAM Timing Configuration 1 */
400 	u32 timing_cfg_2;	/* SDRAM Timing Configuration 2 */
401 	u32 sdram_cfg;		/* SDRAM Control Configuration */
402 	u32 sdram_cfg2;		/* SDRAM Control Configuration 2 */
403 	u32 sdram_mode;		/* SDRAM Mode Configuration */
404 	u32 sdram_mode2;	/* SDRAM Mode Configuration 2 */
405 	u32 sdram_md_cntl;	/* SDRAM Mode Control */
406 	u32 sdram_interval;	/* SDRAM Interval Configuration */
407 	u32 ddr_data_init;	/* SDRAM Data Initialization */
408 	u8 res2[4];
409 	u32 sdram_clk_cntl;	/* SDRAM Clock Control */
410 	u8 res3[0x14];
411 	u32 ddr_init_addr;	/* DDR training initialization address */
412 	u32 ddr_init_ext_addr;	/* DDR training initialization extended address */
413 	u8 res4[0xAA8];
414 	u32 ddr_ip_rev1;	/* DDR IP block revision 1 */
415 	u32 ddr_ip_rev2;	/* DDR IP block revision 2 */
416 	u8 res5[0x200];
417 	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
418 	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
419 	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
420 	u8 res6[0x14];
421 	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
422 	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
423 	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
424 	u8 res7[0x14];
425 	u32 err_detect;		/* Memory Error Detect */
426 	u32 err_disable;	/* Memory Error Disable */
427 	u32 err_int_en;		/* Memory Error Interrupt Enable */
428 	u32 capture_attributes;	/* Memory Error Attributes Capture */
429 	u32 capture_address;	/* Memory Error Address Capture */
430 	u32 capture_ext_address;/* Memory Error Extended Address Capture */
431 	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
432 	u8 res8[0xA4];
433 	u32 debug_reg;
434 	u8 res9[0xFC];
435 } ddr83xx_t;
436 #endif
437 
438 /*
439  * DUART
440  */
441 typedef struct duart83xx {
442 	u8 urbr_ulcr_udlb;	/* combined register for URBR, UTHR and UDLB */
443 	u8 uier_udmb;		/* combined register for UIER and UDMB */
444 	u8 uiir_ufcr_uafr;	/* combined register for UIIR, UFCR and UAFR */
445 	u8 ulcr;		/* line control register */
446 	u8 umcr;		/* MODEM control register */
447 	u8 ulsr;		/* line status register */
448 	u8 umsr;		/* MODEM status register */
449 	u8 uscr;		/* scratch register */
450 	u8 res0[8];
451 	u8 udsr;		/* DMA status register */
452 	u8 res1[3];
453 	u8 res2[0xEC];
454 } duart83xx_t;
455 
456 /*
457  * DMA/Messaging Unit
458  */
459 typedef struct dma83xx {
460 	u32 res0[0xC];		/* 0x0-0x29 reseverd */
461 	u32 omisr;		/* 0x30 Outbound message interrupt status register */
462 	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
463 	u32 res1[0x6];		/* 0x38-0x49 reserved */
464 	u32 imr0;		/* 0x50 Inbound message register 0 */
465 	u32 imr1;		/* 0x54 Inbound message register 1 */
466 	u32 omr0;		/* 0x58 Outbound message register 0 */
467 	u32 omr1;		/* 0x5C Outbound message register 1 */
468 	u32 odr;		/* 0x60 Outbound doorbell register */
469 	u32 res2;		/* 0x64-0x67 reserved */
470 	u32 idr;		/* 0x68 Inbound doorbell register */
471 	u32 res3[0x5];		/* 0x6C-0x79 reserved */
472 	u32 imisr;		/* 0x80 Inbound message interrupt status register */
473 	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
474 	u32 res4[0x1E];		/* 0x88-0x99 reserved */
475 	struct fsl_dma dma[4];
476 } dma83xx_t;
477 
478 /*
479  * PCI Software Configuration Registers
480  */
481 typedef struct pciconf83xx {
482 	u32 config_address;
483 	u32 config_data;
484 	u32 int_ack;
485 	u8 res[116];
486 } pciconf83xx_t;
487 
488 /*
489  * PCI Outbound Translation Register
490  */
491 typedef struct pci_outbound_window {
492 	u32 potar;
493 	u8 res0[4];
494 	u32 pobar;
495 	u8 res1[4];
496 	u32 pocmr;
497 	u8 res2[4];
498 } pot83xx_t;
499 
500 /*
501  * Sequencer
502  */
503 typedef struct ios83xx {
504 	pot83xx_t pot[6];
505 	u8 res0[0x60];
506 	u32 pmcr;
507 	u8 res1[4];
508 	u32 dtcr;
509 	u8 res2[4];
510 } ios83xx_t;
511 
512 /*
513  * PCI Controller Control and Status Registers
514  */
515 typedef struct pcictrl83xx {
516 	u32 esr;
517 	u32 ecdr;
518 	u32 eer;
519 	u32 eatcr;
520 	u32 eacr;
521 	u32 eeacr;
522 	u32 edlcr;
523 	u32 edhcr;
524 	u32 gcr;
525 	u32 ecr;
526 	u32 gsr;
527 	u8 res0[12];
528 	u32 pitar2;
529 	u8 res1[4];
530 	u32 pibar2;
531 	u32 piebar2;
532 	u32 piwar2;
533 	u8 res2[4];
534 	u32 pitar1;
535 	u8 res3[4];
536 	u32 pibar1;
537 	u32 piebar1;
538 	u32 piwar1;
539 	u8 res4[4];
540 	u32 pitar0;
541 	u8 res5[4];
542 	u32 pibar0;
543 	u8 res6[4];
544 	u32 piwar0;
545 	u8 res7[132];
546 } pcictrl83xx_t;
547 
548 /*
549  * USB
550  */
551 typedef struct usb83xx {
552 	u8 fixme[0x1000];
553 } usb83xx_t;
554 
555 /*
556  * TSEC
557  */
558 typedef struct tsec83xx {
559 	u8 fixme[0x1000];
560 } tsec83xx_t;
561 
562 /*
563  * Security
564  */
565 typedef struct security83xx {
566 	u8 fixme[0x10000];
567 } security83xx_t;
568 
569 /*
570  *  PCI Express
571  */
572 struct pex_inbound_window {
573 	u32 ar;
574 	u32 tar;
575 	u32 barl;
576 	u32 barh;
577 };
578 
579 struct pex_outbound_window {
580 	u32 ar;
581 	u32 bar;
582 	u32 tarl;
583 	u32 tarh;
584 };
585 
586 struct pex_csb_bridge {
587 	u32 pex_csb_ver;
588 	u32 pex_csb_cab;
589 	u32 pex_csb_ctrl;
590 	u8 res0[8];
591 	u32 pex_dms_dstmr;
592 	u8 res1[4];
593 	u32 pex_cbs_stat;
594 	u8 res2[0x20];
595 	u32 pex_csb_obctrl;
596 	u32 pex_csb_obstat;
597 	u8 res3[0x98];
598 	u32 pex_csb_ibctrl;
599 	u32 pex_csb_ibstat;
600 	u8 res4[0xb8];
601 	u32 pex_wdma_ctrl;
602 	u32 pex_wdma_addr;
603 	u32 pex_wdma_stat;
604 	u8 res5[0x94];
605 	u32 pex_rdma_ctrl;
606 	u32 pex_rdma_addr;
607 	u32 pex_rdma_stat;
608 	u8 res6[0xd4];
609 	u32 pex_ombcr;
610 	u32 pex_ombdr;
611 	u8 res7[0x38];
612 	u32 pex_imbcr;
613 	u32 pex_imbdr;
614 	u8 res8[0x38];
615 	u32 pex_int_enb;
616 	u32 pex_int_stat;
617 	u32 pex_int_apio_vec1;
618 	u32 pex_int_apio_vec2;
619 	u8 res9[0x10];
620 	u32 pex_int_ppio_vec1;
621 	u32 pex_int_ppio_vec2;
622 	u32 pex_int_wdma_vec1;
623 	u32 pex_int_wdma_vec2;
624 	u32 pex_int_rdma_vec1;
625 	u32 pex_int_rdma_vec2;
626 	u32 pex_int_misc_vec;
627 	u8 res10[4];
628 	u32 pex_int_axi_pio_enb;
629 	u32 pex_int_axi_wdma_enb;
630 	u32 pex_int_axi_rdma_enb;
631 	u32 pex_int_axi_misc_enb;
632 	u32 pex_int_axi_pio_stat;
633 	u32 pex_int_axi_wdma_stat;
634 	u32 pex_int_axi_rdma_stat;
635 	u32 pex_int_axi_misc_stat;
636 	u8 res11[0xa0];
637 	struct pex_outbound_window pex_outbound_win[4];
638 	u8 res12[0x100];
639 	u32 pex_epiwtar0;
640 	u32 pex_epiwtar1;
641 	u32 pex_epiwtar2;
642 	u32 pex_epiwtar3;
643 	u8 res13[0x70];
644 	struct pex_inbound_window pex_inbound_win[4];
645 };
646 
647 typedef struct pex83xx {
648 	u8 pex_cfg_header[0x404];
649 	u32 pex_ltssm_stat;
650 	u8 res0[0x30];
651 	u32 pex_ack_replay_timeout;
652 	u8 res1[4];
653 	u32 pex_gclk_ratio;
654 	u8 res2[0xc];
655 	u32 pex_pm_timer;
656 	u32 pex_pme_timeout;
657 	u8 res3[4];
658 	u32 pex_aspm_req_timer;
659 	u8 res4[0x18];
660 	u32 pex_ssvid_update;
661 	u8 res5[0x34];
662 	u32 pex_cfg_ready;
663 	u8 res6[0x24];
664 	u32 pex_bar_sizel;
665 	u8 res7[4];
666 	u32 pex_bar_sel;
667 	u8 res8[0x20];
668 	u32 pex_bar_pf;
669 	u8 res9[0x88];
670 	u32 pex_pme_to_ack_tor;
671 	u8 res10[0xc];
672 	u32 pex_ss_intr_mask;
673 	u8 res11[0x25c];
674 	struct pex_csb_bridge bridge;
675 	u8 res12[0x160];
676 } pex83xx_t;
677 
678 /*
679  * SATA
680  */
681 typedef struct sata83xx {
682 	u8 fixme[0x1000];
683 } sata83xx_t;
684 
685 /*
686  * eSDHC
687  */
688 typedef struct sdhc83xx {
689 	u8 fixme[0x1000];
690 } sdhc83xx_t;
691 
692 /*
693  * SerDes
694  */
695 typedef struct serdes83xx {
696 	u32 srdscr0;
697 	u32 srdscr1;
698 	u32 srdscr2;
699 	u32 srdscr3;
700 	u32 srdscr4;
701 	u8 res0[0xc];
702 	u32 srdsrstctl;
703 	u8 res1[0xdc];
704 } serdes83xx_t;
705 
706 /*
707  * On Chip ROM
708  */
709 typedef struct rom83xx {
710 	u8 mem[0x10000];
711 } rom83xx_t;
712 
713 /*
714  * TDM
715  */
716 typedef struct tdm83xx {
717 	u8 fixme[0x200];
718 } tdm83xx_t;
719 
720 /*
721  * TDM DMAC
722  */
723 typedef struct tdmdmac83xx {
724 	u8 fixme[0x2000];
725 } tdmdmac83xx_t;
726 
727 #if defined(CONFIG_MPC834x)
728 typedef struct immap {
729 	sysconf83xx_t		sysconf;	/* System configuration */
730 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
731 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
732 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
733 	gtm83xx_t		gtm[2];		/* Global Timers Module */
734 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
735 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
736 	reset83xx_t		reset;		/* Reset Module */
737 	clk83xx_t		clk;		/* System Clock Module */
738 	pmc83xx_t		pmc;		/* Power Management Control Module */
739 	gpio83xx_t		gpio[2];	/* General purpose I/O module */
740 	u8			res0[0x200];
741 	u8			dll_ddr[0x100];
742 	u8			dll_lbc[0x100];
743 	u8			res1[0xE00];
744 #if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
745 	ccsr_ddr_t		ddr;	/* DDR Memory Controller Memory */
746 #else
747 	ddr83xx_t		ddr;	/* DDR Memory Controller Memory */
748 #endif
749 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
750 	u8			res2[0x1300];
751 	duart83xx_t		duart[2];	/* DUART */
752 	u8			res3[0x900];
753 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
754 	u8			res4[0x1000];
755 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
756 	dma83xx_t		dma;		/* DMA */
757 	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
758 	ios83xx_t		ios;		/* Sequencer */
759 	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
760 	u8			res5[0x19900];
761 	usb83xx_t		usb[2];
762 	tsec83xx_t		tsec[2];
763 	u8			res6[0xA000];
764 	security83xx_t		security;
765 	u8			res7[0xC0000];
766 } immap_t;
767 
768 #ifdef CONFIG_HAS_FSL_MPH_USB
769 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x22000	/* use the MPH controller */
770 #else
771 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000	/* use the DR controller */
772 #endif
773 
774 #elif defined(CONFIG_MPC8313)
775 typedef struct immap {
776 	sysconf83xx_t		sysconf;	/* System configuration */
777 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
778 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
779 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
780 	gtm83xx_t		gtm[2];		/* Global Timers Module */
781 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
782 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
783 	reset83xx_t		reset;		/* Reset Module */
784 	clk83xx_t		clk;		/* System Clock Module */
785 	pmc83xx_t		pmc;		/* Power Management Control Module */
786 	gpio83xx_t		gpio[1];	/* General purpose I/O module */
787 	u8			res0[0x1300];
788 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
789 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
790 	u8			res1[0x1300];
791 	duart83xx_t		duart[2];	/* DUART */
792 	u8			res2[0x900];
793 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
794 	u8			res3[0x1000];
795 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
796 	dma83xx_t		dma;		/* DMA */
797 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
798 	u8			res4[0x80];
799 	ios83xx_t		ios;		/* Sequencer */
800 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
801 	u8			res5[0x1aa00];
802 	usb83xx_t		usb[1];
803 	tsec83xx_t		tsec[2];
804 	u8			res6[0xA000];
805 	security83xx_t		security;
806 	u8			res7[0xC0000];
807 } immap_t;
808 
809 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
810 typedef struct immap {
811 	sysconf83xx_t		sysconf;	/* System configuration */
812 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
813 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
814 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
815 	gtm83xx_t		gtm[2];		/* Global Timers Module */
816 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
817 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
818 	reset83xx_t		reset;		/* Reset Module */
819 	clk83xx_t		clk;		/* System Clock Module */
820 	pmc83xx_t		pmc;		/* Power Management Control Module */
821 	gpio83xx_t		gpio[1];	/* General purpose I/O module */
822 	u8			res0[0x1300];
823 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
824 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
825 	u8			res1[0x1300];
826 	duart83xx_t		duart[2];	/* DUART */
827 	u8			res2[0x900];
828 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
829 	u8			res3[0x1000];
830 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
831 	dma83xx_t		dma;		/* DMA */
832 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
833 	u8			res4[0x80];
834 	ios83xx_t		ios;		/* Sequencer */
835 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
836 	u8			res5[0xa00];
837 	pex83xx_t		pciexp[2];	/* PCI Express Controller */
838 	u8			res6[0xb000];
839 	tdm83xx_t		tdm;		/* TDM Controller */
840 	u8			res7[0x1e00];
841 	sata83xx_t		sata[2];	/* SATA Controller */
842 	u8			res8[0x9000];
843 	usb83xx_t		usb[1];		/* USB DR Controller */
844 	tsec83xx_t		tsec[2];
845 	u8			res9[0x6000];
846 	tdmdmac83xx_t		tdmdmac;	/* TDM DMAC */
847 	u8			res10[0x2000];
848 	security83xx_t		security;
849 	u8			res11[0xA3000];
850 	serdes83xx_t		serdes[1];	/* SerDes Registers */
851 	u8			res12[0x1CF00];
852 } immap_t;
853 
854 #elif defined(CONFIG_MPC837x)
855 typedef struct immap {
856 	sysconf83xx_t		sysconf;	/* System configuration */
857 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
858 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
859 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
860 	gtm83xx_t		gtm[2];		/* Global Timers Module */
861 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
862 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
863 	reset83xx_t		reset;		/* Reset Module */
864 	clk83xx_t		clk;		/* System Clock Module */
865 	pmc83xx_t		pmc;		/* Power Management Control Module */
866 	gpio83xx_t		gpio[2];	/* General purpose I/O module */
867 	u8			res0[0x1200];
868 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
869 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
870 	u8			res1[0x1300];
871 	duart83xx_t		duart[2];	/* DUART */
872 	u8			res2[0x900];
873 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
874 	u8			res3[0x1000];
875 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
876 	dma83xx_t		dma;		/* DMA */
877 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
878 	u8			res4[0x80];
879 	ios83xx_t		ios;		/* Sequencer */
880 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
881 	u8			res5[0xa00];
882 	pex83xx_t		pciexp[2];	/* PCI Express Controller */
883 	u8			res6[0xd000];
884 	sata83xx_t		sata[4];	/* SATA Controller */
885 	u8			res7[0x7000];
886 	usb83xx_t		usb[1];		/* USB DR Controller */
887 	tsec83xx_t		tsec[2];
888 	u8			res8[0x8000];
889 	sdhc83xx_t		sdhc;		/* SDHC Controller */
890 	u8			res9[0x1000];
891 	security83xx_t		security;
892 	u8			res10[0xA3000];
893 	serdes83xx_t		serdes[2];	/* SerDes Registers */
894 	u8			res11[0xCE00];
895 	rom83xx_t		rom;		/* On Chip ROM */
896 } immap_t;
897 
898 #elif defined(CONFIG_MPC8360)
899 typedef struct immap {
900 	sysconf83xx_t		sysconf;	/* System configuration */
901 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
902 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
903 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
904 	u8			res0[0x200];
905 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
906 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
907 	reset83xx_t		reset;		/* Reset Module */
908 	clk83xx_t		clk;		/* System Clock Module */
909 	pmc83xx_t		pmc;		/* Power Management Control Module */
910 	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
911 	u8			res1[0x300];
912 	u8			dll_ddr[0x100];
913 	u8			dll_lbc[0x100];
914 	u8			res2[0x200];
915 	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
916 	qesba83xx_t		qesba;		/* QE Secondary Bus Access Windows */
917 	u8			res3[0x400];
918 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
919 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
920 	u8			res4[0x1300];
921 	duart83xx_t		duart[2];	/* DUART */
922 	u8			res5[0x900];
923 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
924 	u8			res6[0x2000];
925 	dma83xx_t		dma;		/* DMA */
926 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
927 	u8			res7[128];
928 	ios83xx_t		ios;		/* Sequencer (IOS) */
929 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
930 	u8			res8[0x4A00];
931 	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
932 	u8			res9[0x22000];
933 	security83xx_t		security;
934 	u8			res10[0xC0000];
935 	u8			qe[0x100000];	/* QE block */
936 } immap_t;
937 
938 #elif defined(CONFIG_MPC832x)
939 typedef struct immap {
940 	sysconf83xx_t		sysconf;	/* System configuration */
941 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
942 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
943 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
944 	gtm83xx_t		gtm[2];		/* Global Timers Module */
945 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
946 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
947 	reset83xx_t		reset;		/* Reset Module */
948 	clk83xx_t		clk;		/* System Clock Module */
949 	pmc83xx_t		pmc;		/* Power Management Control Module */
950 	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
951 	u8			res0[0x300];
952 	u8			dll_ddr[0x100];
953 	u8			dll_lbc[0x100];
954 	u8			res1[0x200];
955 	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
956 	u8			res2[0x800];
957 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
958 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
959 	u8			res3[0x1300];
960 	duart83xx_t		duart[2];	/* DUART */
961 	u8			res4[0x900];
962 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
963 	u8			res5[0x2000];
964 	dma83xx_t		dma;		/* DMA */
965 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
966 	u8			res6[128];
967 	ios83xx_t		ios;		/* Sequencer (IOS) */
968 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
969 	u8			res7[0x27A00];
970 	security83xx_t		security;
971 	u8			res8[0xC0000];
972 	u8			qe[0x100000];	/* QE block */
973 } immap_t;
974 #endif
975 
976 #define CONFIG_SYS_MPC83xx_DDR_OFFSET	(0x2000)
977 #define CONFIG_SYS_MPC83xx_DDR_ADDR \
978 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET)
979 #define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
980 #define CONFIG_SYS_MPC83xx_DMA_ADDR \
981 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
982 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
983 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
984 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
985 
986 #ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
987 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000
988 #endif
989 #define CONFIG_SYS_MPC83xx_USB_ADDR \
990 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
991 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
992 
993 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
994 #define CONFIG_SYS_MDIO1_OFFSET		0x24000
995 
996 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
997 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
998 #endif				/* __IMMAP_83xx__ */
999