1 /*
2  * Copyright 2004-2011 Freescale Semiconductor, Inc.
3  *
4  * MPC83xx Internal Memory Map
5  *
6  * Contributors:
7  *	Dave Liu <daveliu@freescale.com>
8  *	Tanya Jiang <tanya.jiang@freescale.com>
9  *	Mandy Lavi <mandy.lavi@freescale.com>
10  *	Eran Liberty <liberty@freescale.com>
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  *
27  */
28 #ifndef __IMMAP_83xx__
29 #define __IMMAP_83xx__
30 
31 #include <asm/types.h>
32 #include <asm/fsl_i2c.h>
33 #include <asm/mpc8xxx_spi.h>
34 #include <asm/fsl_lbc.h>
35 #include <asm/fsl_dma.h>
36 
37 /*
38  * Local Access Window
39  */
40 typedef struct law83xx {
41 	u32 bar;		/* LBIU local access window base address register */
42 	u32 ar;			/* LBIU local access window attribute register */
43 } law83xx_t;
44 
45 /*
46  * System configuration registers
47  */
48 typedef struct sysconf83xx {
49 	u32 immrbar;		/* Internal memory map base address register */
50 	u8 res0[0x04];
51 	u32 altcbar;		/* Alternate configuration base address register */
52 	u8 res1[0x14];
53 	law83xx_t lblaw[4];	/* LBIU local access window */
54 	u8 res2[0x20];
55 	law83xx_t pcilaw[2];	/* PCI local access window */
56 	u8 res3[0x10];
57 	law83xx_t pcielaw[2];	/* PCI Express local access window */
58 	u8 res4[0x10];
59 	law83xx_t ddrlaw[2];	/* DDR local access window */
60 	u8 res5[0x50];
61 	u32 sgprl;		/* System General Purpose Register Low */
62 	u32 sgprh;		/* System General Purpose Register High */
63 	u32 spridr;		/* System Part and Revision ID Register */
64 	u8 res6[0x04];
65 	u32 spcr;		/* System Priority Configuration Register */
66 	u32 sicrl;		/* System I/O Configuration Register Low */
67 	u32 sicrh;		/* System I/O Configuration Register High */
68 	u8 res7[0x04];
69 	u32 sidcr0;		/* System I/O Delay Configuration Register 0 */
70 	u32 sidcr1;		/* System I/O Delay Configuration Register 1 */
71 	u32 ddrcdr;		/* DDR Control Driver Register */
72 	u32 ddrdsr;		/* DDR Debug Status Register */
73 	u32 obir;		/* Output Buffer Impedance Register */
74 	u8 res8[0xC];
75 	u32 pecr1;		/* PCI Express control register 1 */
76 #if defined(CONFIG_MPC830x)
77 	u32 sdhccr;		/* eSDHC Control Registers for MPC830x */
78 #else
79 	u32 pecr2;		/* PCI Express control register 2 */
80 #endif
81 #if defined(CONFIG_MPC8309)
82 	u32 can_dbg_ctrl;
83 	u32 res9a;
84 	u32 gpr1;
85 	u8 res9b[0xAC];
86 #else
87 	u8 res9[0xB8];
88 #endif
89 } sysconf83xx_t;
90 
91 /*
92  * Watch Dog Timer (WDT) Registers
93  */
94 typedef struct wdt83xx {
95 	u8 res0[4];
96 	u32 swcrr;		/* System watchdog control register */
97 	u32 swcnr;		/* System watchdog count register */
98 	u8 res1[2];
99 	u16 swsrr;		/* System watchdog service register */
100 	u8 res2[0xF0];
101 } wdt83xx_t;
102 
103 /*
104  * RTC/PIT Module Registers
105  */
106 typedef struct rtclk83xx {
107 	u32 cnr;		/* control register */
108 	u32 ldr;		/* load register */
109 	u32 psr;		/* prescale register */
110 	u32 ctr;		/* counter value field register */
111 	u32 evr;		/* event register */
112 	u32 alr;		/* alarm register */
113 	u8 res0[0xE8];
114 } rtclk83xx_t;
115 
116 /*
117  * Global timer module
118  */
119 typedef struct gtm83xx {
120 	u8 cfr1;		/* Timer1/2 Configuration */
121 	u8 res0[3];
122 	u8 cfr2;		/* Timer3/4 Configuration */
123 	u8 res1[11];
124 	u16 mdr1;		/* Timer1 Mode Register */
125 	u16 mdr2;		/* Timer2 Mode Register */
126 	u16 rfr1;		/* Timer1 Reference Register */
127 	u16 rfr2;		/* Timer2 Reference Register */
128 	u16 cpr1;		/* Timer1 Capture Register */
129 	u16 cpr2;		/* Timer2 Capture Register */
130 	u16 cnr1;		/* Timer1 Counter Register */
131 	u16 cnr2;		/* Timer2 Counter Register */
132 	u16 mdr3;		/* Timer3 Mode Register */
133 	u16 mdr4;		/* Timer4 Mode Register */
134 	u16 rfr3;		/* Timer3 Reference Register */
135 	u16 rfr4;		/* Timer4 Reference Register */
136 	u16 cpr3;		/* Timer3 Capture Register */
137 	u16 cpr4;		/* Timer4 Capture Register */
138 	u16 cnr3;		/* Timer3 Counter Register */
139 	u16 cnr4;		/* Timer4 Counter Register */
140 	u16 evr1;		/* Timer1 Event Register */
141 	u16 evr2;		/* Timer2 Event Register */
142 	u16 evr3;		/* Timer3 Event Register */
143 	u16 evr4;		/* Timer4 Event Register */
144 	u16 psr1;		/* Timer1 Prescaler Register */
145 	u16 psr2;		/* Timer2 Prescaler Register */
146 	u16 psr3;		/* Timer3 Prescaler Register */
147 	u16 psr4;		/* Timer4 Prescaler Register */
148 	u8 res[0xC0];
149 } gtm83xx_t;
150 
151 /*
152  * Integrated Programmable Interrupt Controller
153  */
154 typedef struct ipic83xx {
155 	u32 sicfr;		/* System Global Interrupt Configuration Register */
156 	u32 sivcr;		/* System Global Interrupt Vector Register */
157 	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
158 	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
159 	u32 siprr_a;		/* System Internal Interrupt Group A Priority Register */
160 	u32 siprr_b;		/* System Internal Interrupt Group B Priority Register */
161 	u32 siprr_c;		/* System Internal Interrupt Group C Priority Register */
162 	u32 siprr_d;		/* System Internal Interrupt Group D Priority Register */
163 	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
164 	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
165 	u32 sicnr;		/* System Internal Interrupt Control Register */
166 	u32 sepnr;		/* System External Interrupt Pending Register */
167 	u32 smprr_a;		/* System Mixed Interrupt Group A Priority Register */
168 	u32 smprr_b;		/* System Mixed Interrupt Group B Priority Register */
169 	u32 semsr;		/* System External Interrupt Mask Register */
170 	u32 secnr;		/* System External Interrupt Control Register */
171 	u32 sersr;		/* System Error Status Register */
172 	u32 sermr;		/* System Error Mask Register */
173 	u32 sercr;		/* System Error Control Register */
174 	u32 sepcr;		/* System External Interrupt Polarity Control Register */
175 	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
176 	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
177 	u32 sefcr;		/* System External Interrupt Force Register */
178 	u32 serfr;		/* System Error Force Register */
179 	u32 scvcr;		/* System Critical Interrupt Vector Register */
180 	u32 smvcr;		/* System Management Interrupt Vector Register */
181 	u8 res[0x98];
182 } ipic83xx_t;
183 
184 /*
185  * System Arbiter Registers
186  */
187 typedef struct arbiter83xx {
188 	u32 acr;		/* Arbiter Configuration Register */
189 	u32 atr;		/* Arbiter Timers Register */
190 	u8 res[4];
191 	u32 aer;		/* Arbiter Event Register */
192 	u32 aidr;		/* Arbiter Interrupt Definition Register */
193 	u32 amr;		/* Arbiter Mask Register */
194 	u32 aeatr;		/* Arbiter Event Attributes Register */
195 	u32 aeadr;		/* Arbiter Event Address Register */
196 	u32 aerr;		/* Arbiter Event Response Register */
197 	u8 res1[0xDC];
198 } arbiter83xx_t;
199 
200 /*
201  * Reset Module
202  */
203 typedef struct reset83xx {
204 	u32 rcwl;		/* Reset Configuration Word Low Register */
205 	u32 rcwh;		/* Reset Configuration Word High Register */
206 	u8 res0[8];
207 	u32 rsr;		/* Reset Status Register */
208 	u32 rmr;		/* Reset Mode Register */
209 	u32 rpr;		/* Reset protection Register */
210 	u32 rcr;		/* Reset Control Register */
211 	u32 rcer;		/* Reset Control Enable Register */
212 	u8 res1[0xDC];
213 } reset83xx_t;
214 
215 /*
216  * Clock Module
217  */
218 typedef struct clk83xx {
219 	u32 spmr;		/* system PLL mode Register */
220 	u32 occr;		/* output clock control Register */
221 	u32 sccr;		/* system clock control Register */
222 	u8 res0[0xF4];
223 } clk83xx_t;
224 
225 /*
226  * Power Management Control Module
227  */
228 typedef struct pmc83xx {
229 	u32 pmccr;		/* PMC Configuration Register */
230 	u32 pmcer;		/* PMC Event Register */
231 	u32 pmcmr;		/* PMC Mask Register */
232 	u32 pmccr1;		/* PMC Configuration Register 1 */
233 	u32 pmccr2;		/* PMC Configuration Register 2 */
234 	u8 res0[0xEC];
235 } pmc83xx_t;
236 
237 /*
238  * General purpose I/O module
239  */
240 typedef struct gpio83xx {
241 	u32 dir;		/* direction register */
242 	u32 odr;		/* open drain register */
243 	u32 dat;		/* data register */
244 	u32 ier;		/* interrupt event register */
245 	u32 imr;		/* interrupt mask register */
246 	u32 icr;		/* external interrupt control register */
247 	u8 res0[0xE8];
248 } gpio83xx_t;
249 
250 /*
251  * QE Ports Interrupts Registers
252  */
253 typedef struct qepi83xx {
254 	u8 res0[0xC];
255 	u32 qepier;		/* QE Ports Interrupt Event Register */
256 	u32 qepimr;		/* QE Ports Interrupt Mask Register */
257 	u32 qepicr;		/* QE Ports Interrupt Control Register */
258 	u8 res1[0xE8];
259 } qepi83xx_t;
260 
261 /*
262  * QE Parallel I/O Ports
263  */
264 typedef struct gpio_n {
265 	u32 podr;		/* Open Drain Register */
266 	u32 pdat;		/* Data Register */
267 	u32 dir1;		/* direction register 1 */
268 	u32 dir2;		/* direction register 2 */
269 	u32 ppar1;		/* Pin Assignment Register 1 */
270 	u32 ppar2;		/* Pin Assignment Register 2 */
271 } gpio_n_t;
272 
273 typedef struct qegpio83xx {
274 	gpio_n_t ioport[0x7];
275 	u8 res0[0x358];
276 } qepio83xx_t;
277 
278 /*
279  * QE Secondary Bus Access Windows
280  */
281 typedef struct qesba83xx {
282 	u32 lbmcsar;		/* Local bus memory controller start address */
283 	u32 sdmcsar;		/* Secondary DDR memory controller start address */
284 	u8 res0[0x38];
285 	u32 lbmcear;		/* Local bus memory controller end address */
286 	u32 sdmcear;		/* Secondary DDR memory controller end address */
287 	u8 res1[0x38];
288 	u32 lbmcar;		/* Local bus memory controller attributes */
289 	u32 sdmcar;		/* Secondary DDR memory controller attributes */
290 	u8 res2[0x378];
291 } qesba83xx_t;
292 
293 /*
294  * DDR Memory Controller Memory Map
295  */
296 #if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
297 typedef struct ccsr_ddr {
298 	u32	cs0_bnds;		/* Chip Select 0 Memory Bounds */
299 	u8	res1[4];
300 	u32	cs1_bnds;		/* Chip Select 1 Memory Bounds */
301 	u8	res2[4];
302 	u32	cs2_bnds;		/* Chip Select 2 Memory Bounds */
303 	u8	res3[4];
304 	u32	cs3_bnds;		/* Chip Select 3 Memory Bounds */
305 	u8	res4[100];
306 	u32	cs0_config;		/* Chip Select Configuration */
307 	u32	cs1_config;		/* Chip Select Configuration */
308 	u32	cs2_config;		/* Chip Select Configuration */
309 	u32	cs3_config;		/* Chip Select Configuration */
310 	u8	res4a[48];
311 	u32	cs0_config_2;		/* Chip Select Configuration 2 */
312 	u32	cs1_config_2;		/* Chip Select Configuration 2 */
313 	u32	cs2_config_2;		/* Chip Select Configuration 2 */
314 	u32	cs3_config_2;		/* Chip Select Configuration 2 */
315 	u8	res5[48];
316 	u32	timing_cfg_3;		/* SDRAM Timing Configuration 3 */
317 	u32	timing_cfg_0;		/* SDRAM Timing Configuration 0 */
318 	u32	timing_cfg_1;		/* SDRAM Timing Configuration 1 */
319 	u32	timing_cfg_2;		/* SDRAM Timing Configuration 2 */
320 	u32	sdram_cfg;		/* SDRAM Control Configuration */
321 	u32	sdram_cfg_2;		/* SDRAM Control Configuration 2 */
322 	u32	sdram_mode;		/* SDRAM Mode Configuration */
323 	u32	sdram_mode_2;		/* SDRAM Mode Configuration 2 */
324 	u32	sdram_md_cntl;		/* SDRAM Mode Control */
325 	u32	sdram_interval;		/* SDRAM Interval Configuration */
326 	u32	sdram_data_init;	/* SDRAM Data initialization */
327 	u8	res6[4];
328 	u32	sdram_clk_cntl;		/* SDRAM Clock Control */
329 	u8	res7[20];
330 	u32	init_addr;		/* training init addr */
331 	u32	init_ext_addr;		/* training init extended addr */
332 	u8	res8_1[16];
333 	u32	timing_cfg_4;		/* SDRAM Timing Configuration 4 */
334 	u32	timing_cfg_5;		/* SDRAM Timing Configuration 5 */
335 	u8	reg8_1a[8];
336 	u32	ddr_zq_cntl;		/* ZQ calibration control*/
337 	u32	ddr_wrlvl_cntl;		/* write leveling control*/
338 	u8	reg8_1aa[4];
339 	u32	ddr_sr_cntr;		/* self refresh counter */
340 	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
341 	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
342 	u8	reg_1ab[8];
343 	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
344 	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
345 	u8	res8_1b[104];
346 	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
347 	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
348 	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
349 	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
350 	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
351 	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
352 	u8	res8_1ba[0x908];
353 	u32	ddr_dsr1;		/* Debug Status 1 */
354 	u32	ddr_dsr2;		/* Debug Status 2 */
355 	u32	ddr_cdr1;		/* Control Driver 1 */
356 	u32	ddr_cdr2;		/* Control Driver 2 */
357 	u8	res8_1c[200];
358 	u32	ip_rev1;		/* IP Block Revision 1 */
359 	u32	ip_rev2;		/* IP Block Revision 2 */
360 	u32	eor;			/* Enhanced Optimization Register */
361 	u8	res8_2[252];
362 	u32	mtcr;			/* Memory Test Control Register */
363 	u8	res8_3[28];
364 	u32	mtp1;			/* Memory Test Pattern 1 */
365 	u32	mtp2;			/* Memory Test Pattern 2 */
366 	u32	mtp3;			/* Memory Test Pattern 3 */
367 	u32	mtp4;			/* Memory Test Pattern 4 */
368 	u32	mtp5;			/* Memory Test Pattern 5 */
369 	u32	mtp6;			/* Memory Test Pattern 6 */
370 	u32	mtp7;			/* Memory Test Pattern 7 */
371 	u32	mtp8;			/* Memory Test Pattern 8 */
372 	u32	mtp9;			/* Memory Test Pattern 9 */
373 	u32	mtp10;			/* Memory Test Pattern 10 */
374 	u8	res8_4[184];
375 	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
376 	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
377 	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
378 	u8	res9[20];
379 	u32	capture_data_hi;	/* Data Path Read Capture High */
380 	u32	capture_data_lo;	/* Data Path Read Capture Low */
381 	u32	capture_ecc;		/* Data Path Read Capture ECC */
382 	u8	res10[20];
383 	u32	err_detect;		/* Error Detect */
384 	u32	err_disable;		/* Error Disable */
385 	u32	err_int_en;
386 	u32	capture_attributes;	/* Error Attrs Capture */
387 	u32	capture_address;	/* Error Addr Capture */
388 	u32	capture_ext_address;	/* Error Extended Addr Capture */
389 	u32	err_sbe;		/* Single-Bit ECC Error Management */
390 	u8	res11[164];
391 	u32	debug[32];		/* debug_1 to debug_32 */
392 	u8	res12[128];
393 } ccsr_ddr_t;
394 #else
395 typedef struct ddr_cs_bnds {
396 	u32 csbnds;
397 	u8 res0[4];
398 } ddr_cs_bnds_t;
399 
400 typedef struct ddr83xx {
401 	ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
402 	u8 res0[0x60];
403 	u32 cs_config[4];	/* Chip Select x Configuration */
404 	u8 res1[0x70];
405 	u32 timing_cfg_3;	/* SDRAM Timing Configuration 3 */
406 	u32 timing_cfg_0;	/* SDRAM Timing Configuration 0 */
407 	u32 timing_cfg_1;	/* SDRAM Timing Configuration 1 */
408 	u32 timing_cfg_2;	/* SDRAM Timing Configuration 2 */
409 	u32 sdram_cfg;		/* SDRAM Control Configuration */
410 	u32 sdram_cfg2;		/* SDRAM Control Configuration 2 */
411 	u32 sdram_mode;		/* SDRAM Mode Configuration */
412 	u32 sdram_mode2;	/* SDRAM Mode Configuration 2 */
413 	u32 sdram_md_cntl;	/* SDRAM Mode Control */
414 	u32 sdram_interval;	/* SDRAM Interval Configuration */
415 	u32 ddr_data_init;	/* SDRAM Data Initialization */
416 	u8 res2[4];
417 	u32 sdram_clk_cntl;	/* SDRAM Clock Control */
418 	u8 res3[0x14];
419 	u32 ddr_init_addr;	/* DDR training initialization address */
420 	u32 ddr_init_ext_addr;	/* DDR training initialization extended address */
421 	u8 res4[0xAA8];
422 	u32 ddr_ip_rev1;	/* DDR IP block revision 1 */
423 	u32 ddr_ip_rev2;	/* DDR IP block revision 2 */
424 	u8 res5[0x200];
425 	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
426 	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
427 	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
428 	u8 res6[0x14];
429 	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
430 	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
431 	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
432 	u8 res7[0x14];
433 	u32 err_detect;		/* Memory Error Detect */
434 	u32 err_disable;	/* Memory Error Disable */
435 	u32 err_int_en;		/* Memory Error Interrupt Enable */
436 	u32 capture_attributes;	/* Memory Error Attributes Capture */
437 	u32 capture_address;	/* Memory Error Address Capture */
438 	u32 capture_ext_address;/* Memory Error Extended Address Capture */
439 	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
440 	u8 res8[0xA4];
441 	u32 debug_reg;
442 	u8 res9[0xFC];
443 } ddr83xx_t;
444 #endif
445 
446 /*
447  * DUART
448  */
449 typedef struct duart83xx {
450 	u8 urbr_ulcr_udlb;	/* combined register for URBR, UTHR and UDLB */
451 	u8 uier_udmb;		/* combined register for UIER and UDMB */
452 	u8 uiir_ufcr_uafr;	/* combined register for UIIR, UFCR and UAFR */
453 	u8 ulcr;		/* line control register */
454 	u8 umcr;		/* MODEM control register */
455 	u8 ulsr;		/* line status register */
456 	u8 umsr;		/* MODEM status register */
457 	u8 uscr;		/* scratch register */
458 	u8 res0[8];
459 	u8 udsr;		/* DMA status register */
460 	u8 res1[3];
461 	u8 res2[0xEC];
462 } duart83xx_t;
463 
464 /*
465  * DMA/Messaging Unit
466  */
467 typedef struct dma83xx {
468 	u32 res0[0xC];		/* 0x0-0x29 reseverd */
469 	u32 omisr;		/* 0x30 Outbound message interrupt status register */
470 	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
471 	u32 res1[0x6];		/* 0x38-0x49 reserved */
472 	u32 imr0;		/* 0x50 Inbound message register 0 */
473 	u32 imr1;		/* 0x54 Inbound message register 1 */
474 	u32 omr0;		/* 0x58 Outbound message register 0 */
475 	u32 omr1;		/* 0x5C Outbound message register 1 */
476 	u32 odr;		/* 0x60 Outbound doorbell register */
477 	u32 res2;		/* 0x64-0x67 reserved */
478 	u32 idr;		/* 0x68 Inbound doorbell register */
479 	u32 res3[0x5];		/* 0x6C-0x79 reserved */
480 	u32 imisr;		/* 0x80 Inbound message interrupt status register */
481 	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
482 	u32 res4[0x1E];		/* 0x88-0x99 reserved */
483 	struct fsl_dma dma[4];
484 } dma83xx_t;
485 
486 /*
487  * PCI Software Configuration Registers
488  */
489 typedef struct pciconf83xx {
490 	u32 config_address;
491 	u32 config_data;
492 	u32 int_ack;
493 	u8 res[116];
494 } pciconf83xx_t;
495 
496 /*
497  * PCI Outbound Translation Register
498  */
499 typedef struct pci_outbound_window {
500 	u32 potar;
501 	u8 res0[4];
502 	u32 pobar;
503 	u8 res1[4];
504 	u32 pocmr;
505 	u8 res2[4];
506 } pot83xx_t;
507 
508 /*
509  * Sequencer
510  */
511 typedef struct ios83xx {
512 	pot83xx_t pot[6];
513 	u8 res0[0x60];
514 	u32 pmcr;
515 	u8 res1[4];
516 	u32 dtcr;
517 	u8 res2[4];
518 } ios83xx_t;
519 
520 /*
521  * PCI Controller Control and Status Registers
522  */
523 typedef struct pcictrl83xx {
524 	u32 esr;
525 	u32 ecdr;
526 	u32 eer;
527 	u32 eatcr;
528 	u32 eacr;
529 	u32 eeacr;
530 	u32 edlcr;
531 	u32 edhcr;
532 	u32 gcr;
533 	u32 ecr;
534 	u32 gsr;
535 	u8 res0[12];
536 	u32 pitar2;
537 	u8 res1[4];
538 	u32 pibar2;
539 	u32 piebar2;
540 	u32 piwar2;
541 	u8 res2[4];
542 	u32 pitar1;
543 	u8 res3[4];
544 	u32 pibar1;
545 	u32 piebar1;
546 	u32 piwar1;
547 	u8 res4[4];
548 	u32 pitar0;
549 	u8 res5[4];
550 	u32 pibar0;
551 	u8 res6[4];
552 	u32 piwar0;
553 	u8 res7[132];
554 } pcictrl83xx_t;
555 
556 /*
557  * USB
558  */
559 typedef struct usb83xx {
560 	u8 fixme[0x1000];
561 } usb83xx_t;
562 
563 /*
564  * TSEC
565  */
566 typedef struct tsec83xx {
567 	u8 fixme[0x1000];
568 } tsec83xx_t;
569 
570 /*
571  * Security
572  */
573 typedef struct security83xx {
574 	u8 fixme[0x10000];
575 } security83xx_t;
576 
577 /*
578  *  PCI Express
579  */
580 struct pex_inbound_window {
581 	u32 ar;
582 	u32 tar;
583 	u32 barl;
584 	u32 barh;
585 };
586 
587 struct pex_outbound_window {
588 	u32 ar;
589 	u32 bar;
590 	u32 tarl;
591 	u32 tarh;
592 };
593 
594 struct pex_csb_bridge {
595 	u32 pex_csb_ver;
596 	u32 pex_csb_cab;
597 	u32 pex_csb_ctrl;
598 	u8 res0[8];
599 	u32 pex_dms_dstmr;
600 	u8 res1[4];
601 	u32 pex_cbs_stat;
602 	u8 res2[0x20];
603 	u32 pex_csb_obctrl;
604 	u32 pex_csb_obstat;
605 	u8 res3[0x98];
606 	u32 pex_csb_ibctrl;
607 	u32 pex_csb_ibstat;
608 	u8 res4[0xb8];
609 	u32 pex_wdma_ctrl;
610 	u32 pex_wdma_addr;
611 	u32 pex_wdma_stat;
612 	u8 res5[0x94];
613 	u32 pex_rdma_ctrl;
614 	u32 pex_rdma_addr;
615 	u32 pex_rdma_stat;
616 	u8 res6[0xd4];
617 	u32 pex_ombcr;
618 	u32 pex_ombdr;
619 	u8 res7[0x38];
620 	u32 pex_imbcr;
621 	u32 pex_imbdr;
622 	u8 res8[0x38];
623 	u32 pex_int_enb;
624 	u32 pex_int_stat;
625 	u32 pex_int_apio_vec1;
626 	u32 pex_int_apio_vec2;
627 	u8 res9[0x10];
628 	u32 pex_int_ppio_vec1;
629 	u32 pex_int_ppio_vec2;
630 	u32 pex_int_wdma_vec1;
631 	u32 pex_int_wdma_vec2;
632 	u32 pex_int_rdma_vec1;
633 	u32 pex_int_rdma_vec2;
634 	u32 pex_int_misc_vec;
635 	u8 res10[4];
636 	u32 pex_int_axi_pio_enb;
637 	u32 pex_int_axi_wdma_enb;
638 	u32 pex_int_axi_rdma_enb;
639 	u32 pex_int_axi_misc_enb;
640 	u32 pex_int_axi_pio_stat;
641 	u32 pex_int_axi_wdma_stat;
642 	u32 pex_int_axi_rdma_stat;
643 	u32 pex_int_axi_misc_stat;
644 	u8 res11[0xa0];
645 	struct pex_outbound_window pex_outbound_win[4];
646 	u8 res12[0x100];
647 	u32 pex_epiwtar0;
648 	u32 pex_epiwtar1;
649 	u32 pex_epiwtar2;
650 	u32 pex_epiwtar3;
651 	u8 res13[0x70];
652 	struct pex_inbound_window pex_inbound_win[4];
653 };
654 
655 typedef struct pex83xx {
656 	u8 pex_cfg_header[0x404];
657 	u32 pex_ltssm_stat;
658 	u8 res0[0x30];
659 	u32 pex_ack_replay_timeout;
660 	u8 res1[4];
661 	u32 pex_gclk_ratio;
662 	u8 res2[0xc];
663 	u32 pex_pm_timer;
664 	u32 pex_pme_timeout;
665 	u8 res3[4];
666 	u32 pex_aspm_req_timer;
667 	u8 res4[0x18];
668 	u32 pex_ssvid_update;
669 	u8 res5[0x34];
670 	u32 pex_cfg_ready;
671 	u8 res6[0x24];
672 	u32 pex_bar_sizel;
673 	u8 res7[4];
674 	u32 pex_bar_sel;
675 	u8 res8[0x20];
676 	u32 pex_bar_pf;
677 	u8 res9[0x88];
678 	u32 pex_pme_to_ack_tor;
679 	u8 res10[0xc];
680 	u32 pex_ss_intr_mask;
681 	u8 res11[0x25c];
682 	struct pex_csb_bridge bridge;
683 	u8 res12[0x160];
684 } pex83xx_t;
685 
686 /*
687  * SATA
688  */
689 typedef struct sata83xx {
690 	u8 fixme[0x1000];
691 } sata83xx_t;
692 
693 /*
694  * eSDHC
695  */
696 typedef struct sdhc83xx {
697 	u8 fixme[0x1000];
698 } sdhc83xx_t;
699 
700 /*
701  * SerDes
702  */
703 typedef struct serdes83xx {
704 	u32 srdscr0;
705 	u32 srdscr1;
706 	u32 srdscr2;
707 	u32 srdscr3;
708 	u32 srdscr4;
709 	u8 res0[0xc];
710 	u32 srdsrstctl;
711 	u8 res1[0xdc];
712 } serdes83xx_t;
713 
714 /*
715  * On Chip ROM
716  */
717 typedef struct rom83xx {
718 #if defined(CONFIG_MPC8309)
719 	u8 mem[0x8000];
720 #else
721 	u8 mem[0x10000];
722 #endif
723 } rom83xx_t;
724 
725 /*
726  * TDM
727  */
728 typedef struct tdm83xx {
729 	u8 fixme[0x200];
730 } tdm83xx_t;
731 
732 /*
733  * TDM DMAC
734  */
735 typedef struct tdmdmac83xx {
736 	u8 fixme[0x2000];
737 } tdmdmac83xx_t;
738 
739 #if defined(CONFIG_MPC834x)
740 typedef struct immap {
741 	sysconf83xx_t		sysconf;	/* System configuration */
742 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
743 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
744 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
745 	gtm83xx_t		gtm[2];		/* Global Timers Module */
746 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
747 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
748 	reset83xx_t		reset;		/* Reset Module */
749 	clk83xx_t		clk;		/* System Clock Module */
750 	pmc83xx_t		pmc;		/* Power Management Control Module */
751 	gpio83xx_t		gpio[2];	/* General purpose I/O module */
752 	u8			res0[0x200];
753 	u8			dll_ddr[0x100];
754 	u8			dll_lbc[0x100];
755 	u8			res1[0xE00];
756 #if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
757 	ccsr_ddr_t		ddr;	/* DDR Memory Controller Memory */
758 #else
759 	ddr83xx_t		ddr;	/* DDR Memory Controller Memory */
760 #endif
761 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
762 	u8			res2[0x1300];
763 	duart83xx_t		duart[2];	/* DUART */
764 	u8			res3[0x900];
765 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
766 	u8			res4[0x1000];
767 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
768 	dma83xx_t		dma;		/* DMA */
769 	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
770 	ios83xx_t		ios;		/* Sequencer */
771 	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
772 	u8			res5[0x19900];
773 	usb83xx_t		usb[2];
774 	tsec83xx_t		tsec[2];
775 	u8			res6[0xA000];
776 	security83xx_t		security;
777 	u8			res7[0xC0000];
778 } immap_t;
779 
780 #ifdef CONFIG_HAS_FSL_MPH_USB
781 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x22000	/* use the MPH controller */
782 #else
783 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000	/* use the DR controller */
784 #endif
785 
786 #elif defined(CONFIG_MPC8313)
787 typedef struct immap {
788 	sysconf83xx_t		sysconf;	/* System configuration */
789 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
790 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
791 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
792 	gtm83xx_t		gtm[2];		/* Global Timers Module */
793 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
794 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
795 	reset83xx_t		reset;		/* Reset Module */
796 	clk83xx_t		clk;		/* System Clock Module */
797 	pmc83xx_t		pmc;		/* Power Management Control Module */
798 	gpio83xx_t		gpio[1];	/* General purpose I/O module */
799 	u8			res0[0x1300];
800 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
801 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
802 	u8			res1[0x1300];
803 	duart83xx_t		duart[2];	/* DUART */
804 	u8			res2[0x900];
805 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
806 	u8			res3[0x1000];
807 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
808 	dma83xx_t		dma;		/* DMA */
809 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
810 	u8			res4[0x80];
811 	ios83xx_t		ios;		/* Sequencer */
812 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
813 	u8			res5[0x1aa00];
814 	usb83xx_t		usb[1];
815 	tsec83xx_t		tsec[2];
816 	u8			res6[0xA000];
817 	security83xx_t		security;
818 	u8			res7[0xC0000];
819 } immap_t;
820 
821 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
822 typedef struct immap {
823 	sysconf83xx_t		sysconf;	/* System configuration */
824 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
825 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
826 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
827 	gtm83xx_t		gtm[2];		/* Global Timers Module */
828 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
829 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
830 	reset83xx_t		reset;		/* Reset Module */
831 	clk83xx_t		clk;		/* System Clock Module */
832 	pmc83xx_t		pmc;		/* Power Management Control Module */
833 	gpio83xx_t		gpio[1];	/* General purpose I/O module */
834 	u8			res0[0x1300];
835 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
836 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
837 	u8			res1[0x1300];
838 	duart83xx_t		duart[2];	/* DUART */
839 	u8			res2[0x900];
840 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
841 	u8			res3[0x1000];
842 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
843 	dma83xx_t		dma;		/* DMA */
844 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
845 	u8			res4[0x80];
846 	ios83xx_t		ios;		/* Sequencer */
847 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
848 	u8			res5[0xa00];
849 	pex83xx_t		pciexp[2];	/* PCI Express Controller */
850 	u8			res6[0xb000];
851 	tdm83xx_t		tdm;		/* TDM Controller */
852 	u8			res7[0x1e00];
853 	sata83xx_t		sata[2];	/* SATA Controller */
854 	u8			res8[0x9000];
855 	usb83xx_t		usb[1];		/* USB DR Controller */
856 	tsec83xx_t		tsec[2];
857 	u8			res9[0x6000];
858 	tdmdmac83xx_t		tdmdmac;	/* TDM DMAC */
859 	u8			res10[0x2000];
860 	security83xx_t		security;
861 	u8			res11[0xA3000];
862 	serdes83xx_t		serdes[1];	/* SerDes Registers */
863 	u8			res12[0x1CF00];
864 } immap_t;
865 
866 #elif defined(CONFIG_MPC837x)
867 typedef struct immap {
868 	sysconf83xx_t		sysconf;	/* System configuration */
869 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
870 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
871 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
872 	gtm83xx_t		gtm[2];		/* Global Timers Module */
873 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
874 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
875 	reset83xx_t		reset;		/* Reset Module */
876 	clk83xx_t		clk;		/* System Clock Module */
877 	pmc83xx_t		pmc;		/* Power Management Control Module */
878 	gpio83xx_t		gpio[2];	/* General purpose I/O module */
879 	u8			res0[0x1200];
880 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
881 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
882 	u8			res1[0x1300];
883 	duart83xx_t		duart[2];	/* DUART */
884 	u8			res2[0x900];
885 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
886 	u8			res3[0x1000];
887 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
888 	dma83xx_t		dma;		/* DMA */
889 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
890 	u8			res4[0x80];
891 	ios83xx_t		ios;		/* Sequencer */
892 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
893 	u8			res5[0xa00];
894 	pex83xx_t		pciexp[2];	/* PCI Express Controller */
895 	u8			res6[0xd000];
896 	sata83xx_t		sata[4];	/* SATA Controller */
897 	u8			res7[0x7000];
898 	usb83xx_t		usb[1];		/* USB DR Controller */
899 	tsec83xx_t		tsec[2];
900 	u8			res8[0x8000];
901 	sdhc83xx_t		sdhc;		/* SDHC Controller */
902 	u8			res9[0x1000];
903 	security83xx_t		security;
904 	u8			res10[0xA3000];
905 	serdes83xx_t		serdes[2];	/* SerDes Registers */
906 	u8			res11[0xCE00];
907 	rom83xx_t		rom;		/* On Chip ROM */
908 } immap_t;
909 
910 #elif defined(CONFIG_MPC8360)
911 typedef struct immap {
912 	sysconf83xx_t		sysconf;	/* System configuration */
913 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
914 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
915 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
916 	u8			res0[0x200];
917 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
918 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
919 	reset83xx_t		reset;		/* Reset Module */
920 	clk83xx_t		clk;		/* System Clock Module */
921 	pmc83xx_t		pmc;		/* Power Management Control Module */
922 	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
923 	u8			res1[0x300];
924 	u8			dll_ddr[0x100];
925 	u8			dll_lbc[0x100];
926 	u8			res2[0x200];
927 	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
928 	qesba83xx_t		qesba;		/* QE Secondary Bus Access Windows */
929 	u8			res3[0x400];
930 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
931 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
932 	u8			res4[0x1300];
933 	duart83xx_t		duart[2];	/* DUART */
934 	u8			res5[0x900];
935 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
936 	u8			res6[0x2000];
937 	dma83xx_t		dma;		/* DMA */
938 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
939 	u8			res7[128];
940 	ios83xx_t		ios;		/* Sequencer (IOS) */
941 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
942 	u8			res8[0x4A00];
943 	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
944 	u8			res9[0x22000];
945 	security83xx_t		security;
946 	u8			res10[0xC0000];
947 	u8			qe[0x100000];	/* QE block */
948 } immap_t;
949 
950 #elif defined(CONFIG_MPC832x)
951 typedef struct immap {
952 	sysconf83xx_t		sysconf;	/* System configuration */
953 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
954 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
955 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
956 	gtm83xx_t		gtm[2];		/* Global Timers Module */
957 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
958 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
959 	reset83xx_t		reset;		/* Reset Module */
960 	clk83xx_t		clk;		/* System Clock Module */
961 	pmc83xx_t		pmc;		/* Power Management Control Module */
962 	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
963 	u8			res0[0x300];
964 	u8			dll_ddr[0x100];
965 	u8			dll_lbc[0x100];
966 	u8			res1[0x200];
967 	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
968 	u8			res2[0x800];
969 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
970 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
971 	u8			res3[0x1300];
972 	duart83xx_t		duart[2];	/* DUART */
973 	u8			res4[0x900];
974 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
975 	u8			res5[0x2000];
976 	dma83xx_t		dma;		/* DMA */
977 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
978 	u8			res6[128];
979 	ios83xx_t		ios;		/* Sequencer (IOS) */
980 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
981 	u8			res7[0x27A00];
982 	security83xx_t		security;
983 	u8			res8[0xC0000];
984 	u8			qe[0x100000];	/* QE block */
985 } immap_t;
986 #elif defined(CONFIG_MPC8309)
987 typedef struct immap {
988 	sysconf83xx_t		sysconf;	/* System configuration */
989 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
990 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
991 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
992 	gtm83xx_t		gtm[2];		/* Global Timers Module */
993 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
994 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
995 	reset83xx_t		reset;		/* Reset Module */
996 	clk83xx_t		clk;		/* System Clock Module */
997 	pmc83xx_t		pmc;		/* Power Management Control Module */
998 	gpio83xx_t		gpio[2];	/* General purpose I/O module */
999 	u8			res0[0x500];	/* res0 1.25 KBytes added for 8309 */
1000 	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
1001 	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
1002 	u8			res1[0x800];
1003 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
1004 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
1005 	u8			res2[0x1300];
1006 	duart83xx_t		duart[2];	/* DUART */
1007 	u8			res3[0x200];
1008 	duart83xx_t		duart1[2];	/* DUART */
1009 	u8			res4[0x500];
1010 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
1011 	u8			res5[0x1000];
1012 	u8			spi[0x100];
1013 	u8			res6[0xf00];
1014 	dma83xx_t		dma;		/* DMA */
1015 	pciconf83xx_t		pci_conf[1];	/* PCI Configuration Registers */
1016 	u8			res7[0x80];
1017 	ios83xx_t		ios;		/* Sequencer (IOS) */
1018 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Control & Status Registers */
1019 	u8			res8[0x13A00];
1020 	u8			can1[0x1000];	/* Flexcan 1 */
1021 	u8			can2[0x1000];	/* Flexcan 2 */
1022 	u8			res9[0x5000];
1023 	usb83xx_t		usb;
1024 	u8			res10[0x5000];
1025 	u8			can3[0x1000];	/* Flexcan 3 */
1026 	u8			can4[0x1000];	/* Flexcan 4 */
1027 	u8			res11[0x1000];
1028 	u8			dma1[0x2000];	/* DMA */
1029 	sdhc83xx_t		sdhc;		/* SDHC Controller */
1030 	u8			res12[0xC1000];
1031 	rom83xx_t		rom;		/* On Chip ROM */
1032 	u8			res13[0x8000];
1033 	u8			qe[0x100000];	/* QE block */
1034 	u8			res14[0xE00000];/* Added for 8309 */
1035 } immap_t;
1036 #endif
1037 
1038 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
1039 #define CONFIG_SYS_MPC8xxx_DDR_ADDR \
1040 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
1041 #define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
1042 #define CONFIG_SYS_MPC83xx_DMA_ADDR \
1043 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
1044 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
1045 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
1046 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
1047 
1048 #ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
1049 #define CONFIG_SYS_MPC83xx_USB_OFFSET  0x23000
1050 #endif
1051 #define CONFIG_SYS_MPC83xx_USB_ADDR \
1052 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
1053 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
1054 
1055 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
1056 #define CONFIG_SYS_MDIO1_OFFSET		0x24000
1057 
1058 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
1059 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
1060 #endif				/* __IMMAP_83xx__ */
1061