1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2004-2011 Freescale Semiconductor, Inc.
4  *
5  * MPC83xx Internal Memory Map
6  *
7  * Contributors:
8  *	Dave Liu <daveliu@freescale.com>
9  *	Tanya Jiang <tanya.jiang@freescale.com>
10  *	Mandy Lavi <mandy.lavi@freescale.com>
11  *	Eran Liberty <liberty@freescale.com>
12  */
13 #ifndef __IMMAP_83xx__
14 #define __IMMAP_83xx__
15 
16 #include <fsl_immap.h>
17 #include <asm/types.h>
18 #include <asm/fsl_i2c.h>
19 #include <asm/mpc8xxx_spi.h>
20 #include <asm/fsl_lbc.h>
21 #include <asm/fsl_dma.h>
22 
23 /*
24  * Local Access Window
25  */
26 typedef struct law83xx {
27 	u32 bar;		/* LBIU local access window base address register */
28 	u32 ar;			/* LBIU local access window attribute register */
29 } law83xx_t;
30 
31 /*
32  * System configuration registers
33  */
34 typedef struct sysconf83xx {
35 	u32 immrbar;		/* Internal memory map base address register */
36 	u8 res0[0x04];
37 	u32 altcbar;		/* Alternate configuration base address register */
38 	u8 res1[0x14];
39 	law83xx_t lblaw[4];	/* LBIU local access window */
40 	u8 res2[0x20];
41 	law83xx_t pcilaw[2];	/* PCI local access window */
42 	u8 res3[0x10];
43 	law83xx_t pcielaw[2];	/* PCI Express local access window */
44 	u8 res4[0x10];
45 	law83xx_t ddrlaw[2];	/* DDR local access window */
46 	u8 res5[0x50];
47 	u32 sgprl;		/* System General Purpose Register Low */
48 	u32 sgprh;		/* System General Purpose Register High */
49 	u32 spridr;		/* System Part and Revision ID Register */
50 	u8 res6[0x04];
51 	u32 spcr;		/* System Priority Configuration Register */
52 	u32 sicrl;		/* System I/O Configuration Register Low */
53 	u32 sicrh;		/* System I/O Configuration Register High */
54 	u8 res7[0x04];
55 	u32 sidcr0;		/* System I/O Delay Configuration Register 0 */
56 	u32 sidcr1;		/* System I/O Delay Configuration Register 1 */
57 	u32 ddrcdr;		/* DDR Control Driver Register */
58 	u32 ddrdsr;		/* DDR Debug Status Register */
59 	u32 obir;		/* Output Buffer Impedance Register */
60 	u8 res8[0xC];
61 	u32 pecr1;		/* PCI Express control register 1 */
62 #if defined(CONFIG_MPC830x)
63 	u32 sdhccr;		/* eSDHC Control Registers for MPC830x */
64 #else
65 	u32 pecr2;		/* PCI Express control register 2 */
66 #endif
67 #if defined(CONFIG_MPC8309)
68 	u32 can_dbg_ctrl;
69 	u32 res9a;
70 	u32 gpr1;
71 	u8 res9b[0xAC];
72 #else
73 	u8 res9[0xB8];
74 #endif
75 } sysconf83xx_t;
76 
77 /*
78  * Watch Dog Timer (WDT) Registers
79  */
80 typedef struct wdt83xx {
81 	u8 res0[4];
82 	u32 swcrr;		/* System watchdog control register */
83 	u32 swcnr;		/* System watchdog count register */
84 	u8 res1[2];
85 	u16 swsrr;		/* System watchdog service register */
86 	u8 res2[0xF0];
87 } wdt83xx_t;
88 
89 /*
90  * RTC/PIT Module Registers
91  */
92 typedef struct rtclk83xx {
93 	u32 cnr;		/* control register */
94 	u32 ldr;		/* load register */
95 	u32 psr;		/* prescale register */
96 	u32 ctr;		/* counter value field register */
97 	u32 evr;		/* event register */
98 	u32 alr;		/* alarm register */
99 	u8 res0[0xE8];
100 } rtclk83xx_t;
101 
102 /*
103  * Global timer module
104  */
105 typedef struct gtm83xx {
106 	u8 cfr1;		/* Timer1/2 Configuration */
107 	u8 res0[3];
108 	u8 cfr2;		/* Timer3/4 Configuration */
109 	u8 res1[11];
110 	u16 mdr1;		/* Timer1 Mode Register */
111 	u16 mdr2;		/* Timer2 Mode Register */
112 	u16 rfr1;		/* Timer1 Reference Register */
113 	u16 rfr2;		/* Timer2 Reference Register */
114 	u16 cpr1;		/* Timer1 Capture Register */
115 	u16 cpr2;		/* Timer2 Capture Register */
116 	u16 cnr1;		/* Timer1 Counter Register */
117 	u16 cnr2;		/* Timer2 Counter Register */
118 	u16 mdr3;		/* Timer3 Mode Register */
119 	u16 mdr4;		/* Timer4 Mode Register */
120 	u16 rfr3;		/* Timer3 Reference Register */
121 	u16 rfr4;		/* Timer4 Reference Register */
122 	u16 cpr3;		/* Timer3 Capture Register */
123 	u16 cpr4;		/* Timer4 Capture Register */
124 	u16 cnr3;		/* Timer3 Counter Register */
125 	u16 cnr4;		/* Timer4 Counter Register */
126 	u16 evr1;		/* Timer1 Event Register */
127 	u16 evr2;		/* Timer2 Event Register */
128 	u16 evr3;		/* Timer3 Event Register */
129 	u16 evr4;		/* Timer4 Event Register */
130 	u16 psr1;		/* Timer1 Prescaler Register */
131 	u16 psr2;		/* Timer2 Prescaler Register */
132 	u16 psr3;		/* Timer3 Prescaler Register */
133 	u16 psr4;		/* Timer4 Prescaler Register */
134 	u8 res[0xC0];
135 } gtm83xx_t;
136 
137 /*
138  * Integrated Programmable Interrupt Controller
139  */
140 typedef struct ipic83xx {
141 	u32 sicfr;		/* System Global Interrupt Configuration Register */
142 	u32 sivcr;		/* System Global Interrupt Vector Register */
143 	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
144 	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
145 	u32 siprr_a;		/* System Internal Interrupt Group A Priority Register */
146 	u32 siprr_b;		/* System Internal Interrupt Group B Priority Register */
147 	u32 siprr_c;		/* System Internal Interrupt Group C Priority Register */
148 	u32 siprr_d;		/* System Internal Interrupt Group D Priority Register */
149 	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
150 	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
151 	u32 sicnr;		/* System Internal Interrupt Control Register */
152 	u32 sepnr;		/* System External Interrupt Pending Register */
153 	u32 smprr_a;		/* System Mixed Interrupt Group A Priority Register */
154 	u32 smprr_b;		/* System Mixed Interrupt Group B Priority Register */
155 	u32 semsr;		/* System External Interrupt Mask Register */
156 	u32 secnr;		/* System External Interrupt Control Register */
157 	u32 sersr;		/* System Error Status Register */
158 	u32 sermr;		/* System Error Mask Register */
159 	u32 sercr;		/* System Error Control Register */
160 	u32 sepcr;		/* System External Interrupt Polarity Control Register */
161 	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
162 	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
163 	u32 sefcr;		/* System External Interrupt Force Register */
164 	u32 serfr;		/* System Error Force Register */
165 	u32 scvcr;		/* System Critical Interrupt Vector Register */
166 	u32 smvcr;		/* System Management Interrupt Vector Register */
167 	u8 res[0x98];
168 } ipic83xx_t;
169 
170 /*
171  * System Arbiter Registers
172  */
173 typedef struct arbiter83xx {
174 	u32 acr;		/* Arbiter Configuration Register */
175 	u32 atr;		/* Arbiter Timers Register */
176 	u8 res[4];
177 	u32 aer;		/* Arbiter Event Register */
178 	u32 aidr;		/* Arbiter Interrupt Definition Register */
179 	u32 amr;		/* Arbiter Mask Register */
180 	u32 aeatr;		/* Arbiter Event Attributes Register */
181 	u32 aeadr;		/* Arbiter Event Address Register */
182 	u32 aerr;		/* Arbiter Event Response Register */
183 	u8 res1[0xDC];
184 } arbiter83xx_t;
185 
186 /*
187  * Reset Module
188  */
189 typedef struct reset83xx {
190 	u32 rcwl;		/* Reset Configuration Word Low Register */
191 	u32 rcwh;		/* Reset Configuration Word High Register */
192 	u8 res0[8];
193 	u32 rsr;		/* Reset Status Register */
194 	u32 rmr;		/* Reset Mode Register */
195 	u32 rpr;		/* Reset protection Register */
196 	u32 rcr;		/* Reset Control Register */
197 	u32 rcer;		/* Reset Control Enable Register */
198 	u8 res1[0xDC];
199 } reset83xx_t;
200 
201 /*
202  * Clock Module
203  */
204 typedef struct clk83xx {
205 	u32 spmr;		/* system PLL mode Register */
206 	u32 occr;		/* output clock control Register */
207 	u32 sccr;		/* system clock control Register */
208 	u8 res0[0xF4];
209 } clk83xx_t;
210 
211 /*
212  * Power Management Control Module
213  */
214 typedef struct pmc83xx {
215 	u32 pmccr;		/* PMC Configuration Register */
216 	u32 pmcer;		/* PMC Event Register */
217 	u32 pmcmr;		/* PMC Mask Register */
218 	u32 pmccr1;		/* PMC Configuration Register 1 */
219 	u32 pmccr2;		/* PMC Configuration Register 2 */
220 	u8 res0[0xEC];
221 } pmc83xx_t;
222 
223 /*
224  * General purpose I/O module
225  */
226 typedef struct gpio83xx {
227 	u32 dir;		/* direction register */
228 	u32 odr;		/* open drain register */
229 	u32 dat;		/* data register */
230 	u32 ier;		/* interrupt event register */
231 	u32 imr;		/* interrupt mask register */
232 	u32 icr;		/* external interrupt control register */
233 	u8 res0[0xE8];
234 } gpio83xx_t;
235 
236 /*
237  * QE Ports Interrupts Registers
238  */
239 typedef struct qepi83xx {
240 	u8 res0[0xC];
241 	u32 qepier;		/* QE Ports Interrupt Event Register */
242 	u32 qepimr;		/* QE Ports Interrupt Mask Register */
243 	u32 qepicr;		/* QE Ports Interrupt Control Register */
244 	u8 res1[0xE8];
245 } qepi83xx_t;
246 
247 /*
248  * QE Parallel I/O Ports
249  */
250 typedef struct gpio_n {
251 	u32 podr;		/* Open Drain Register */
252 	u32 pdat;		/* Data Register */
253 	u32 dir1;		/* direction register 1 */
254 	u32 dir2;		/* direction register 2 */
255 	u32 ppar1;		/* Pin Assignment Register 1 */
256 	u32 ppar2;		/* Pin Assignment Register 2 */
257 } gpio_n_t;
258 
259 typedef struct qegpio83xx {
260 	gpio_n_t ioport[0x7];
261 	u8 res0[0x358];
262 } qepio83xx_t;
263 
264 /*
265  * QE Secondary Bus Access Windows
266  */
267 typedef struct qesba83xx {
268 	u32 lbmcsar;		/* Local bus memory controller start address */
269 	u32 sdmcsar;		/* Secondary DDR memory controller start address */
270 	u8 res0[0x38];
271 	u32 lbmcear;		/* Local bus memory controller end address */
272 	u32 sdmcear;		/* Secondary DDR memory controller end address */
273 	u8 res1[0x38];
274 	u32 lbmcar;		/* Local bus memory controller attributes */
275 	u32 sdmcar;		/* Secondary DDR memory controller attributes */
276 	u8 res2[0x378];
277 } qesba83xx_t;
278 
279 /*
280  * DDR Memory Controller Memory Map for DDR1
281  * The structure of DDR2, or DDR3 is defined in fsl_immap.h
282  */
283 #if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
284 typedef struct ddr_cs_bnds {
285 	u32 csbnds;
286 	u8 res0[4];
287 } ddr_cs_bnds_t;
288 
289 typedef struct ddr83xx {
290 	ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
291 	u8 res0[0x60];
292 	u32 cs_config[4];	/* Chip Select x Configuration */
293 	u8 res1[0x70];
294 	u32 timing_cfg_3;	/* SDRAM Timing Configuration 3 */
295 	u32 timing_cfg_0;	/* SDRAM Timing Configuration 0 */
296 	u32 timing_cfg_1;	/* SDRAM Timing Configuration 1 */
297 	u32 timing_cfg_2;	/* SDRAM Timing Configuration 2 */
298 	u32 sdram_cfg;		/* SDRAM Control Configuration */
299 	u32 sdram_cfg2;		/* SDRAM Control Configuration 2 */
300 	u32 sdram_mode;		/* SDRAM Mode Configuration */
301 	u32 sdram_mode2;	/* SDRAM Mode Configuration 2 */
302 	u32 sdram_md_cntl;	/* SDRAM Mode Control */
303 	u32 sdram_interval;	/* SDRAM Interval Configuration */
304 	u32 ddr_data_init;	/* SDRAM Data Initialization */
305 	u8 res2[4];
306 	u32 sdram_clk_cntl;	/* SDRAM Clock Control */
307 	u8 res3[0x14];
308 	u32 ddr_init_addr;	/* DDR training initialization address */
309 	u32 ddr_init_ext_addr;	/* DDR training initialization extended address */
310 	u8 res4[0xAA8];
311 	u32 ddr_ip_rev1;	/* DDR IP block revision 1 */
312 	u32 ddr_ip_rev2;	/* DDR IP block revision 2 */
313 	u8 res5[0x200];
314 	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
315 	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
316 	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
317 	u8 res6[0x14];
318 	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
319 	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
320 	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
321 	u8 res7[0x14];
322 	u32 err_detect;		/* Memory Error Detect */
323 	u32 err_disable;	/* Memory Error Disable */
324 	u32 err_int_en;		/* Memory Error Interrupt Enable */
325 	u32 capture_attributes;	/* Memory Error Attributes Capture */
326 	u32 capture_address;	/* Memory Error Address Capture */
327 	u32 capture_ext_address;/* Memory Error Extended Address Capture */
328 	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
329 	u8 res8[0xA4];
330 	u32 debug_reg;
331 	u8 res9[0xFC];
332 } ddr83xx_t;
333 #endif
334 
335 /*
336  * DUART
337  */
338 typedef struct duart83xx {
339 	u8 urbr_ulcr_udlb;	/* combined register for URBR, UTHR and UDLB */
340 	u8 uier_udmb;		/* combined register for UIER and UDMB */
341 	u8 uiir_ufcr_uafr;	/* combined register for UIIR, UFCR and UAFR */
342 	u8 ulcr;		/* line control register */
343 	u8 umcr;		/* MODEM control register */
344 	u8 ulsr;		/* line status register */
345 	u8 umsr;		/* MODEM status register */
346 	u8 uscr;		/* scratch register */
347 	u8 res0[8];
348 	u8 udsr;		/* DMA status register */
349 	u8 res1[3];
350 	u8 res2[0xEC];
351 } duart83xx_t;
352 
353 /*
354  * DMA/Messaging Unit
355  */
356 typedef struct dma83xx {
357 	u32 res0[0xC];		/* 0x0-0x29 reseverd */
358 	u32 omisr;		/* 0x30 Outbound message interrupt status register */
359 	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
360 	u32 res1[0x6];		/* 0x38-0x49 reserved */
361 	u32 imr0;		/* 0x50 Inbound message register 0 */
362 	u32 imr1;		/* 0x54 Inbound message register 1 */
363 	u32 omr0;		/* 0x58 Outbound message register 0 */
364 	u32 omr1;		/* 0x5C Outbound message register 1 */
365 	u32 odr;		/* 0x60 Outbound doorbell register */
366 	u32 res2;		/* 0x64-0x67 reserved */
367 	u32 idr;		/* 0x68 Inbound doorbell register */
368 	u32 res3[0x5];		/* 0x6C-0x79 reserved */
369 	u32 imisr;		/* 0x80 Inbound message interrupt status register */
370 	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
371 	u32 res4[0x1E];		/* 0x88-0x99 reserved */
372 	struct fsl_dma dma[4];
373 } dma83xx_t;
374 
375 /*
376  * PCI Software Configuration Registers
377  */
378 typedef struct pciconf83xx {
379 	u32 config_address;
380 	u32 config_data;
381 	u32 int_ack;
382 	u8 res[116];
383 } pciconf83xx_t;
384 
385 /*
386  * PCI Outbound Translation Register
387  */
388 typedef struct pci_outbound_window {
389 	u32 potar;
390 	u8 res0[4];
391 	u32 pobar;
392 	u8 res1[4];
393 	u32 pocmr;
394 	u8 res2[4];
395 } pot83xx_t;
396 
397 /*
398  * Sequencer
399  */
400 typedef struct ios83xx {
401 	pot83xx_t pot[6];
402 	u8 res0[0x60];
403 	u32 pmcr;
404 	u8 res1[4];
405 	u32 dtcr;
406 	u8 res2[4];
407 } ios83xx_t;
408 
409 /*
410  * PCI Controller Control and Status Registers
411  */
412 typedef struct pcictrl83xx {
413 	u32 esr;
414 	u32 ecdr;
415 	u32 eer;
416 	u32 eatcr;
417 	u32 eacr;
418 	u32 eeacr;
419 	u32 edlcr;
420 	u32 edhcr;
421 	u32 gcr;
422 	u32 ecr;
423 	u32 gsr;
424 	u8 res0[12];
425 	u32 pitar2;
426 	u8 res1[4];
427 	u32 pibar2;
428 	u32 piebar2;
429 	u32 piwar2;
430 	u8 res2[4];
431 	u32 pitar1;
432 	u8 res3[4];
433 	u32 pibar1;
434 	u32 piebar1;
435 	u32 piwar1;
436 	u8 res4[4];
437 	u32 pitar0;
438 	u8 res5[4];
439 	u32 pibar0;
440 	u8 res6[4];
441 	u32 piwar0;
442 	u8 res7[132];
443 } pcictrl83xx_t;
444 
445 /*
446  * USB
447  */
448 typedef struct usb83xx {
449 	u8 fixme[0x1000];
450 } usb83xx_t;
451 
452 /*
453  * TSEC
454  */
455 typedef struct tsec83xx {
456 	u8 fixme[0x1000];
457 } tsec83xx_t;
458 
459 /*
460  * Security
461  */
462 typedef struct security83xx {
463 	u8 fixme[0x10000];
464 } security83xx_t;
465 
466 /*
467  *  PCI Express
468  */
469 struct pex_inbound_window {
470 	u32 ar;
471 	u32 tar;
472 	u32 barl;
473 	u32 barh;
474 };
475 
476 struct pex_outbound_window {
477 	u32 ar;
478 	u32 bar;
479 	u32 tarl;
480 	u32 tarh;
481 };
482 
483 struct pex_csb_bridge {
484 	u32 pex_csb_ver;
485 	u32 pex_csb_cab;
486 	u32 pex_csb_ctrl;
487 	u8 res0[8];
488 	u32 pex_dms_dstmr;
489 	u8 res1[4];
490 	u32 pex_cbs_stat;
491 	u8 res2[0x20];
492 	u32 pex_csb_obctrl;
493 	u32 pex_csb_obstat;
494 	u8 res3[0x98];
495 	u32 pex_csb_ibctrl;
496 	u32 pex_csb_ibstat;
497 	u8 res4[0xb8];
498 	u32 pex_wdma_ctrl;
499 	u32 pex_wdma_addr;
500 	u32 pex_wdma_stat;
501 	u8 res5[0x94];
502 	u32 pex_rdma_ctrl;
503 	u32 pex_rdma_addr;
504 	u32 pex_rdma_stat;
505 	u8 res6[0xd4];
506 	u32 pex_ombcr;
507 	u32 pex_ombdr;
508 	u8 res7[0x38];
509 	u32 pex_imbcr;
510 	u32 pex_imbdr;
511 	u8 res8[0x38];
512 	u32 pex_int_enb;
513 	u32 pex_int_stat;
514 	u32 pex_int_apio_vec1;
515 	u32 pex_int_apio_vec2;
516 	u8 res9[0x10];
517 	u32 pex_int_ppio_vec1;
518 	u32 pex_int_ppio_vec2;
519 	u32 pex_int_wdma_vec1;
520 	u32 pex_int_wdma_vec2;
521 	u32 pex_int_rdma_vec1;
522 	u32 pex_int_rdma_vec2;
523 	u32 pex_int_misc_vec;
524 	u8 res10[4];
525 	u32 pex_int_axi_pio_enb;
526 	u32 pex_int_axi_wdma_enb;
527 	u32 pex_int_axi_rdma_enb;
528 	u32 pex_int_axi_misc_enb;
529 	u32 pex_int_axi_pio_stat;
530 	u32 pex_int_axi_wdma_stat;
531 	u32 pex_int_axi_rdma_stat;
532 	u32 pex_int_axi_misc_stat;
533 	u8 res11[0xa0];
534 	struct pex_outbound_window pex_outbound_win[4];
535 	u8 res12[0x100];
536 	u32 pex_epiwtar0;
537 	u32 pex_epiwtar1;
538 	u32 pex_epiwtar2;
539 	u32 pex_epiwtar3;
540 	u8 res13[0x70];
541 	struct pex_inbound_window pex_inbound_win[4];
542 };
543 
544 typedef struct pex83xx {
545 	u8 pex_cfg_header[0x404];
546 	u32 pex_ltssm_stat;
547 	u8 res0[0x30];
548 	u32 pex_ack_replay_timeout;
549 	u8 res1[4];
550 	u32 pex_gclk_ratio;
551 	u8 res2[0xc];
552 	u32 pex_pm_timer;
553 	u32 pex_pme_timeout;
554 	u8 res3[4];
555 	u32 pex_aspm_req_timer;
556 	u8 res4[0x18];
557 	u32 pex_ssvid_update;
558 	u8 res5[0x34];
559 	u32 pex_cfg_ready;
560 	u8 res6[0x24];
561 	u32 pex_bar_sizel;
562 	u8 res7[4];
563 	u32 pex_bar_sel;
564 	u8 res8[0x20];
565 	u32 pex_bar_pf;
566 	u8 res9[0x88];
567 	u32 pex_pme_to_ack_tor;
568 	u8 res10[0xc];
569 	u32 pex_ss_intr_mask;
570 	u8 res11[0x25c];
571 	struct pex_csb_bridge bridge;
572 	u8 res12[0x160];
573 } pex83xx_t;
574 
575 /*
576  * SATA
577  */
578 typedef struct sata83xx {
579 	u8 fixme[0x1000];
580 } sata83xx_t;
581 
582 /*
583  * eSDHC
584  */
585 typedef struct sdhc83xx {
586 	u8 fixme[0x1000];
587 } sdhc83xx_t;
588 
589 /*
590  * SerDes
591  */
592 typedef struct serdes83xx {
593 	u32 srdscr0;
594 	u32 srdscr1;
595 	u32 srdscr2;
596 	u32 srdscr3;
597 	u32 srdscr4;
598 	u8 res0[0xc];
599 	u32 srdsrstctl;
600 	u8 res1[0xdc];
601 } serdes83xx_t;
602 
603 /*
604  * On Chip ROM
605  */
606 typedef struct rom83xx {
607 #if defined(CONFIG_MPC8309)
608 	u8 mem[0x8000];
609 #else
610 	u8 mem[0x10000];
611 #endif
612 } rom83xx_t;
613 
614 /*
615  * TDM
616  */
617 typedef struct tdm83xx {
618 	u8 fixme[0x200];
619 } tdm83xx_t;
620 
621 /*
622  * TDM DMAC
623  */
624 typedef struct tdmdmac83xx {
625 	u8 fixme[0x2000];
626 } tdmdmac83xx_t;
627 
628 #if defined(CONFIG_MPC834x)
629 typedef struct immap {
630 	sysconf83xx_t		sysconf;	/* System configuration */
631 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
632 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
633 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
634 	gtm83xx_t		gtm[2];		/* Global Timers Module */
635 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
636 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
637 	reset83xx_t		reset;		/* Reset Module */
638 	clk83xx_t		clk;		/* System Clock Module */
639 	pmc83xx_t		pmc;		/* Power Management Control Module */
640 	gpio83xx_t		gpio[2];	/* General purpose I/O module */
641 	u8			res0[0x200];
642 	u8			dll_ddr[0x100];
643 	u8			dll_lbc[0x100];
644 	u8			res1[0xE00];
645 #if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
646 	struct ccsr_ddr		ddr;	/* DDR Memory Controller Memory */
647 #else
648 	ddr83xx_t		ddr;	/* DDR Memory Controller Memory */
649 #endif
650 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
651 	u8			res2[0x1300];
652 	duart83xx_t		duart[2];	/* DUART */
653 	u8			res3[0x900];
654 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
655 	u8			res4[0x1000];
656 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
657 	dma83xx_t		dma;		/* DMA */
658 	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
659 	ios83xx_t		ios;		/* Sequencer */
660 	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
661 	u8			res5[0x19900];
662 	usb83xx_t		usb[2];
663 	tsec83xx_t		tsec[2];
664 	u8			res6[0xA000];
665 	security83xx_t		security;
666 	u8			res7[0xC0000];
667 } immap_t;
668 
669 #ifndef	CONFIG_MPC834x
670 #ifdef CONFIG_HAS_FSL_MPH_USB
671 #define CONFIG_SYS_MPC83xx_USB1_OFFSET  0x22000	/* use the MPH controller */
672 #define CONFIG_SYS_MPC83xx_USB2_OFFSET	0
673 #else
674 #define CONFIG_SYS_MPC83xx_USB1_OFFSET	0
675 #define CONFIG_SYS_MPC83xx_USB2_OFFSET  0x23000	/* use the DR controller */
676 #endif
677 #else
678 #define CONFIG_SYS_MPC83xx_USB1_OFFSET	0x22000
679 #define CONFIG_SYS_MPC83xx_USB2_OFFSET  0x23000
680 #endif
681 
682 #elif defined(CONFIG_MPC8313)
683 typedef struct immap {
684 	sysconf83xx_t		sysconf;	/* System configuration */
685 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
686 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
687 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
688 	gtm83xx_t		gtm[2];		/* Global Timers Module */
689 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
690 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
691 	reset83xx_t		reset;		/* Reset Module */
692 	clk83xx_t		clk;		/* System Clock Module */
693 	pmc83xx_t		pmc;		/* Power Management Control Module */
694 	gpio83xx_t		gpio[1];	/* General purpose I/O module */
695 	u8			res0[0x1300];
696 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
697 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
698 	u8			res1[0x1300];
699 	duart83xx_t		duart[2];	/* DUART */
700 	u8			res2[0x900];
701 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
702 	u8			res3[0x1000];
703 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
704 	dma83xx_t		dma;		/* DMA */
705 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
706 	u8			res4[0x80];
707 	ios83xx_t		ios;		/* Sequencer */
708 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
709 	u8			res5[0x1aa00];
710 	usb83xx_t		usb[1];
711 	tsec83xx_t		tsec[2];
712 	u8			res6[0xA000];
713 	security83xx_t		security;
714 	u8			res7[0xC0000];
715 } immap_t;
716 
717 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
718 typedef struct immap {
719 	sysconf83xx_t		sysconf;	/* System configuration */
720 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
721 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
722 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
723 	gtm83xx_t		gtm[2];		/* Global Timers Module */
724 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
725 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
726 	reset83xx_t		reset;		/* Reset Module */
727 	clk83xx_t		clk;		/* System Clock Module */
728 	pmc83xx_t		pmc;		/* Power Management Control Module */
729 	gpio83xx_t		gpio[1];	/* General purpose I/O module */
730 	u8			res0[0x1300];
731 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
732 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
733 	u8			res1[0x1300];
734 	duart83xx_t		duart[2];	/* DUART */
735 	u8			res2[0x900];
736 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
737 	u8			res3[0x1000];
738 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
739 	dma83xx_t		dma;		/* DMA */
740 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
741 	u8			res4[0x80];
742 	ios83xx_t		ios;		/* Sequencer */
743 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
744 	u8			res5[0xa00];
745 	pex83xx_t		pciexp[2];	/* PCI Express Controller */
746 	u8			res6[0xb000];
747 	tdm83xx_t		tdm;		/* TDM Controller */
748 	u8			res7[0x1e00];
749 	sata83xx_t		sata[2];	/* SATA Controller */
750 	u8			res8[0x9000];
751 	usb83xx_t		usb[1];		/* USB DR Controller */
752 	tsec83xx_t		tsec[2];
753 	u8			res9[0x6000];
754 	tdmdmac83xx_t		tdmdmac;	/* TDM DMAC */
755 	u8			res10[0x2000];
756 	security83xx_t		security;
757 	u8			res11[0xA3000];
758 	serdes83xx_t		serdes[1];	/* SerDes Registers */
759 	u8			res12[0x1CF00];
760 } immap_t;
761 
762 #elif defined(CONFIG_MPC837x)
763 typedef struct immap {
764 	sysconf83xx_t		sysconf;	/* System configuration */
765 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
766 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
767 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
768 	gtm83xx_t		gtm[2];		/* Global Timers Module */
769 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
770 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
771 	reset83xx_t		reset;		/* Reset Module */
772 	clk83xx_t		clk;		/* System Clock Module */
773 	pmc83xx_t		pmc;		/* Power Management Control Module */
774 	gpio83xx_t		gpio[2];	/* General purpose I/O module */
775 	u8			res0[0x1200];
776 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
777 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
778 	u8			res1[0x1300];
779 	duart83xx_t		duart[2];	/* DUART */
780 	u8			res2[0x900];
781 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
782 	u8			res3[0x1000];
783 	spi8xxx_t		spi;		/* Serial Peripheral Interface */
784 	dma83xx_t		dma;		/* DMA */
785 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
786 	u8			res4[0x80];
787 	ios83xx_t		ios;		/* Sequencer */
788 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
789 	u8			res5[0xa00];
790 	pex83xx_t		pciexp[2];	/* PCI Express Controller */
791 	u8			res6[0xd000];
792 	sata83xx_t		sata[4];	/* SATA Controller */
793 	u8			res7[0x7000];
794 	usb83xx_t		usb[1];		/* USB DR Controller */
795 	tsec83xx_t		tsec[2];
796 	u8			res8[0x8000];
797 	sdhc83xx_t		sdhc;		/* SDHC Controller */
798 	u8			res9[0x1000];
799 	security83xx_t		security;
800 	u8			res10[0xA3000];
801 	serdes83xx_t		serdes[2];	/* SerDes Registers */
802 	u8			res11[0xCE00];
803 	rom83xx_t		rom;		/* On Chip ROM */
804 } immap_t;
805 
806 #elif defined(CONFIG_MPC8360)
807 typedef struct immap {
808 	sysconf83xx_t		sysconf;	/* System configuration */
809 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
810 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
811 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
812 	u8			res0[0x200];
813 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
814 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
815 	reset83xx_t		reset;		/* Reset Module */
816 	clk83xx_t		clk;		/* System Clock Module */
817 	pmc83xx_t		pmc;		/* Power Management Control Module */
818 	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
819 	u8			res1[0x300];
820 	u8			dll_ddr[0x100];
821 	u8			dll_lbc[0x100];
822 	u8			res2[0x200];
823 	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
824 	qesba83xx_t		qesba;		/* QE Secondary Bus Access Windows */
825 	u8			res3[0x400];
826 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
827 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
828 	u8			res4[0x1300];
829 	duart83xx_t		duart[2];	/* DUART */
830 	u8			res5[0x900];
831 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
832 	u8			res6[0x2000];
833 	dma83xx_t		dma;		/* DMA */
834 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
835 	u8			res7[128];
836 	ios83xx_t		ios;		/* Sequencer (IOS) */
837 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
838 	u8			res8[0x4A00];
839 	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
840 	u8			res9[0x22000];
841 	security83xx_t		security;
842 	u8			res10[0xC0000];
843 	u8			qe[0x100000];	/* QE block */
844 } immap_t;
845 
846 #elif defined(CONFIG_MPC832x)
847 typedef struct immap {
848 	sysconf83xx_t		sysconf;	/* System configuration */
849 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
850 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
851 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
852 	gtm83xx_t		gtm[2];		/* Global Timers Module */
853 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
854 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
855 	reset83xx_t		reset;		/* Reset Module */
856 	clk83xx_t		clk;		/* System Clock Module */
857 	pmc83xx_t		pmc;		/* Power Management Control Module */
858 	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
859 	u8			res0[0x300];
860 	u8			dll_ddr[0x100];
861 	u8			dll_lbc[0x100];
862 	u8			res1[0x200];
863 	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
864 	u8			res2[0x800];
865 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
866 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
867 	u8			res3[0x1300];
868 	duart83xx_t		duart[2];	/* DUART */
869 	u8			res4[0x900];
870 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
871 	u8			res5[0x2000];
872 	dma83xx_t		dma;		/* DMA */
873 	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
874 	u8			res6[128];
875 	ios83xx_t		ios;		/* Sequencer (IOS) */
876 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
877 	u8			res7[0x27A00];
878 	security83xx_t		security;
879 	u8			res8[0xC0000];
880 	u8			qe[0x100000];	/* QE block */
881 } immap_t;
882 #elif defined(CONFIG_MPC8309)
883 typedef struct immap {
884 	sysconf83xx_t		sysconf;	/* System configuration */
885 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
886 	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
887 	rtclk83xx_t		pit;		/* Periodic Interval Timer */
888 	gtm83xx_t		gtm[2];		/* Global Timers Module */
889 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
890 	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
891 	reset83xx_t		reset;		/* Reset Module */
892 	clk83xx_t		clk;		/* System Clock Module */
893 	pmc83xx_t		pmc;		/* Power Management Control Module */
894 	gpio83xx_t		gpio[2];	/* General purpose I/O module */
895 	u8			res0[0x500];	/* res0 1.25 KBytes added for 8309 */
896 	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
897 	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
898 	u8			res1[0x800];
899 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
900 	fsl_i2c_t		i2c[2];		/* I2C Controllers */
901 	u8			res2[0x1300];
902 	duart83xx_t		duart[2];	/* DUART */
903 	u8			res3[0x200];
904 	duart83xx_t		duart1[2];	/* DUART */
905 	u8			res4[0x500];
906 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
907 	u8			res5[0x1000];
908 	u8			spi[0x100];
909 	u8			res6[0xf00];
910 	dma83xx_t		dma;		/* DMA */
911 	pciconf83xx_t		pci_conf[1];	/* PCI Configuration Registers */
912 	u8			res7[0x80];
913 	ios83xx_t		ios;		/* Sequencer (IOS) */
914 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Control & Status Registers */
915 	u8			res8[0x13A00];
916 	u8			can1[0x1000];	/* Flexcan 1 */
917 	u8			can2[0x1000];	/* Flexcan 2 */
918 	u8			res9[0x5000];
919 	usb83xx_t		usb;
920 	u8			res10[0x5000];
921 	u8			can3[0x1000];	/* Flexcan 3 */
922 	u8			can4[0x1000];	/* Flexcan 4 */
923 	u8			res11[0x1000];
924 	u8			dma1[0x2000];	/* DMA */
925 	sdhc83xx_t		sdhc;		/* SDHC Controller */
926 	u8			res12[0xC1000];
927 	rom83xx_t		rom;		/* On Chip ROM */
928 	u8			res13[0x8000];
929 	u8			qe[0x100000];	/* QE block */
930 	u8			res14[0xE00000];/* Added for 8309 */
931 } immap_t;
932 #endif
933 
934 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
935 #define CONFIG_SYS_FSL_DDR_ADDR \
936 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
937 #define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
938 #define CONFIG_SYS_MPC83xx_DMA_ADDR \
939 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
940 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
941 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
942 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
943 
944 #ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
945 #define CONFIG_SYS_MPC83xx_USB1_OFFSET  0x23000
946 #endif
947 #define CONFIG_SYS_MPC83xx_USB1_ADDR \
948 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
949 #if defined(CONFIG_MPC834x)
950 #define CONFIG_SYS_MPC83xx_USB2_ADDR \
951 			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
952 #endif
953 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
954 
955 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
956 #define CONFIG_SYS_MDIO1_OFFSET		0x24000
957 
958 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
959 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
960 #endif				/* __IMMAP_83xx__ */
961