1 /* 2 * Copyright 2004-2011 Freescale Semiconductor, Inc. 3 * 4 * MPC83xx Internal Memory Map 5 * 6 * Contributors: 7 * Dave Liu <daveliu@freescale.com> 8 * Tanya Jiang <tanya.jiang@freescale.com> 9 * Mandy Lavi <mandy.lavi@freescale.com> 10 * Eran Liberty <liberty@freescale.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 #ifndef __IMMAP_83xx__ 15 #define __IMMAP_83xx__ 16 17 #include <asm/types.h> 18 #include <asm/fsl_i2c.h> 19 #include <asm/mpc8xxx_spi.h> 20 #include <asm/fsl_lbc.h> 21 #include <asm/fsl_dma.h> 22 23 /* 24 * Local Access Window 25 */ 26 typedef struct law83xx { 27 u32 bar; /* LBIU local access window base address register */ 28 u32 ar; /* LBIU local access window attribute register */ 29 } law83xx_t; 30 31 /* 32 * System configuration registers 33 */ 34 typedef struct sysconf83xx { 35 u32 immrbar; /* Internal memory map base address register */ 36 u8 res0[0x04]; 37 u32 altcbar; /* Alternate configuration base address register */ 38 u8 res1[0x14]; 39 law83xx_t lblaw[4]; /* LBIU local access window */ 40 u8 res2[0x20]; 41 law83xx_t pcilaw[2]; /* PCI local access window */ 42 u8 res3[0x10]; 43 law83xx_t pcielaw[2]; /* PCI Express local access window */ 44 u8 res4[0x10]; 45 law83xx_t ddrlaw[2]; /* DDR local access window */ 46 u8 res5[0x50]; 47 u32 sgprl; /* System General Purpose Register Low */ 48 u32 sgprh; /* System General Purpose Register High */ 49 u32 spridr; /* System Part and Revision ID Register */ 50 u8 res6[0x04]; 51 u32 spcr; /* System Priority Configuration Register */ 52 u32 sicrl; /* System I/O Configuration Register Low */ 53 u32 sicrh; /* System I/O Configuration Register High */ 54 u8 res7[0x04]; 55 u32 sidcr0; /* System I/O Delay Configuration Register 0 */ 56 u32 sidcr1; /* System I/O Delay Configuration Register 1 */ 57 u32 ddrcdr; /* DDR Control Driver Register */ 58 u32 ddrdsr; /* DDR Debug Status Register */ 59 u32 obir; /* Output Buffer Impedance Register */ 60 u8 res8[0xC]; 61 u32 pecr1; /* PCI Express control register 1 */ 62 #if defined(CONFIG_MPC830x) 63 u32 sdhccr; /* eSDHC Control Registers for MPC830x */ 64 #else 65 u32 pecr2; /* PCI Express control register 2 */ 66 #endif 67 #if defined(CONFIG_MPC8309) 68 u32 can_dbg_ctrl; 69 u32 res9a; 70 u32 gpr1; 71 u8 res9b[0xAC]; 72 #else 73 u8 res9[0xB8]; 74 #endif 75 } sysconf83xx_t; 76 77 /* 78 * Watch Dog Timer (WDT) Registers 79 */ 80 typedef struct wdt83xx { 81 u8 res0[4]; 82 u32 swcrr; /* System watchdog control register */ 83 u32 swcnr; /* System watchdog count register */ 84 u8 res1[2]; 85 u16 swsrr; /* System watchdog service register */ 86 u8 res2[0xF0]; 87 } wdt83xx_t; 88 89 /* 90 * RTC/PIT Module Registers 91 */ 92 typedef struct rtclk83xx { 93 u32 cnr; /* control register */ 94 u32 ldr; /* load register */ 95 u32 psr; /* prescale register */ 96 u32 ctr; /* counter value field register */ 97 u32 evr; /* event register */ 98 u32 alr; /* alarm register */ 99 u8 res0[0xE8]; 100 } rtclk83xx_t; 101 102 /* 103 * Global timer module 104 */ 105 typedef struct gtm83xx { 106 u8 cfr1; /* Timer1/2 Configuration */ 107 u8 res0[3]; 108 u8 cfr2; /* Timer3/4 Configuration */ 109 u8 res1[11]; 110 u16 mdr1; /* Timer1 Mode Register */ 111 u16 mdr2; /* Timer2 Mode Register */ 112 u16 rfr1; /* Timer1 Reference Register */ 113 u16 rfr2; /* Timer2 Reference Register */ 114 u16 cpr1; /* Timer1 Capture Register */ 115 u16 cpr2; /* Timer2 Capture Register */ 116 u16 cnr1; /* Timer1 Counter Register */ 117 u16 cnr2; /* Timer2 Counter Register */ 118 u16 mdr3; /* Timer3 Mode Register */ 119 u16 mdr4; /* Timer4 Mode Register */ 120 u16 rfr3; /* Timer3 Reference Register */ 121 u16 rfr4; /* Timer4 Reference Register */ 122 u16 cpr3; /* Timer3 Capture Register */ 123 u16 cpr4; /* Timer4 Capture Register */ 124 u16 cnr3; /* Timer3 Counter Register */ 125 u16 cnr4; /* Timer4 Counter Register */ 126 u16 evr1; /* Timer1 Event Register */ 127 u16 evr2; /* Timer2 Event Register */ 128 u16 evr3; /* Timer3 Event Register */ 129 u16 evr4; /* Timer4 Event Register */ 130 u16 psr1; /* Timer1 Prescaler Register */ 131 u16 psr2; /* Timer2 Prescaler Register */ 132 u16 psr3; /* Timer3 Prescaler Register */ 133 u16 psr4; /* Timer4 Prescaler Register */ 134 u8 res[0xC0]; 135 } gtm83xx_t; 136 137 /* 138 * Integrated Programmable Interrupt Controller 139 */ 140 typedef struct ipic83xx { 141 u32 sicfr; /* System Global Interrupt Configuration Register */ 142 u32 sivcr; /* System Global Interrupt Vector Register */ 143 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ 144 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ 145 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ 146 u32 siprr_b; /* System Internal Interrupt Group B Priority Register */ 147 u32 siprr_c; /* System Internal Interrupt Group C Priority Register */ 148 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ 149 u32 simsr_h; /* System Internal Interrupt Mask Register - High */ 150 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ 151 u32 sicnr; /* System Internal Interrupt Control Register */ 152 u32 sepnr; /* System External Interrupt Pending Register */ 153 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ 154 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ 155 u32 semsr; /* System External Interrupt Mask Register */ 156 u32 secnr; /* System External Interrupt Control Register */ 157 u32 sersr; /* System Error Status Register */ 158 u32 sermr; /* System Error Mask Register */ 159 u32 sercr; /* System Error Control Register */ 160 u32 sepcr; /* System External Interrupt Polarity Control Register */ 161 u32 sifcr_h; /* System Internal Interrupt Force Register - High */ 162 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ 163 u32 sefcr; /* System External Interrupt Force Register */ 164 u32 serfr; /* System Error Force Register */ 165 u32 scvcr; /* System Critical Interrupt Vector Register */ 166 u32 smvcr; /* System Management Interrupt Vector Register */ 167 u8 res[0x98]; 168 } ipic83xx_t; 169 170 /* 171 * System Arbiter Registers 172 */ 173 typedef struct arbiter83xx { 174 u32 acr; /* Arbiter Configuration Register */ 175 u32 atr; /* Arbiter Timers Register */ 176 u8 res[4]; 177 u32 aer; /* Arbiter Event Register */ 178 u32 aidr; /* Arbiter Interrupt Definition Register */ 179 u32 amr; /* Arbiter Mask Register */ 180 u32 aeatr; /* Arbiter Event Attributes Register */ 181 u32 aeadr; /* Arbiter Event Address Register */ 182 u32 aerr; /* Arbiter Event Response Register */ 183 u8 res1[0xDC]; 184 } arbiter83xx_t; 185 186 /* 187 * Reset Module 188 */ 189 typedef struct reset83xx { 190 u32 rcwl; /* Reset Configuration Word Low Register */ 191 u32 rcwh; /* Reset Configuration Word High Register */ 192 u8 res0[8]; 193 u32 rsr; /* Reset Status Register */ 194 u32 rmr; /* Reset Mode Register */ 195 u32 rpr; /* Reset protection Register */ 196 u32 rcr; /* Reset Control Register */ 197 u32 rcer; /* Reset Control Enable Register */ 198 u8 res1[0xDC]; 199 } reset83xx_t; 200 201 /* 202 * Clock Module 203 */ 204 typedef struct clk83xx { 205 u32 spmr; /* system PLL mode Register */ 206 u32 occr; /* output clock control Register */ 207 u32 sccr; /* system clock control Register */ 208 u8 res0[0xF4]; 209 } clk83xx_t; 210 211 /* 212 * Power Management Control Module 213 */ 214 typedef struct pmc83xx { 215 u32 pmccr; /* PMC Configuration Register */ 216 u32 pmcer; /* PMC Event Register */ 217 u32 pmcmr; /* PMC Mask Register */ 218 u32 pmccr1; /* PMC Configuration Register 1 */ 219 u32 pmccr2; /* PMC Configuration Register 2 */ 220 u8 res0[0xEC]; 221 } pmc83xx_t; 222 223 /* 224 * General purpose I/O module 225 */ 226 typedef struct gpio83xx { 227 u32 dir; /* direction register */ 228 u32 odr; /* open drain register */ 229 u32 dat; /* data register */ 230 u32 ier; /* interrupt event register */ 231 u32 imr; /* interrupt mask register */ 232 u32 icr; /* external interrupt control register */ 233 u8 res0[0xE8]; 234 } gpio83xx_t; 235 236 /* 237 * QE Ports Interrupts Registers 238 */ 239 typedef struct qepi83xx { 240 u8 res0[0xC]; 241 u32 qepier; /* QE Ports Interrupt Event Register */ 242 u32 qepimr; /* QE Ports Interrupt Mask Register */ 243 u32 qepicr; /* QE Ports Interrupt Control Register */ 244 u8 res1[0xE8]; 245 } qepi83xx_t; 246 247 /* 248 * QE Parallel I/O Ports 249 */ 250 typedef struct gpio_n { 251 u32 podr; /* Open Drain Register */ 252 u32 pdat; /* Data Register */ 253 u32 dir1; /* direction register 1 */ 254 u32 dir2; /* direction register 2 */ 255 u32 ppar1; /* Pin Assignment Register 1 */ 256 u32 ppar2; /* Pin Assignment Register 2 */ 257 } gpio_n_t; 258 259 typedef struct qegpio83xx { 260 gpio_n_t ioport[0x7]; 261 u8 res0[0x358]; 262 } qepio83xx_t; 263 264 /* 265 * QE Secondary Bus Access Windows 266 */ 267 typedef struct qesba83xx { 268 u32 lbmcsar; /* Local bus memory controller start address */ 269 u32 sdmcsar; /* Secondary DDR memory controller start address */ 270 u8 res0[0x38]; 271 u32 lbmcear; /* Local bus memory controller end address */ 272 u32 sdmcear; /* Secondary DDR memory controller end address */ 273 u8 res1[0x38]; 274 u32 lbmcar; /* Local bus memory controller attributes */ 275 u32 sdmcar; /* Secondary DDR memory controller attributes */ 276 u8 res2[0x378]; 277 } qesba83xx_t; 278 279 /* 280 * DDR Memory Controller Memory Map 281 */ 282 #if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) 283 typedef struct ccsr_ddr { 284 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ 285 u8 res1[4]; 286 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ 287 u8 res2[4]; 288 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ 289 u8 res3[4]; 290 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ 291 u8 res4[100]; 292 u32 cs0_config; /* Chip Select Configuration */ 293 u32 cs1_config; /* Chip Select Configuration */ 294 u32 cs2_config; /* Chip Select Configuration */ 295 u32 cs3_config; /* Chip Select Configuration */ 296 u8 res4a[48]; 297 u32 cs0_config_2; /* Chip Select Configuration 2 */ 298 u32 cs1_config_2; /* Chip Select Configuration 2 */ 299 u32 cs2_config_2; /* Chip Select Configuration 2 */ 300 u32 cs3_config_2; /* Chip Select Configuration 2 */ 301 u8 res5[48]; 302 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 303 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 304 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 305 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 306 u32 sdram_cfg; /* SDRAM Control Configuration */ 307 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ 308 u32 sdram_mode; /* SDRAM Mode Configuration */ 309 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ 310 u32 sdram_md_cntl; /* SDRAM Mode Control */ 311 u32 sdram_interval; /* SDRAM Interval Configuration */ 312 u32 sdram_data_init; /* SDRAM Data initialization */ 313 u8 res6[4]; 314 u32 sdram_clk_cntl; /* SDRAM Clock Control */ 315 u8 res7[20]; 316 u32 init_addr; /* training init addr */ 317 u32 init_ext_addr; /* training init extended addr */ 318 u8 res8_1[16]; 319 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ 320 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ 321 u8 reg8_1a[8]; 322 u32 ddr_zq_cntl; /* ZQ calibration control*/ 323 u32 ddr_wrlvl_cntl; /* write leveling control*/ 324 u8 reg8_1aa[4]; 325 u32 ddr_sr_cntr; /* self refresh counter */ 326 u32 ddr_sdram_rcw_1; /* Control Words 1 */ 327 u32 ddr_sdram_rcw_2; /* Control Words 2 */ 328 u8 reg_1ab[8]; 329 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ 330 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ 331 u8 res8_1b[104]; 332 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ 333 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ 334 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ 335 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ 336 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ 337 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ 338 u8 res8_1ba[0x908]; 339 u32 ddr_dsr1; /* Debug Status 1 */ 340 u32 ddr_dsr2; /* Debug Status 2 */ 341 u32 ddr_cdr1; /* Control Driver 1 */ 342 u32 ddr_cdr2; /* Control Driver 2 */ 343 u8 res8_1c[200]; 344 u32 ip_rev1; /* IP Block Revision 1 */ 345 u32 ip_rev2; /* IP Block Revision 2 */ 346 u32 eor; /* Enhanced Optimization Register */ 347 u8 res8_2[252]; 348 u32 mtcr; /* Memory Test Control Register */ 349 u8 res8_3[28]; 350 u32 mtp1; /* Memory Test Pattern 1 */ 351 u32 mtp2; /* Memory Test Pattern 2 */ 352 u32 mtp3; /* Memory Test Pattern 3 */ 353 u32 mtp4; /* Memory Test Pattern 4 */ 354 u32 mtp5; /* Memory Test Pattern 5 */ 355 u32 mtp6; /* Memory Test Pattern 6 */ 356 u32 mtp7; /* Memory Test Pattern 7 */ 357 u32 mtp8; /* Memory Test Pattern 8 */ 358 u32 mtp9; /* Memory Test Pattern 9 */ 359 u32 mtp10; /* Memory Test Pattern 10 */ 360 u8 res8_4[184]; 361 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ 362 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ 363 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ 364 u8 res9[20]; 365 u32 capture_data_hi; /* Data Path Read Capture High */ 366 u32 capture_data_lo; /* Data Path Read Capture Low */ 367 u32 capture_ecc; /* Data Path Read Capture ECC */ 368 u8 res10[20]; 369 u32 err_detect; /* Error Detect */ 370 u32 err_disable; /* Error Disable */ 371 u32 err_int_en; 372 u32 capture_attributes; /* Error Attrs Capture */ 373 u32 capture_address; /* Error Addr Capture */ 374 u32 capture_ext_address; /* Error Extended Addr Capture */ 375 u32 err_sbe; /* Single-Bit ECC Error Management */ 376 u8 res11[164]; 377 u32 debug[32]; /* debug_1 to debug_32 */ 378 u8 res12[128]; 379 } ccsr_ddr_t; 380 #else 381 typedef struct ddr_cs_bnds { 382 u32 csbnds; 383 u8 res0[4]; 384 } ddr_cs_bnds_t; 385 386 typedef struct ddr83xx { 387 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ 388 u8 res0[0x60]; 389 u32 cs_config[4]; /* Chip Select x Configuration */ 390 u8 res1[0x70]; 391 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 392 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 393 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 394 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 395 u32 sdram_cfg; /* SDRAM Control Configuration */ 396 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ 397 u32 sdram_mode; /* SDRAM Mode Configuration */ 398 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ 399 u32 sdram_md_cntl; /* SDRAM Mode Control */ 400 u32 sdram_interval; /* SDRAM Interval Configuration */ 401 u32 ddr_data_init; /* SDRAM Data Initialization */ 402 u8 res2[4]; 403 u32 sdram_clk_cntl; /* SDRAM Clock Control */ 404 u8 res3[0x14]; 405 u32 ddr_init_addr; /* DDR training initialization address */ 406 u32 ddr_init_ext_addr; /* DDR training initialization extended address */ 407 u8 res4[0xAA8]; 408 u32 ddr_ip_rev1; /* DDR IP block revision 1 */ 409 u32 ddr_ip_rev2; /* DDR IP block revision 2 */ 410 u8 res5[0x200]; 411 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ 412 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ 413 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ 414 u8 res6[0x14]; 415 u32 capture_data_hi; /* Memory Data Path Read Capture High */ 416 u32 capture_data_lo; /* Memory Data Path Read Capture Low */ 417 u32 capture_ecc; /* Memory Data Path Read Capture ECC */ 418 u8 res7[0x14]; 419 u32 err_detect; /* Memory Error Detect */ 420 u32 err_disable; /* Memory Error Disable */ 421 u32 err_int_en; /* Memory Error Interrupt Enable */ 422 u32 capture_attributes; /* Memory Error Attributes Capture */ 423 u32 capture_address; /* Memory Error Address Capture */ 424 u32 capture_ext_address;/* Memory Error Extended Address Capture */ 425 u32 err_sbe; /* Memory Single-Bit ECC Error Management */ 426 u8 res8[0xA4]; 427 u32 debug_reg; 428 u8 res9[0xFC]; 429 } ddr83xx_t; 430 #endif 431 432 /* 433 * DUART 434 */ 435 typedef struct duart83xx { 436 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ 437 u8 uier_udmb; /* combined register for UIER and UDMB */ 438 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ 439 u8 ulcr; /* line control register */ 440 u8 umcr; /* MODEM control register */ 441 u8 ulsr; /* line status register */ 442 u8 umsr; /* MODEM status register */ 443 u8 uscr; /* scratch register */ 444 u8 res0[8]; 445 u8 udsr; /* DMA status register */ 446 u8 res1[3]; 447 u8 res2[0xEC]; 448 } duart83xx_t; 449 450 /* 451 * DMA/Messaging Unit 452 */ 453 typedef struct dma83xx { 454 u32 res0[0xC]; /* 0x0-0x29 reseverd */ 455 u32 omisr; /* 0x30 Outbound message interrupt status register */ 456 u32 omimr; /* 0x34 Outbound message interrupt mask register */ 457 u32 res1[0x6]; /* 0x38-0x49 reserved */ 458 u32 imr0; /* 0x50 Inbound message register 0 */ 459 u32 imr1; /* 0x54 Inbound message register 1 */ 460 u32 omr0; /* 0x58 Outbound message register 0 */ 461 u32 omr1; /* 0x5C Outbound message register 1 */ 462 u32 odr; /* 0x60 Outbound doorbell register */ 463 u32 res2; /* 0x64-0x67 reserved */ 464 u32 idr; /* 0x68 Inbound doorbell register */ 465 u32 res3[0x5]; /* 0x6C-0x79 reserved */ 466 u32 imisr; /* 0x80 Inbound message interrupt status register */ 467 u32 imimr; /* 0x84 Inbound message interrupt mask register */ 468 u32 res4[0x1E]; /* 0x88-0x99 reserved */ 469 struct fsl_dma dma[4]; 470 } dma83xx_t; 471 472 /* 473 * PCI Software Configuration Registers 474 */ 475 typedef struct pciconf83xx { 476 u32 config_address; 477 u32 config_data; 478 u32 int_ack; 479 u8 res[116]; 480 } pciconf83xx_t; 481 482 /* 483 * PCI Outbound Translation Register 484 */ 485 typedef struct pci_outbound_window { 486 u32 potar; 487 u8 res0[4]; 488 u32 pobar; 489 u8 res1[4]; 490 u32 pocmr; 491 u8 res2[4]; 492 } pot83xx_t; 493 494 /* 495 * Sequencer 496 */ 497 typedef struct ios83xx { 498 pot83xx_t pot[6]; 499 u8 res0[0x60]; 500 u32 pmcr; 501 u8 res1[4]; 502 u32 dtcr; 503 u8 res2[4]; 504 } ios83xx_t; 505 506 /* 507 * PCI Controller Control and Status Registers 508 */ 509 typedef struct pcictrl83xx { 510 u32 esr; 511 u32 ecdr; 512 u32 eer; 513 u32 eatcr; 514 u32 eacr; 515 u32 eeacr; 516 u32 edlcr; 517 u32 edhcr; 518 u32 gcr; 519 u32 ecr; 520 u32 gsr; 521 u8 res0[12]; 522 u32 pitar2; 523 u8 res1[4]; 524 u32 pibar2; 525 u32 piebar2; 526 u32 piwar2; 527 u8 res2[4]; 528 u32 pitar1; 529 u8 res3[4]; 530 u32 pibar1; 531 u32 piebar1; 532 u32 piwar1; 533 u8 res4[4]; 534 u32 pitar0; 535 u8 res5[4]; 536 u32 pibar0; 537 u8 res6[4]; 538 u32 piwar0; 539 u8 res7[132]; 540 } pcictrl83xx_t; 541 542 /* 543 * USB 544 */ 545 typedef struct usb83xx { 546 u8 fixme[0x1000]; 547 } usb83xx_t; 548 549 /* 550 * TSEC 551 */ 552 typedef struct tsec83xx { 553 u8 fixme[0x1000]; 554 } tsec83xx_t; 555 556 /* 557 * Security 558 */ 559 typedef struct security83xx { 560 u8 fixme[0x10000]; 561 } security83xx_t; 562 563 /* 564 * PCI Express 565 */ 566 struct pex_inbound_window { 567 u32 ar; 568 u32 tar; 569 u32 barl; 570 u32 barh; 571 }; 572 573 struct pex_outbound_window { 574 u32 ar; 575 u32 bar; 576 u32 tarl; 577 u32 tarh; 578 }; 579 580 struct pex_csb_bridge { 581 u32 pex_csb_ver; 582 u32 pex_csb_cab; 583 u32 pex_csb_ctrl; 584 u8 res0[8]; 585 u32 pex_dms_dstmr; 586 u8 res1[4]; 587 u32 pex_cbs_stat; 588 u8 res2[0x20]; 589 u32 pex_csb_obctrl; 590 u32 pex_csb_obstat; 591 u8 res3[0x98]; 592 u32 pex_csb_ibctrl; 593 u32 pex_csb_ibstat; 594 u8 res4[0xb8]; 595 u32 pex_wdma_ctrl; 596 u32 pex_wdma_addr; 597 u32 pex_wdma_stat; 598 u8 res5[0x94]; 599 u32 pex_rdma_ctrl; 600 u32 pex_rdma_addr; 601 u32 pex_rdma_stat; 602 u8 res6[0xd4]; 603 u32 pex_ombcr; 604 u32 pex_ombdr; 605 u8 res7[0x38]; 606 u32 pex_imbcr; 607 u32 pex_imbdr; 608 u8 res8[0x38]; 609 u32 pex_int_enb; 610 u32 pex_int_stat; 611 u32 pex_int_apio_vec1; 612 u32 pex_int_apio_vec2; 613 u8 res9[0x10]; 614 u32 pex_int_ppio_vec1; 615 u32 pex_int_ppio_vec2; 616 u32 pex_int_wdma_vec1; 617 u32 pex_int_wdma_vec2; 618 u32 pex_int_rdma_vec1; 619 u32 pex_int_rdma_vec2; 620 u32 pex_int_misc_vec; 621 u8 res10[4]; 622 u32 pex_int_axi_pio_enb; 623 u32 pex_int_axi_wdma_enb; 624 u32 pex_int_axi_rdma_enb; 625 u32 pex_int_axi_misc_enb; 626 u32 pex_int_axi_pio_stat; 627 u32 pex_int_axi_wdma_stat; 628 u32 pex_int_axi_rdma_stat; 629 u32 pex_int_axi_misc_stat; 630 u8 res11[0xa0]; 631 struct pex_outbound_window pex_outbound_win[4]; 632 u8 res12[0x100]; 633 u32 pex_epiwtar0; 634 u32 pex_epiwtar1; 635 u32 pex_epiwtar2; 636 u32 pex_epiwtar3; 637 u8 res13[0x70]; 638 struct pex_inbound_window pex_inbound_win[4]; 639 }; 640 641 typedef struct pex83xx { 642 u8 pex_cfg_header[0x404]; 643 u32 pex_ltssm_stat; 644 u8 res0[0x30]; 645 u32 pex_ack_replay_timeout; 646 u8 res1[4]; 647 u32 pex_gclk_ratio; 648 u8 res2[0xc]; 649 u32 pex_pm_timer; 650 u32 pex_pme_timeout; 651 u8 res3[4]; 652 u32 pex_aspm_req_timer; 653 u8 res4[0x18]; 654 u32 pex_ssvid_update; 655 u8 res5[0x34]; 656 u32 pex_cfg_ready; 657 u8 res6[0x24]; 658 u32 pex_bar_sizel; 659 u8 res7[4]; 660 u32 pex_bar_sel; 661 u8 res8[0x20]; 662 u32 pex_bar_pf; 663 u8 res9[0x88]; 664 u32 pex_pme_to_ack_tor; 665 u8 res10[0xc]; 666 u32 pex_ss_intr_mask; 667 u8 res11[0x25c]; 668 struct pex_csb_bridge bridge; 669 u8 res12[0x160]; 670 } pex83xx_t; 671 672 /* 673 * SATA 674 */ 675 typedef struct sata83xx { 676 u8 fixme[0x1000]; 677 } sata83xx_t; 678 679 /* 680 * eSDHC 681 */ 682 typedef struct sdhc83xx { 683 u8 fixme[0x1000]; 684 } sdhc83xx_t; 685 686 /* 687 * SerDes 688 */ 689 typedef struct serdes83xx { 690 u32 srdscr0; 691 u32 srdscr1; 692 u32 srdscr2; 693 u32 srdscr3; 694 u32 srdscr4; 695 u8 res0[0xc]; 696 u32 srdsrstctl; 697 u8 res1[0xdc]; 698 } serdes83xx_t; 699 700 /* 701 * On Chip ROM 702 */ 703 typedef struct rom83xx { 704 #if defined(CONFIG_MPC8309) 705 u8 mem[0x8000]; 706 #else 707 u8 mem[0x10000]; 708 #endif 709 } rom83xx_t; 710 711 /* 712 * TDM 713 */ 714 typedef struct tdm83xx { 715 u8 fixme[0x200]; 716 } tdm83xx_t; 717 718 /* 719 * TDM DMAC 720 */ 721 typedef struct tdmdmac83xx { 722 u8 fixme[0x2000]; 723 } tdmdmac83xx_t; 724 725 #if defined(CONFIG_MPC834x) 726 typedef struct immap { 727 sysconf83xx_t sysconf; /* System configuration */ 728 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 729 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 730 rtclk83xx_t pit; /* Periodic Interval Timer */ 731 gtm83xx_t gtm[2]; /* Global Timers Module */ 732 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 733 arbiter83xx_t arbiter; /* System Arbiter Registers */ 734 reset83xx_t reset; /* Reset Module */ 735 clk83xx_t clk; /* System Clock Module */ 736 pmc83xx_t pmc; /* Power Management Control Module */ 737 gpio83xx_t gpio[2]; /* General purpose I/O module */ 738 u8 res0[0x200]; 739 u8 dll_ddr[0x100]; 740 u8 dll_lbc[0x100]; 741 u8 res1[0xE00]; 742 #if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) 743 ccsr_ddr_t ddr; /* DDR Memory Controller Memory */ 744 #else 745 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 746 #endif 747 fsl_i2c_t i2c[2]; /* I2C Controllers */ 748 u8 res2[0x1300]; 749 duart83xx_t duart[2]; /* DUART */ 750 u8 res3[0x900]; 751 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 752 u8 res4[0x1000]; 753 spi8xxx_t spi; /* Serial Peripheral Interface */ 754 dma83xx_t dma; /* DMA */ 755 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ 756 ios83xx_t ios; /* Sequencer */ 757 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ 758 u8 res5[0x19900]; 759 usb83xx_t usb[2]; 760 tsec83xx_t tsec[2]; 761 u8 res6[0xA000]; 762 security83xx_t security; 763 u8 res7[0xC0000]; 764 } immap_t; 765 766 #ifdef CONFIG_HAS_FSL_MPH_USB 767 #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */ 768 #else 769 #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */ 770 #endif 771 772 #elif defined(CONFIG_MPC8313) 773 typedef struct immap { 774 sysconf83xx_t sysconf; /* System configuration */ 775 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 776 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 777 rtclk83xx_t pit; /* Periodic Interval Timer */ 778 gtm83xx_t gtm[2]; /* Global Timers Module */ 779 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 780 arbiter83xx_t arbiter; /* System Arbiter Registers */ 781 reset83xx_t reset; /* Reset Module */ 782 clk83xx_t clk; /* System Clock Module */ 783 pmc83xx_t pmc; /* Power Management Control Module */ 784 gpio83xx_t gpio[1]; /* General purpose I/O module */ 785 u8 res0[0x1300]; 786 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 787 fsl_i2c_t i2c[2]; /* I2C Controllers */ 788 u8 res1[0x1300]; 789 duart83xx_t duart[2]; /* DUART */ 790 u8 res2[0x900]; 791 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 792 u8 res3[0x1000]; 793 spi8xxx_t spi; /* Serial Peripheral Interface */ 794 dma83xx_t dma; /* DMA */ 795 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 796 u8 res4[0x80]; 797 ios83xx_t ios; /* Sequencer */ 798 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 799 u8 res5[0x1aa00]; 800 usb83xx_t usb[1]; 801 tsec83xx_t tsec[2]; 802 u8 res6[0xA000]; 803 security83xx_t security; 804 u8 res7[0xC0000]; 805 } immap_t; 806 807 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 808 typedef struct immap { 809 sysconf83xx_t sysconf; /* System configuration */ 810 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 811 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 812 rtclk83xx_t pit; /* Periodic Interval Timer */ 813 gtm83xx_t gtm[2]; /* Global Timers Module */ 814 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 815 arbiter83xx_t arbiter; /* System Arbiter Registers */ 816 reset83xx_t reset; /* Reset Module */ 817 clk83xx_t clk; /* System Clock Module */ 818 pmc83xx_t pmc; /* Power Management Control Module */ 819 gpio83xx_t gpio[1]; /* General purpose I/O module */ 820 u8 res0[0x1300]; 821 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 822 fsl_i2c_t i2c[2]; /* I2C Controllers */ 823 u8 res1[0x1300]; 824 duart83xx_t duart[2]; /* DUART */ 825 u8 res2[0x900]; 826 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 827 u8 res3[0x1000]; 828 spi8xxx_t spi; /* Serial Peripheral Interface */ 829 dma83xx_t dma; /* DMA */ 830 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 831 u8 res4[0x80]; 832 ios83xx_t ios; /* Sequencer */ 833 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 834 u8 res5[0xa00]; 835 pex83xx_t pciexp[2]; /* PCI Express Controller */ 836 u8 res6[0xb000]; 837 tdm83xx_t tdm; /* TDM Controller */ 838 u8 res7[0x1e00]; 839 sata83xx_t sata[2]; /* SATA Controller */ 840 u8 res8[0x9000]; 841 usb83xx_t usb[1]; /* USB DR Controller */ 842 tsec83xx_t tsec[2]; 843 u8 res9[0x6000]; 844 tdmdmac83xx_t tdmdmac; /* TDM DMAC */ 845 u8 res10[0x2000]; 846 security83xx_t security; 847 u8 res11[0xA3000]; 848 serdes83xx_t serdes[1]; /* SerDes Registers */ 849 u8 res12[0x1CF00]; 850 } immap_t; 851 852 #elif defined(CONFIG_MPC837x) 853 typedef struct immap { 854 sysconf83xx_t sysconf; /* System configuration */ 855 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 856 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 857 rtclk83xx_t pit; /* Periodic Interval Timer */ 858 gtm83xx_t gtm[2]; /* Global Timers Module */ 859 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 860 arbiter83xx_t arbiter; /* System Arbiter Registers */ 861 reset83xx_t reset; /* Reset Module */ 862 clk83xx_t clk; /* System Clock Module */ 863 pmc83xx_t pmc; /* Power Management Control Module */ 864 gpio83xx_t gpio[2]; /* General purpose I/O module */ 865 u8 res0[0x1200]; 866 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 867 fsl_i2c_t i2c[2]; /* I2C Controllers */ 868 u8 res1[0x1300]; 869 duart83xx_t duart[2]; /* DUART */ 870 u8 res2[0x900]; 871 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 872 u8 res3[0x1000]; 873 spi8xxx_t spi; /* Serial Peripheral Interface */ 874 dma83xx_t dma; /* DMA */ 875 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 876 u8 res4[0x80]; 877 ios83xx_t ios; /* Sequencer */ 878 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 879 u8 res5[0xa00]; 880 pex83xx_t pciexp[2]; /* PCI Express Controller */ 881 u8 res6[0xd000]; 882 sata83xx_t sata[4]; /* SATA Controller */ 883 u8 res7[0x7000]; 884 usb83xx_t usb[1]; /* USB DR Controller */ 885 tsec83xx_t tsec[2]; 886 u8 res8[0x8000]; 887 sdhc83xx_t sdhc; /* SDHC Controller */ 888 u8 res9[0x1000]; 889 security83xx_t security; 890 u8 res10[0xA3000]; 891 serdes83xx_t serdes[2]; /* SerDes Registers */ 892 u8 res11[0xCE00]; 893 rom83xx_t rom; /* On Chip ROM */ 894 } immap_t; 895 896 #elif defined(CONFIG_MPC8360) 897 typedef struct immap { 898 sysconf83xx_t sysconf; /* System configuration */ 899 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 900 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 901 rtclk83xx_t pit; /* Periodic Interval Timer */ 902 u8 res0[0x200]; 903 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 904 arbiter83xx_t arbiter; /* System Arbiter Registers */ 905 reset83xx_t reset; /* Reset Module */ 906 clk83xx_t clk; /* System Clock Module */ 907 pmc83xx_t pmc; /* Power Management Control Module */ 908 qepi83xx_t qepi; /* QE Ports Interrupts Registers */ 909 u8 res1[0x300]; 910 u8 dll_ddr[0x100]; 911 u8 dll_lbc[0x100]; 912 u8 res2[0x200]; 913 qepio83xx_t qepio; /* QE Parallel I/O ports */ 914 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ 915 u8 res3[0x400]; 916 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 917 fsl_i2c_t i2c[2]; /* I2C Controllers */ 918 u8 res4[0x1300]; 919 duart83xx_t duart[2]; /* DUART */ 920 u8 res5[0x900]; 921 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 922 u8 res6[0x2000]; 923 dma83xx_t dma; /* DMA */ 924 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 925 u8 res7[128]; 926 ios83xx_t ios; /* Sequencer (IOS) */ 927 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 928 u8 res8[0x4A00]; 929 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ 930 u8 res9[0x22000]; 931 security83xx_t security; 932 u8 res10[0xC0000]; 933 u8 qe[0x100000]; /* QE block */ 934 } immap_t; 935 936 #elif defined(CONFIG_MPC832x) 937 typedef struct immap { 938 sysconf83xx_t sysconf; /* System configuration */ 939 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 940 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 941 rtclk83xx_t pit; /* Periodic Interval Timer */ 942 gtm83xx_t gtm[2]; /* Global Timers Module */ 943 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 944 arbiter83xx_t arbiter; /* System Arbiter Registers */ 945 reset83xx_t reset; /* Reset Module */ 946 clk83xx_t clk; /* System Clock Module */ 947 pmc83xx_t pmc; /* Power Management Control Module */ 948 qepi83xx_t qepi; /* QE Ports Interrupts Registers */ 949 u8 res0[0x300]; 950 u8 dll_ddr[0x100]; 951 u8 dll_lbc[0x100]; 952 u8 res1[0x200]; 953 qepio83xx_t qepio; /* QE Parallel I/O ports */ 954 u8 res2[0x800]; 955 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 956 fsl_i2c_t i2c[2]; /* I2C Controllers */ 957 u8 res3[0x1300]; 958 duart83xx_t duart[2]; /* DUART */ 959 u8 res4[0x900]; 960 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 961 u8 res5[0x2000]; 962 dma83xx_t dma; /* DMA */ 963 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 964 u8 res6[128]; 965 ios83xx_t ios; /* Sequencer (IOS) */ 966 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 967 u8 res7[0x27A00]; 968 security83xx_t security; 969 u8 res8[0xC0000]; 970 u8 qe[0x100000]; /* QE block */ 971 } immap_t; 972 #elif defined(CONFIG_MPC8309) 973 typedef struct immap { 974 sysconf83xx_t sysconf; /* System configuration */ 975 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 976 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 977 rtclk83xx_t pit; /* Periodic Interval Timer */ 978 gtm83xx_t gtm[2]; /* Global Timers Module */ 979 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 980 arbiter83xx_t arbiter; /* System Arbiter Registers */ 981 reset83xx_t reset; /* Reset Module */ 982 clk83xx_t clk; /* System Clock Module */ 983 pmc83xx_t pmc; /* Power Management Control Module */ 984 gpio83xx_t gpio[2]; /* General purpose I/O module */ 985 u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */ 986 qepi83xx_t qepi; /* QE Ports Interrupts Registers */ 987 qepio83xx_t qepio; /* QE Parallel I/O ports */ 988 u8 res1[0x800]; 989 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 990 fsl_i2c_t i2c[2]; /* I2C Controllers */ 991 u8 res2[0x1300]; 992 duart83xx_t duart[2]; /* DUART */ 993 u8 res3[0x200]; 994 duart83xx_t duart1[2]; /* DUART */ 995 u8 res4[0x500]; 996 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ 997 u8 res5[0x1000]; 998 u8 spi[0x100]; 999 u8 res6[0xf00]; 1000 dma83xx_t dma; /* DMA */ 1001 pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */ 1002 u8 res7[0x80]; 1003 ios83xx_t ios; /* Sequencer (IOS) */ 1004 pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */ 1005 u8 res8[0x13A00]; 1006 u8 can1[0x1000]; /* Flexcan 1 */ 1007 u8 can2[0x1000]; /* Flexcan 2 */ 1008 u8 res9[0x5000]; 1009 usb83xx_t usb; 1010 u8 res10[0x5000]; 1011 u8 can3[0x1000]; /* Flexcan 3 */ 1012 u8 can4[0x1000]; /* Flexcan 4 */ 1013 u8 res11[0x1000]; 1014 u8 dma1[0x2000]; /* DMA */ 1015 sdhc83xx_t sdhc; /* SDHC Controller */ 1016 u8 res12[0xC1000]; 1017 rom83xx_t rom; /* On Chip ROM */ 1018 u8 res13[0x8000]; 1019 u8 qe[0x100000]; /* QE block */ 1020 u8 res14[0xE00000];/* Added for 8309 */ 1021 } immap_t; 1022 #endif 1023 1024 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) 1025 #define CONFIG_SYS_MPC8xxx_DDR_ADDR \ 1026 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) 1027 #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) 1028 #define CONFIG_SYS_MPC83xx_DMA_ADDR \ 1029 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET) 1030 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) 1031 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ 1032 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) 1033 1034 #ifndef CONFIG_SYS_MPC83xx_USB_OFFSET 1035 #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 1036 #endif 1037 #define CONFIG_SYS_MPC83xx_USB_ADDR \ 1038 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) 1039 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) 1040 1041 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 1042 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 1043 1044 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 1045 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 1046 #endif /* __IMMAP_83xx__ */ 1047