1 /*
2  * Copyright 2010 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17  * MA 02111-1307 USA
18  */
19 
20 #ifndef __FSL_SERDES_H
21 #define __FSL_SERDES_H
22 
23 #include <config.h>
24 
25 enum srds_prtcl {
26 	NONE = 0,
27 	PCIE1,
28 	PCIE2,
29 	PCIE3,
30 	PCIE4,
31 	SATA1,
32 	SATA2,
33 	SRIO1,
34 	SRIO2,
35 	SGMII_FM1_DTSEC1,
36 	SGMII_FM1_DTSEC2,
37 	SGMII_FM1_DTSEC3,
38 	SGMII_FM1_DTSEC4,
39 	SGMII_FM1_DTSEC5,
40 	SGMII_FM1_DTSEC6,
41 	SGMII_FM1_DTSEC9,
42 	SGMII_FM1_DTSEC10,
43 	SGMII_FM2_DTSEC1,
44 	SGMII_FM2_DTSEC2,
45 	SGMII_FM2_DTSEC3,
46 	SGMII_FM2_DTSEC4,
47 	SGMII_FM2_DTSEC5,
48 	SGMII_FM2_DTSEC6,
49 	SGMII_FM2_DTSEC9,
50 	SGMII_FM2_DTSEC10,
51 	SGMII_TSEC1,
52 	SGMII_TSEC2,
53 	SGMII_TSEC3,
54 	SGMII_TSEC4,
55 	XAUI_FM1,
56 	XAUI_FM2,
57 	AURORA,
58 	CPRI1,
59 	CPRI2,
60 	CPRI3,
61 	CPRI4,
62 	CPRI5,
63 	CPRI6,
64 	CPRI7,
65 	CPRI8,
66 	XAUI_FM1_MAC9,
67 	XAUI_FM1_MAC10,
68 	XAUI_FM2_MAC9,
69 	XAUI_FM2_MAC10,
70 	HIGIG_FM1_MAC9,
71 	HIGIG_FM1_MAC10,
72 	HIGIG_FM2_MAC9,
73 	HIGIG_FM2_MAC10,
74 	QSGMII_FM1_A,		/* A indicates MACs 1-4 */
75 	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
76 	QSGMII_FM2_A,
77 	QSGMII_FM2_B,
78 	XFI_FM1_MAC9,
79 	XFI_FM1_MAC10,
80 	XFI_FM2_MAC9,
81 	XFI_FM2_MAC10,
82 	INTERLAKEN,
83 	SGMII_SW1_DTSEC1,	/* SW indicates on L2 switch */
84 	SGMII_SW1_DTSEC2,
85 	SGMII_SW1_DTSEC3,
86 	SGMII_SW1_DTSEC4,
87 	SGMII_SW1_DTSEC5,
88 	SGMII_SW1_DTSEC6,
89 	QSGMII_SW1_A,		/* SW indicates on L2 swtich */
90 	QSGMII_SW1_B,
91 };
92 
93 enum srds {
94 	FSL_SRDS_1  = 0,
95 	FSL_SRDS_2  = 1,
96 	FSL_SRDS_3  = 2,
97 	FSL_SRDS_4  = 3,
98 };
99 
100 int is_serdes_configured(enum srds_prtcl device);
101 void fsl_serdes_init(void);
102 
103 #ifdef CONFIG_FSL_CORENET
104 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
105 int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
106 #else
107 int serdes_get_first_lane(enum srds_prtcl device);
108 #endif
109 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
110 void serdes_reset_rx(enum srds_prtcl device);
111 #endif
112 #endif
113 
114 #endif /* __FSL_SERDES_H */
115