1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __FSL_SECURE_BOOT_H
8 #define __FSL_SECURE_BOOT_H
9 #include <asm/config_mpc85xx.h>
10 
11 #ifdef CONFIG_SECURE_BOOT
12 #define CONFIG_CMD_ESBC_VALIDATE
13 #define CONFIG_FSL_SEC_MON
14 #define CONFIG_SHA_PROG_HW_ACCEL
15 #define CONFIG_DM
16 #define CONFIG_RSA
17 #define CONFIG_RSA_FREESCALE_EXP
18 #ifndef CONFIG_FSL_CAAM
19 #define CONFIG_FSL_CAAM
20 #endif
21 #endif
22 
23 #ifdef CONFIG_SECURE_BOOT
24 #if defined(CONFIG_FSL_CORENET)
25 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
26 #elif defined(CONFIG_BSC9132QDS)
27 #define CONFIG_SYS_PBI_FLASH_BASE		0xc8000000
28 #elif defined(CONFIG_C29XPCIE)
29 #define CONFIG_SYS_PBI_FLASH_BASE		0xcc000000
30 #else
31 #define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
32 #endif
33 #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
34 
35 #if defined(CONFIG_B4860QDS) || \
36 	defined(CONFIG_T4240QDS) || \
37 	defined(CONFIG_T2080QDS) || \
38 	defined(CONFIG_T2080RDB) || \
39 	defined(CONFIG_T1040QDS) || \
40 	defined(CONFIG_T104xRDB) || \
41 	defined(CONFIG_PPC_T1023) || \
42 	defined(CONFIG_PPC_T1024)
43 #define CONFIG_SYS_CPC_REINIT_F
44 #define CONFIG_KEY_REVOCATION
45 #undef CONFIG_SYS_INIT_L3_ADDR
46 #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
47 #endif
48 
49 #if defined(CONFIG_C29XPCIE)
50 #define CONFIG_KEY_REVOCATION
51 #endif
52 
53 #if defined(CONFIG_PPC_P3041)	||	\
54 	defined(CONFIG_PPC_P4080) ||	\
55 	defined(CONFIG_PPC_P5020) ||	\
56 	defined(CONFIG_PPC_P5040) ||	\
57 	defined(CONFIG_PPC_P2041)
58 	#define	CONFIG_FSL_TRUST_ARCH_v1
59 #endif
60 
61 #if defined(CONFIG_FSL_CORENET)
62 /* The key used for verification of next level images
63  * is picked up from an Extension Table which has
64  * been verified by the ISBC (Internal Secure boot Code)
65  * in boot ROM of the SoC
66  */
67 #define CONFIG_FSL_ISBC_KEY_EXT
68 #endif
69 
70 #ifndef CONFIG_FIT_SIGNATURE
71 /* The bootscript header address is different for B4860 because the NOR
72  * mapping is different on B4 due to reduced NOR size.
73  */
74 #if defined(CONFIG_B4860QDS)
75 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
76 #elif defined(CONFIG_FSL_CORENET)
77 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
78 #elif defined(CONFIG_BSC9132QDS)
79 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
80 #elif defined(CONFIG_C29XPCIE)
81 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
82 #else
83 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
84 #endif
85 
86 #include <config_fsl_secboot.h>
87 #endif
88 
89 #endif
90 #endif
91