1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __FSL_SECURE_BOOT_H
8 #define __FSL_SECURE_BOOT_H
9 #include <asm/config_mpc85xx.h>
10 
11 #ifdef CONFIG_SECURE_BOOT
12 
13 #ifndef CONFIG_FIT_SIGNATURE
14 #define CONFIG_CHAIN_OF_TRUST
15 #endif
16 
17 #if defined(CONFIG_FSL_CORENET)
18 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
19 #elif defined(CONFIG_BSC9132QDS)
20 #define CONFIG_SYS_PBI_FLASH_BASE		0xc8000000
21 #elif defined(CONFIG_C29XPCIE)
22 #define CONFIG_SYS_PBI_FLASH_BASE		0xcc000000
23 #else
24 #define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
25 #endif
26 #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
27 
28 #if defined(CONFIG_B4860QDS) || \
29 	defined(CONFIG_T4240QDS) || \
30 	defined(CONFIG_T2080QDS) || \
31 	defined(CONFIG_T2080RDB) || \
32 	defined(CONFIG_T1040QDS) || \
33 	defined(CONFIG_T104xD4QDS) || \
34 	defined(CONFIG_T104xRDB) || \
35 	defined(CONFIG_T104xD4RDB) || \
36 	defined(CONFIG_PPC_T1023) || \
37 	defined(CONFIG_PPC_T1024)
38 #ifndef CONFIG_SYS_RAMBOOT
39 #define CONFIG_SYS_CPC_REINIT_F
40 #endif
41 #define CONFIG_KEY_REVOCATION
42 #undef CONFIG_SYS_INIT_L3_ADDR
43 #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
44 #endif
45 
46 #if defined(CONFIG_RAMBOOT_PBL)
47 #undef CONFIG_SYS_INIT_L3_ADDR
48 #ifdef CONFIG_SYS_INIT_L3_VADDR
49 #define CONFIG_SYS_INIT_L3_ADDR	\
50 			(CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
51 					0xbff00000
52 #else
53 #define CONFIG_SYS_INIT_L3_ADDR		0xbff00000
54 #endif
55 #endif
56 
57 #if defined(CONFIG_C29XPCIE)
58 #define CONFIG_KEY_REVOCATION
59 #endif
60 
61 #if defined(CONFIG_PPC_P3041)	||	\
62 	defined(CONFIG_PPC_P4080) ||	\
63 	defined(CONFIG_PPC_P5020) ||	\
64 	defined(CONFIG_PPC_P5040) ||	\
65 	defined(CONFIG_PPC_P2041)
66 	#define	CONFIG_FSL_TRUST_ARCH_v1
67 #endif
68 
69 #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
70 /* The key used for verification of next level images
71  * is picked up from an Extension Table which has
72  * been verified by the ISBC (Internal Secure boot Code)
73  * in boot ROM of the SoC.
74  * The feature is only applicable in case of NOR boot and is
75  * not applicable in case of RAMBOOT (NAND, SD, SPI).
76  */
77 #define CONFIG_FSL_ISBC_KEY_EXT
78 #endif
79 #endif /* #ifdef CONFIG_SECURE_BOOT */
80 
81 #ifdef CONFIG_CHAIN_OF_TRUST
82 #ifdef CONFIG_SPL_BUILD
83 /*
84  * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
85  * due to space crunch on CPC and thus malloc will not work.
86  */
87 #define CONFIG_SPL_PPAACT_ADDR		0x2e000000
88 #define CONFIG_SPL_SPAACT_ADDR		0x2f000000
89 #define CONFIG_SPL_JR0_LIODN_S		454
90 #define CONFIG_SPL_JR0_LIODN_NS		458
91 /*
92  * Define the key hash for U-Boot here if public/private key pair used to
93  * sign U-boot are different from the SRK hash put in the fuse
94  * Example of defining KEY_HASH is
95  * #define CONFIG_SPL_UBOOT_KEY_HASH \
96  *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
97  * else leave it defined as NULL
98  */
99 
100 #define CONFIG_SPL_UBOOT_KEY_HASH	NULL
101 #endif /* ifdef CONFIG_SPL_BUILD */
102 
103 #define CONFIG_CMD_ESBC_VALIDATE
104 #define CONFIG_CMD_BLOB
105 #define CONFIG_FSL_SEC_MON
106 #define CONFIG_SHA_PROG_HW_ACCEL
107 #define CONFIG_RSA_FREESCALE_EXP
108 
109 #ifndef CONFIG_FSL_CAAM
110 #define CONFIG_FSL_CAAM
111 #endif
112 
113 #ifndef CONFIG_SPL_BUILD
114 /*
115  * fsl_setenv_chain_of_trust() must be called from
116  * board_late_init()
117  */
118 #ifndef CONFIG_BOARD_LATE_INIT
119 #define CONFIG_BOARD_LATE_INIT
120 #endif
121 
122 /* If Boot Script is not on NOR and is required to be copied on RAM */
123 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
124 #define CONFIG_BS_HDR_ADDR_RAM		0x00010000
125 #define CONFIG_BS_HDR_ADDR_DEVICE	0x00800000
126 #define CONFIG_BS_HDR_SIZE		0x00002000
127 #define CONFIG_BS_ADDR_RAM		0x00012000
128 #define CONFIG_BS_ADDR_DEVICE		0x00802000
129 #define CONFIG_BS_SIZE			0x00001000
130 
131 #define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
132 #else
133 
134 /* The bootscript header address is different for B4860 because the NOR
135  * mapping is different on B4 due to reduced NOR size.
136  */
137 #if defined(CONFIG_B4860QDS)
138 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
139 #elif defined(CONFIG_FSL_CORENET)
140 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
141 #elif defined(CONFIG_BSC9132QDS)
142 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
143 #elif defined(CONFIG_C29XPCIE)
144 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
145 #else
146 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
147 #endif
148 
149 #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
150 
151 #include <config_fsl_chain_trust.h>
152 #endif /* #ifndef CONFIG_SPL_BUILD */
153 #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
154 #endif
155