1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __FSL_SECURE_BOOT_H
8 #define __FSL_SECURE_BOOT_H
9 #include <asm/config_mpc85xx.h>
10 
11 #ifdef CONFIG_SECURE_BOOT
12 #define CONFIG_CMD_ESBC_VALIDATE
13 #define CONFIG_FSL_SEC_MON
14 #define CONFIG_SHA_PROG_HW_ACCEL
15 #define CONFIG_DM
16 #define CONFIG_RSA
17 #define CONFIG_RSA_FREESCALE_EXP
18 #ifndef CONFIG_FSL_CAAM
19 #define CONFIG_FSL_CAAM
20 #endif
21 #endif
22 
23 #ifdef CONFIG_SECURE_BOOT
24 #if defined(CONFIG_FSL_CORENET)
25 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
26 #elif defined(CONFIG_BSC9132QDS)
27 #define CONFIG_SYS_PBI_FLASH_BASE		0xc8000000
28 #elif defined(CONFIG_C29XPCIE)
29 #define CONFIG_SYS_PBI_FLASH_BASE		0xcc000000
30 #else
31 #define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
32 #endif
33 #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
34 
35 #if defined(CONFIG_B4860QDS) || \
36 	defined(CONFIG_T4240QDS) || \
37 	defined(CONFIG_T2080QDS) || \
38 	defined(CONFIG_T2080RDB) || \
39 	defined(CONFIG_T1040QDS) || \
40 	defined(CONFIG_T104xD4QDS) || \
41 	defined(CONFIG_T104xRDB) || \
42 	defined(CONFIG_T104xD4RDB) || \
43 	defined(CONFIG_PPC_T1023) || \
44 	defined(CONFIG_PPC_T1024)
45 #define CONFIG_SYS_CPC_REINIT_F
46 #define CONFIG_KEY_REVOCATION
47 #undef CONFIG_SYS_INIT_L3_ADDR
48 #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
49 #endif
50 
51 #if defined(CONFIG_RAMBOOT_PBL)
52 #undef CONFIG_SYS_INIT_L3_ADDR
53 #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
54 #endif
55 
56 #if defined(CONFIG_C29XPCIE)
57 #define CONFIG_KEY_REVOCATION
58 #endif
59 
60 #if defined(CONFIG_PPC_P3041)	||	\
61 	defined(CONFIG_PPC_P4080) ||	\
62 	defined(CONFIG_PPC_P5020) ||	\
63 	defined(CONFIG_PPC_P5040) ||	\
64 	defined(CONFIG_PPC_P2041)
65 	#define	CONFIG_FSL_TRUST_ARCH_v1
66 #endif
67 
68 #if defined(CONFIG_FSL_CORENET)
69 /* The key used for verification of next level images
70  * is picked up from an Extension Table which has
71  * been verified by the ISBC (Internal Secure boot Code)
72  * in boot ROM of the SoC
73  */
74 #define CONFIG_FSL_ISBC_KEY_EXT
75 #endif
76 
77 #ifndef CONFIG_FIT_SIGNATURE
78 /* If Boot Script is not on NOR and is required to be copied on RAM */
79 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
80 #define CONFIG_BS_HDR_ADDR_RAM		0x00010000
81 #define CONFIG_BS_HDR_ADDR_FLASH	0x00800000
82 #define CONFIG_BS_HDR_SIZE		0x00002000
83 #define CONFIG_BS_ADDR_RAM		0x00012000
84 #define CONFIG_BS_ADDR_FLASH		0x00802000
85 #define CONFIG_BS_SIZE			0x00001000
86 
87 #define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
88 #else
89 
90 /* The bootscript header address is different for B4860 because the NOR
91  * mapping is different on B4 due to reduced NOR size.
92  */
93 #if defined(CONFIG_B4860QDS)
94 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
95 #elif defined(CONFIG_FSL_CORENET)
96 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
97 #elif defined(CONFIG_BSC9132QDS)
98 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
99 #elif defined(CONFIG_C29XPCIE)
100 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
101 #else
102 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
103 #endif
104 
105 #endif
106 
107 #include <config_fsl_secboot.h>
108 #endif
109 
110 #endif
111 #endif
112