17065b7d4SRuchika Gupta /* 27065b7d4SRuchika Gupta * Copyright 2010-2011 Freescale Semiconductor, Inc. 37065b7d4SRuchika Gupta * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 57065b7d4SRuchika Gupta */ 67065b7d4SRuchika Gupta 77065b7d4SRuchika Gupta #ifndef __FSL_SECURE_BOOT_H 87065b7d4SRuchika Gupta #define __FSL_SECURE_BOOT_H 9e04916a7Sgaurav rana #include <asm/config_mpc85xx.h> 10e04916a7Sgaurav rana 11e04916a7Sgaurav rana #ifdef CONFIG_SECURE_BOOT 12bdc22074SAneesh Bansal 13bdc22074SAneesh Bansal #ifndef CONFIG_FIT_SIGNATURE 14bdc22074SAneesh Bansal #define CONFIG_CHAIN_OF_TRUST 15e04916a7Sgaurav rana #endif 167065b7d4SRuchika Gupta 177065b7d4SRuchika Gupta #if defined(CONFIG_FSL_CORENET) 187065b7d4SRuchika Gupta #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 19a202b9f8SYork Sun #elif defined(CONFIG_TARGET_BSC9132QDS) 20f978f7c2SAneesh Bansal #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 21ebccf255SYork Sun #elif defined(CONFIG_TARGET_C29XPCIE) 22b3f0f632SAneesh Bansal #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000 237065b7d4SRuchika Gupta #else 247065b7d4SRuchika Gupta #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 257065b7d4SRuchika Gupta #endif 267065b7d4SRuchika Gupta #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 277065b7d4SRuchika Gupta 28ca4819dfSAneesh Bansal #if defined(CONFIG_B4860QDS) || \ 29ca4819dfSAneesh Bansal defined(CONFIG_T4240QDS) || \ 302d8db6d3SAneesh Bansal defined(CONFIG_T2080QDS) || \ 31e47c2a68SAneesh Bansal defined(CONFIG_T2080RDB) || \ 322d8db6d3SAneesh Bansal defined(CONFIG_T1040QDS) || \ 33e622d9edSgaurav rana defined(CONFIG_T104xD4QDS) || \ 34f6050790SShengzhou Liu defined(CONFIG_T104xRDB) || \ 35e622d9edSgaurav rana defined(CONFIG_T104xD4RDB) || \ 36f6050790SShengzhou Liu defined(CONFIG_PPC_T1023) || \ 37f6050790SShengzhou Liu defined(CONFIG_PPC_T1024) 38aa36c84eSSumit Garg #ifndef CONFIG_SYS_RAMBOOT 39fb4a2409SAneesh Bansal #define CONFIG_SYS_CPC_REINIT_F 40aa36c84eSSumit Garg #endif 41e04916a7Sgaurav rana #define CONFIG_KEY_REVOCATION 42fb4a2409SAneesh Bansal #undef CONFIG_SYS_INIT_L3_ADDR 43fb4a2409SAneesh Bansal #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 44fb4a2409SAneesh Bansal #endif 45fb4a2409SAneesh Bansal 46467a40dfSAneesh Bansal #if defined(CONFIG_RAMBOOT_PBL) 47467a40dfSAneesh Bansal #undef CONFIG_SYS_INIT_L3_ADDR 48aa36c84eSSumit Garg #ifdef CONFIG_SYS_INIT_L3_VADDR 49aa36c84eSSumit Garg #define CONFIG_SYS_INIT_L3_ADDR \ 50aa36c84eSSumit Garg (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 51aa36c84eSSumit Garg 0xbff00000 52aa36c84eSSumit Garg #else 53467a40dfSAneesh Bansal #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 54467a40dfSAneesh Bansal #endif 55aa36c84eSSumit Garg #endif 56467a40dfSAneesh Bansal 57ebccf255SYork Sun #if defined(CONFIG_TARGET_C29XPCIE) 58e04916a7Sgaurav rana #define CONFIG_KEY_REVOCATION 59e04916a7Sgaurav rana #endif 60e04916a7Sgaurav rana 615e5fdd2dSYork Sun #if defined(CONFIG_ARCH_P3041) || \ 62e71372cbSYork Sun defined(CONFIG_ARCH_P4080) || \ 63cefe11cdSYork Sun defined(CONFIG_ARCH_P5020) || \ 64*95390360SYork Sun defined(CONFIG_ARCH_P5040) || \ 65ce040c83SYork Sun defined(CONFIG_ARCH_P2041) 66e04916a7Sgaurav rana #define CONFIG_FSL_TRUST_ARCH_v1 67e04916a7Sgaurav rana #endif 68e04916a7Sgaurav rana 692ed948f4SAneesh Bansal #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) 70e04916a7Sgaurav rana /* The key used for verification of next level images 71e04916a7Sgaurav rana * is picked up from an Extension Table which has 72e04916a7Sgaurav rana * been verified by the ISBC (Internal Secure boot Code) 732ed948f4SAneesh Bansal * in boot ROM of the SoC. 742ed948f4SAneesh Bansal * The feature is only applicable in case of NOR boot and is 752ed948f4SAneesh Bansal * not applicable in case of RAMBOOT (NAND, SD, SPI). 76e04916a7Sgaurav rana */ 77e04916a7Sgaurav rana #define CONFIG_FSL_ISBC_KEY_EXT 78e04916a7Sgaurav rana #endif 79bdc22074SAneesh Bansal #endif /* #ifdef CONFIG_SECURE_BOOT */ 80e04916a7Sgaurav rana 81bdc22074SAneesh Bansal #ifdef CONFIG_CHAIN_OF_TRUST 82b63f8a43SSimon Glass #ifdef CONFIG_SPL_BUILD 838f01397bSSumit Garg /* 848f01397bSSumit Garg * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init 858f01397bSSumit Garg * due to space crunch on CPC and thus malloc will not work. 868f01397bSSumit Garg */ 878f01397bSSumit Garg #define CONFIG_SPL_PPAACT_ADDR 0x2e000000 888f01397bSSumit Garg #define CONFIG_SPL_SPAACT_ADDR 0x2f000000 898f01397bSSumit Garg #define CONFIG_SPL_JR0_LIODN_S 454 908f01397bSSumit Garg #define CONFIG_SPL_JR0_LIODN_NS 458 918f01397bSSumit Garg /* 928f01397bSSumit Garg * Define the key hash for U-Boot here if public/private key pair used to 938f01397bSSumit Garg * sign U-boot are different from the SRK hash put in the fuse 948f01397bSSumit Garg * Example of defining KEY_HASH is 958f01397bSSumit Garg * #define CONFIG_SPL_UBOOT_KEY_HASH \ 968f01397bSSumit Garg * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" 978f01397bSSumit Garg * else leave it defined as NULL 988f01397bSSumit Garg */ 998f01397bSSumit Garg 1008f01397bSSumit Garg #define CONFIG_SPL_UBOOT_KEY_HASH NULL 1018f01397bSSumit Garg #endif /* ifdef CONFIG_SPL_BUILD */ 1028f01397bSSumit Garg 103bdc22074SAneesh Bansal #define CONFIG_CMD_ESBC_VALIDATE 104bdc22074SAneesh Bansal #define CONFIG_CMD_BLOB 105bdc22074SAneesh Bansal #define CONFIG_FSL_SEC_MON 106bdc22074SAneesh Bansal #define CONFIG_SHA_PROG_HW_ACCEL 107bdc22074SAneesh Bansal #define CONFIG_RSA_FREESCALE_EXP 108bdc22074SAneesh Bansal 109bdc22074SAneesh Bansal #ifndef CONFIG_FSL_CAAM 110bdc22074SAneesh Bansal #define CONFIG_FSL_CAAM 111bdc22074SAneesh Bansal #endif 112bdc22074SAneesh Bansal 1138f01397bSSumit Garg #ifndef CONFIG_SPL_BUILD 1148f01397bSSumit Garg /* 1158f01397bSSumit Garg * fsl_setenv_chain_of_trust() must be called from 116d0a6d7ceSAneesh Bansal * board_late_init() 117d0a6d7ceSAneesh Bansal */ 118d0a6d7ceSAneesh Bansal #ifndef CONFIG_BOARD_LATE_INIT 119d0a6d7ceSAneesh Bansal #define CONFIG_BOARD_LATE_INIT 120d0a6d7ceSAneesh Bansal #endif 121d0a6d7ceSAneesh Bansal 1225050f6f0SAneesh Bansal /* If Boot Script is not on NOR and is required to be copied on RAM */ 1235050f6f0SAneesh Bansal #ifdef CONFIG_BOOTSCRIPT_COPY_RAM 1245050f6f0SAneesh Bansal #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 12569d4b48cSSumit Garg #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 1265050f6f0SAneesh Bansal #define CONFIG_BS_HDR_SIZE 0x00002000 1275050f6f0SAneesh Bansal #define CONFIG_BS_ADDR_RAM 0x00012000 12869d4b48cSSumit Garg #define CONFIG_BS_ADDR_DEVICE 0x00802000 1295050f6f0SAneesh Bansal #define CONFIG_BS_SIZE 0x00001000 1305050f6f0SAneesh Bansal 1315050f6f0SAneesh Bansal #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM 1325050f6f0SAneesh Bansal #else 1335050f6f0SAneesh Bansal 13498cb0efdSgaurav rana /* The bootscript header address is different for B4860 because the NOR 13598cb0efdSgaurav rana * mapping is different on B4 due to reduced NOR size. 13698cb0efdSgaurav rana */ 13798cb0efdSgaurav rana #if defined(CONFIG_B4860QDS) 13898cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000 13998cb0efdSgaurav rana #elif defined(CONFIG_FSL_CORENET) 14098cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000 141a202b9f8SYork Sun #elif defined(CONFIG_TARGET_BSC9132QDS) 14298cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000 143ebccf255SYork Sun #elif defined(CONFIG_TARGET_C29XPCIE) 14498cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000 14598cb0efdSgaurav rana #else 14698cb0efdSgaurav rana #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000 14798cb0efdSgaurav rana #endif 14898cb0efdSgaurav rana 149bdc22074SAneesh Bansal #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ 1505050f6f0SAneesh Bansal 151bdc22074SAneesh Bansal #include <config_fsl_chain_trust.h> 1528f01397bSSumit Garg #endif /* #ifndef CONFIG_SPL_BUILD */ 153bdc22074SAneesh Bansal #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ 1540d2cff2dSPo Liu #endif 155