1 /*
2  * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17  * MA 02111-1307 USA
18  *
19  */
20 
21 #ifndef __FSL_PCI_H_
22 #define __FSL_PCI_H_
23 
24 #include <asm/fsl_law.h>
25 
26 int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel);
27 
28 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
29 int fsl_is_pci_agent(struct pci_controller *hose);
30 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
31 void fsl_pci_config_unlock(struct pci_controller *hose);
32 void ft_fsl_pci_setup(void *blob, const char *pci_compat,
33 			struct pci_controller *hose, unsigned long ctrl_addr);
34 
35 /*
36  * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
37  */
38 
39 /*
40  * PCI Translation Registers
41  */
42 typedef struct pci_outbound_window {
43 	u32	potar;		/* 0x00 - Address */
44 	u32	potear;		/* 0x04 - Address Extended */
45 	u32	powbar;		/* 0x08 - Window Base Address */
46 	u32	res1;
47 	u32	powar;		/* 0x10 - Window Attributes */
48 #define POWAR_EN	0x80000000
49 #define POWAR_IO_READ	0x00080000
50 #define POWAR_MEM_READ	0x00040000
51 #define POWAR_IO_WRITE	0x00008000
52 #define POWAR_MEM_WRITE	0x00004000
53 	u32	res2[3];
54 } pot_t;
55 
56 typedef struct pci_inbound_window {
57 	u32	pitar;		/* 0x00 - Address */
58 	u32	res1;
59 	u32	piwbar;		/* 0x08 - Window Base Address */
60 	u32	piwbear;	/* 0x0c - Window Base Address Extended */
61 	u32	piwar;		/* 0x10 - Window Attributes */
62 #define PIWAR_EN		0x80000000
63 #define PIWAR_PF		0x20000000
64 #define PIWAR_LOCAL		0x00f00000
65 #define PIWAR_READ_SNOOP	0x00050000
66 #define PIWAR_WRITE_SNOOP	0x00005000
67 	u32	res2[3];
68 } pit_t;
69 
70 /* PCI/PCI Express Registers */
71 typedef struct ccsr_pci {
72 	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
73 	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
74 	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
75 	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
76 	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
77 	u32	config;		/* 0x014 - PCIE CONFIG Register */
78 	char	res2[8];
79 	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
80 	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
81 	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
82 	u32	pm_command;	/* 0x02c - PCIE PM Command register */
83 	char	res4[3016];	/*     (- #xbf8	 #x30)3016 */
84 	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
85 	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */
86 
87 	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
88 	u32	res5[64];
89 	pit_t	pit[3];		/* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
90 #define PIT3 0
91 #define PIT2 1
92 #define PIT1 2
93 
94 #if 0
95 	u32	potar0;		/* 0xc00 - PCI Outbound Transaction Address Register 0 */
96 	u32	potear0;	/* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
97 	char	res5[8];
98 	u32	powar0;		/* 0xc10 - PCI Outbound Window Attributes Register 0 */
99 	char	res6[12];
100 	u32	potar1;		/* 0xc20 - PCI Outbound Transaction Address Register 1 */
101 	u32	potear1;	/* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
102 	u32	powbar1;	/* 0xc28 - PCI Outbound Window Base Address Register 1 */
103 	char	res7[4];
104 	u32	powar1;		/* 0xc30 - PCI Outbound Window Attributes Register 1 */
105 	char	res8[12];
106 	u32	potar2;		/* 0xc40 - PCI Outbound Transaction Address Register 2 */
107 	u32	potear2;	/* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
108 	u32	powbar2;	/* 0xc48 - PCI Outbound Window Base Address Register 2 */
109 	char	res9[4];
110 	u32	powar2;		/* 0xc50 - PCI Outbound Window Attributes Register 2 */
111 	char	res10[12];
112 	u32	potar3;		/* 0xc60 - PCI Outbound Transaction Address Register 3 */
113 	u32	potear3;	/* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
114 	u32	powbar3;	/* 0xc68 - PCI Outbound Window Base Address Register 3 */
115 	char	res11[4];
116 	u32	powar3;		/* 0xc70 - PCI Outbound Window Attributes Register 3 */
117 	char	res12[12];
118 	u32	potar4;		/* 0xc80 - PCI Outbound Transaction Address Register 4 */
119 	u32	potear4;	/* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
120 	u32	powbar4;	/* 0xc88 - PCI Outbound Window Base Address Register 4 */
121 	char	res13[4];
122 	u32	powar4;		/* 0xc90 - PCI Outbound Window Attributes Register 4 */
123 	char	res14[268];
124 	u32	pitar3;		/* 0xda0 - PCI Inbound Translation Address Register 3 */
125 	char	res15[4];
126 	u32	piwbar3;	/* 0xda8 - PCI Inbound Window Base Address Register 3 */
127 	u32	piwbear3;	/* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
128 	u32	piwar3;		/* 0xdb0 - PCI Inbound Window Attributes Register 3 */
129 	char	res16[12];
130 	u32	pitar2;		/* 0xdc0 - PCI Inbound Translation Address Register 2 */
131 	char	res17[4];
132 	u32	piwbar2;	/* 0xdc8 - PCI Inbound Window Base Address Register 2 */
133 	u32	piwbear2;	/* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
134 	u32	piwar2;		/* 0xdd0 - PCI Inbound Window Attributes Register 2 */
135 	char	res18[12];
136 	u32	pitar1;		/* 0xde0 - PCI Inbound Translation Address Register 1 */
137 	char	res19[4];
138 	u32	piwbar1;	/* 0xde8 - PCI Inbound Window Base Address Register 1 */
139 	char	res20[4];
140 	u32	piwar1;		/* 0xdf0 - PCI Inbound Window Attributes Register 1 */
141 	char	res21[12];
142 #endif
143 	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
144 	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
145 	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
146 	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
147 	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
148 /*	u32	perr_disr	 * 0xe10 - PCIE Erorr Disable Register */
149 	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
150 	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
151 	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
152 	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
153 /*	u32	perr_cap_stat;	 * 0xe20 - PCIE Error Capture Status Register */
154 	char	res22[4];
155 	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
156 	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
157 	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
158 	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
159 	char	res23[200];
160 	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
161 	char	res24[252];
162 } ccsr_fsl_pci_t;
163 
164 struct fsl_pci_info {
165 	unsigned long regs;
166 	pci_addr_t mem_bus;
167 	phys_size_t mem_phys;
168 	pci_size_t mem_size;
169 	pci_addr_t io_bus;
170 	phys_size_t io_phys;
171 	pci_size_t io_size;
172 	enum law_trgt_if law;
173 	int pci_num;
174 };
175 
176 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
177 				struct pci_controller *hose, int busno);
178 
179 #define SET_STD_PCI_INFO(x, num) \
180 {			\
181 	x.regs = CONFIG_SYS_PCI##num##_ADDR;	\
182 	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
183 	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
184 	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
185 	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
186 	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
187 	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
188 	x.law = LAW_TRGT_IF_PCI_##num; \
189 	x.pci_num = num; \
190 }
191 
192 #define SET_STD_PCIE_INFO(x, num) \
193 {			\
194 	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
195 	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
196 	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
197 	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
198 	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
199 	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
200 	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
201 	x.law = LAW_TRGT_IF_PCIE_##num; \
202 	x.pci_num = num; \
203 }
204 
205 #define __FT_FSL_PCI_SETUP(blob, compat, num) \
206 	ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \
207 			 CONFIG_SYS_PCI##num##_ADDR)
208 
209 #define __FT_FSL_PCI_DEL(blob, compat, num) \
210 	ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR)
211 
212 #define __FT_FSL_PCIE_SETUP(blob, compat, num) \
213 	ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \
214 			 CONFIG_SYS_PCIE##num##_ADDR)
215 
216 #define __FT_FSL_PCIE_DEL(blob, compat, num) \
217 	ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR)
218 
219 #ifdef CONFIG_PCI1
220 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
221 #else
222 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1)
223 #endif
224 
225 #ifdef CONFIG_PCI2
226 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
227 #else
228 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2)
229 #endif
230 
231 #ifdef CONFIG_PCIE1
232 #define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
233 #else
234 #define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1)
235 #endif
236 
237 #ifdef CONFIG_PCIE2
238 #define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
239 #else
240 #define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2)
241 #endif
242 
243 #ifdef CONFIG_PCIE3
244 #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
245 #else
246 #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3)
247 #endif
248 
249 #ifdef CONFIG_PCIE4
250 #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
251 #else
252 #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4)
253 #endif
254 
255 #if defined(CONFIG_FSL_CORENET)
256 #define FSL_PCIE_COMPAT	"fsl,p4080-pcie"
257 #define FT_FSL_PCI_SETUP \
258 	FT_FSL_PCIE1_SETUP; \
259 	FT_FSL_PCIE2_SETUP; \
260 	FT_FSL_PCIE3_SETUP; \
261 	FT_FSL_PCIE4_SETUP;
262 #elif defined(CONFIG_MPC85xx)
263 #define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
264 #define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
265 #define FT_FSL_PCI_SETUP \
266 	FT_FSL_PCI1_SETUP; \
267 	FT_FSL_PCI2_SETUP; \
268 	FT_FSL_PCIE1_SETUP; \
269 	FT_FSL_PCIE2_SETUP; \
270 	FT_FSL_PCIE3_SETUP;
271 #elif defined(CONFIG_MPC86xx)
272 #define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
273 #define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"
274 #define FT_FSL_PCI_SETUP \
275 	FT_FSL_PCI1_SETUP; \
276 	FT_FSL_PCIE1_SETUP; \
277 	FT_FSL_PCIE2_SETUP;
278 #else
279 #error FT_FSL_PCI_SETUP not defined
280 #endif
281 
282 
283 #endif
284