1 /* 2 * Copyright 2007,2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __FSL_PCI_H_ 8 #define __FSL_PCI_H_ 9 10 #include <asm/fsl_law.h> 11 #include <asm/fsl_serdes.h> 12 #include <pci.h> 13 14 #define PEX_IP_BLK_REV_2_2 0x02080202 15 #define PEX_IP_BLK_REV_2_3 0x02080203 16 #define PEX_IP_BLK_REV_3_0 0x02080300 17 18 /* Freescale-specific PCI config registers */ 19 #define FSL_PCI_PBFR 0x44 20 21 #define FSL_PCIE_CFG_RDY 0x4b0 22 #define FSL_PCIE_V3_CFG_RDY 0x1 23 #define FSL_PROG_IF_AGENT 0x1 24 25 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ 26 #define PCI_LTSSM_L0 0x16 /* L0 state */ 27 28 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); 29 int fsl_is_pci_agent(struct pci_controller *hose); 30 void fsl_pci_config_unlock(struct pci_controller *hose); 31 void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr); 32 33 /* 34 * Common PCI/PCIE Register structure for mpc85xx and mpc86xx 35 */ 36 37 /* 38 * PCI Translation Registers 39 */ 40 typedef struct pci_outbound_window { 41 u32 potar; /* 0x00 - Address */ 42 u32 potear; /* 0x04 - Address Extended */ 43 u32 powbar; /* 0x08 - Window Base Address */ 44 u32 res1; 45 u32 powar; /* 0x10 - Window Attributes */ 46 #define POWAR_EN 0x80000000 47 #define POWAR_IO_READ 0x00080000 48 #define POWAR_MEM_READ 0x00040000 49 #define POWAR_IO_WRITE 0x00008000 50 #define POWAR_MEM_WRITE 0x00004000 51 u32 res2[3]; 52 } pot_t; 53 54 typedef struct pci_inbound_window { 55 u32 pitar; /* 0x00 - Address */ 56 u32 res1; 57 u32 piwbar; /* 0x08 - Window Base Address */ 58 u32 piwbear; /* 0x0c - Window Base Address Extended */ 59 u32 piwar; /* 0x10 - Window Attributes */ 60 #define PIWAR_EN 0x80000000 61 #define PIWAR_PF 0x20000000 62 #define PIWAR_LOCAL 0x00f00000 63 #define PIWAR_READ_SNOOP 0x00050000 64 #define PIWAR_WRITE_SNOOP 0x00005000 65 u32 res2[3]; 66 } pit_t; 67 68 /* PCI/PCI Express Registers */ 69 typedef struct ccsr_pci { 70 u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ 71 u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ 72 u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ 73 u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ 74 u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ 75 u32 config; /* 0x014 - PCIE CONFIG Register */ 76 u32 int_status; /* 0x018 - PCIE interrupt status register */ 77 char res2[4]; 78 u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ 79 u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ 80 u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ 81 u32 pm_command; /* 0x02c - PCIE PM Command register */ 82 char res3[2188]; /* (0x8bc - 0x30 = 2188) */ 83 u32 dbi_ro_wr_en; /* 0x8bc - DBI read only write enable reg */ 84 char res4[824]; /* (0xbf8 - 0x8c0 = 824) */ 85 u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ 86 u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ 87 88 pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ 89 u32 res5[24]; 90 pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */ 91 u32 res6[24]; 92 pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */ 93 94 #define PIT3 0 95 #define PIT2 1 96 #define PIT1 2 97 98 #if 0 99 u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ 100 u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ 101 char res5[8]; 102 u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ 103 char res6[12]; 104 u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ 105 u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ 106 u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ 107 char res7[4]; 108 u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ 109 char res8[12]; 110 u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ 111 u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ 112 u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ 113 char res9[4]; 114 u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ 115 char res10[12]; 116 u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ 117 u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ 118 u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ 119 char res11[4]; 120 u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ 121 char res12[12]; 122 u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ 123 u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ 124 u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ 125 char res13[4]; 126 u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ 127 char res14[268]; 128 u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ 129 char res15[4]; 130 u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ 131 u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ 132 u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ 133 char res16[12]; 134 u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ 135 char res17[4]; 136 u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ 137 u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ 138 u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ 139 char res18[12]; 140 u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ 141 char res19[4]; 142 u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ 143 char res20[4]; 144 u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ 145 char res21[12]; 146 #endif 147 u32 pedr; /* 0xe00 - PCI Error Detect Register */ 148 u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ 149 u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ 150 u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ 151 u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ 152 /* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ 153 u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ 154 u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ 155 u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ 156 u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ 157 /* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ 158 char res22[4]; 159 u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ 160 u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ 161 u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ 162 u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ 163 char res23[200]; 164 u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ 165 char res24[16]; 166 u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/ 167 u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/ 168 char res25[228]; 169 } ccsr_fsl_pci_t; 170 #define PCIE_CONFIG_PC 0x00020000 171 #define PCIE_CONFIG_OB_CK 0x00002000 172 #define PCIE_CONFIG_SAC 0x00000010 173 #define PCIE_CONFIG_SP 0x80000002 174 #define PCIE_CONFIG_SCC 0x80000001 175 176 struct fsl_pci_info { 177 unsigned long regs; 178 pci_addr_t mem_bus; 179 phys_size_t mem_phys; 180 pci_size_t mem_size; 181 pci_addr_t io_bus; 182 phys_size_t io_phys; 183 pci_size_t io_size; 184 enum law_trgt_if law; 185 int pci_num; 186 }; 187 188 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info); 189 int fsl_pci_init_port(struct fsl_pci_info *pci_info, 190 struct pci_controller *hose, int busno); 191 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, 192 struct fsl_pci_info *pci_info); 193 int fsl_pcie_init_board(int busno); 194 195 #define SET_STD_PCI_INFO(x, num) \ 196 { \ 197 x.regs = CONFIG_SYS_PCI##num##_ADDR; \ 198 x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ 199 x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ 200 x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ 201 x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ 202 x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ 203 x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ 204 x.law = LAW_TRGT_IF_PCI_##num; \ 205 x.pci_num = num; \ 206 } 207 208 #define SET_STD_PCIE_INFO(x, num) \ 209 { \ 210 x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ 211 x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ 212 x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ 213 x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ 214 x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ 215 x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ 216 x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ 217 x.law = LAW_TRGT_IF_PCIE_##num; \ 218 x.pci_num = num; \ 219 } 220 221 #define __FT_FSL_PCI_SETUP(blob, compat, num) \ 222 ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) 223 224 #define __FT_FSL_PCIE_SETUP(blob, compat, num) \ 225 ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) 226 227 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) 228 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) 229 230 #define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1) 231 #define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2) 232 #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3) 233 #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4) 234 235 #if !defined(CONFIG_PCI) 236 #define FT_FSL_PCI_SETUP 237 #elif defined(CONFIG_FSL_CORENET) 238 #define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT 239 #define FT_FSL_PCI_SETUP \ 240 FT_FSL_PCIE1_SETUP; \ 241 FT_FSL_PCIE2_SETUP; \ 242 FT_FSL_PCIE3_SETUP; \ 243 FT_FSL_PCIE4_SETUP; 244 #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP 245 #elif defined(CONFIG_MPC85xx) 246 #define FSL_PCI_COMPAT "fsl,mpc8540-pci" 247 #ifdef CONFIG_SYS_FSL_PCIE_COMPAT 248 #define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT 249 #else 250 #define FSL_PCIE_COMPAT "fsl,mpc8548-pcie" 251 #endif 252 #define FT_FSL_PCI_SETUP \ 253 FT_FSL_PCI1_SETUP; \ 254 FT_FSL_PCI2_SETUP; \ 255 FT_FSL_PCIE1_SETUP; \ 256 FT_FSL_PCIE2_SETUP; \ 257 FT_FSL_PCIE3_SETUP; 258 #define FT_FSL_PCIE_SETUP \ 259 FT_FSL_PCIE1_SETUP; \ 260 FT_FSL_PCIE2_SETUP; \ 261 FT_FSL_PCIE3_SETUP; 262 #elif defined(CONFIG_MPC86xx) 263 #define FSL_PCI_COMPAT "fsl,mpc8610-pci" 264 #define FSL_PCIE_COMPAT "fsl,mpc8641-pcie" 265 #define FT_FSL_PCI_SETUP \ 266 FT_FSL_PCI1_SETUP; \ 267 FT_FSL_PCIE1_SETUP; \ 268 FT_FSL_PCIE2_SETUP; 269 #else 270 #error FT_FSL_PCI_SETUP not defined 271 #endif 272 273 274 #endif 275