1 /*
2  * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12 
13 #ifndef __ASM_PPC_FSL_LBC_H
14 #define __ASM_PPC_FSL_LBC_H
15 
16 #include <config.h>
17 #include <common.h>
18 
19 #ifdef CONFIG_MPC85xx
20 void lbc_sdram_init(void);
21 #endif
22 
23 /* BR - Base Registers
24  */
25 #define BR0				0x5000		/* Register offset to immr */
26 #define BR1				0x5008
27 #define BR2				0x5010
28 #define BR3				0x5018
29 #define BR4				0x5020
30 #define BR5				0x5028
31 #define BR6				0x5030
32 #define BR7				0x5038
33 
34 #define BR_BA				0xFFFF8000
35 #define BR_BA_SHIFT			15
36 #define BR_XBA				0x00006000
37 #define BR_XBA_SHIFT			13
38 #define BR_PS				0x00001800
39 #define BR_PS_SHIFT			11
40 #define BR_PS_8				0x00000800	/* Port Size 8 bit */
41 #define BR_PS_16			0x00001000	/* Port Size 16 bit */
42 #define BR_PS_32			0x00001800	/* Port Size 32 bit */
43 #define BR_DECC				0x00000600
44 #define BR_DECC_SHIFT			9
45 #define BR_DECC_OFF			0x00000000
46 #define BR_DECC_CHK			0x00000200
47 #define BR_DECC_CHK_GEN			0x00000400
48 #define BR_WP				0x00000100
49 #define BR_WP_SHIFT			8
50 #define BR_MSEL				0x000000E0
51 #define BR_MSEL_SHIFT			5
52 #define BR_MS_GPCM			0x00000000	/* GPCM */
53 #if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360)
54 #define BR_MS_FCM			0x00000020	/* FCM */
55 #endif
56 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360)
57 #define BR_MS_SDRAM			0x00000060	/* SDRAM */
58 #elif defined(CONFIG_MPC85xx)
59 #define BR_MS_SDRAM			0x00000000	/* SDRAM */
60 #endif
61 #define BR_MS_UPMA			0x00000080	/* UPMA */
62 #define BR_MS_UPMB			0x000000A0	/* UPMB */
63 #define BR_MS_UPMC			0x000000C0	/* UPMC */
64 #if !defined(CONFIG_MPC834x)
65 #define BR_ATOM				0x0000000C
66 #define BR_ATOM_SHIFT			2
67 #endif
68 #define BR_V				0x00000001
69 #define BR_V_SHIFT			0
70 
71 #define BR_UPMx_TO_MSEL(x)		((x + 4) << BR_MSEL_SHIFT)
72 
73 #define UPMA			0
74 #define UPMB			1
75 #define UPMC			2
76 
77 #if defined(CONFIG_MPC834x)
78 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
79 #else
80 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
81 #endif
82 
83 /* Convert an address into the right format for the BR registers */
84 #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
85 #define BR_PHYS_ADDR(x)	((unsigned long)((x & 0x0ffff8000ULL) | \
86 					 ((x & 0x300000000ULL) >> 19)))
87 #else
88 #define BR_PHYS_ADDR(x) (x & 0xffff8000)
89 #endif
90 
91 /* OR - Option Registers
92  */
93 #define OR0				0x5004		/* Register offset to immr */
94 #define OR1				0x500C
95 #define OR2				0x5014
96 #define OR3				0x501C
97 #define OR4				0x5024
98 #define OR5				0x502C
99 #define OR6				0x5034
100 #define OR7				0x503C
101 
102 #define OR_GPCM_AM			0xFFFF8000
103 #define OR_GPCM_AM_SHIFT		15
104 #define OR_GPCM_XAM			0x00006000
105 #define OR_GPCM_XAM_SHIFT		13
106 #define OR_GPCM_BCTLD			0x00001000
107 #define OR_GPCM_BCTLD_SHIFT		12
108 #define OR_GPCM_CSNT			0x00000800
109 #define OR_GPCM_CSNT_SHIFT		11
110 #define OR_GPCM_ACS			0x00000600
111 #define OR_GPCM_ACS_SHIFT		9
112 #define OR_GPCM_ACS_DIV2		0x00000600
113 #define OR_GPCM_ACS_DIV4		0x00000400
114 #define OR_GPCM_XACS			0x00000100
115 #define OR_GPCM_XACS_SHIFT		8
116 #define OR_GPCM_SCY			0x000000F0
117 #define OR_GPCM_SCY_SHIFT		4
118 #define OR_GPCM_SCY_1			0x00000010
119 #define OR_GPCM_SCY_2			0x00000020
120 #define OR_GPCM_SCY_3			0x00000030
121 #define OR_GPCM_SCY_4			0x00000040
122 #define OR_GPCM_SCY_5			0x00000050
123 #define OR_GPCM_SCY_6			0x00000060
124 #define OR_GPCM_SCY_7			0x00000070
125 #define OR_GPCM_SCY_8			0x00000080
126 #define OR_GPCM_SCY_9			0x00000090
127 #define OR_GPCM_SCY_10			0x000000a0
128 #define OR_GPCM_SCY_11			0x000000b0
129 #define OR_GPCM_SCY_12			0x000000c0
130 #define OR_GPCM_SCY_13			0x000000d0
131 #define OR_GPCM_SCY_14			0x000000e0
132 #define OR_GPCM_SCY_15			0x000000f0
133 #define OR_GPCM_SETA			0x00000008
134 #define OR_GPCM_SETA_SHIFT		3
135 #define OR_GPCM_TRLX			0x00000004
136 #define OR_GPCM_TRLX_SHIFT		2
137 #define OR_GPCM_TRLX_CLEAR		0x00000000
138 #define OR_GPCM_TRLX_SET		0x00000004
139 #define OR_GPCM_EHTR			0x00000002
140 #define OR_GPCM_EHTR_SHIFT		1
141 #define OR_GPCM_EHTR_CLEAR		0x00000000
142 #define OR_GPCM_EHTR_SET		0x00000002
143 #if !defined(CONFIG_MPC8308)
144 #define OR_GPCM_EAD			0x00000001
145 #define OR_GPCM_EAD_SHIFT		0
146 #endif
147 
148 /* helpers to convert values into an OR address mask (GPCM mode) */
149 #define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
150 #define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
151 
152 #define OR_FCM_AM			0xFFFF8000
153 #define OR_FCM_AM_SHIFT				15
154 #define OR_FCM_XAM			0x00006000
155 #define OR_FCM_XAM_SHIFT		13
156 #define OR_FCM_BCTLD			0x00001000
157 #define OR_FCM_BCTLD_SHIFT			12
158 #define OR_FCM_PGS			0x00000400
159 #define OR_FCM_PGS_SHIFT			10
160 #define OR_FCM_CSCT			0x00000200
161 #define OR_FCM_CSCT_SHIFT			 9
162 #define OR_FCM_CST			0x00000100
163 #define OR_FCM_CST_SHIFT			 8
164 #define OR_FCM_CHT			0x00000080
165 #define OR_FCM_CHT_SHIFT			 7
166 #define OR_FCM_SCY			0x00000070
167 #define OR_FCM_SCY_SHIFT			 4
168 #define OR_FCM_SCY_1			0x00000010
169 #define OR_FCM_SCY_2			0x00000020
170 #define OR_FCM_SCY_3			0x00000030
171 #define OR_FCM_SCY_4			0x00000040
172 #define OR_FCM_SCY_5			0x00000050
173 #define OR_FCM_SCY_6			0x00000060
174 #define OR_FCM_SCY_7			0x00000070
175 #define OR_FCM_RST			0x00000008
176 #define OR_FCM_RST_SHIFT			 3
177 #define OR_FCM_TRLX			0x00000004
178 #define OR_FCM_TRLX_SHIFT			 2
179 #define OR_FCM_EHTR			0x00000002
180 #define OR_FCM_EHTR_SHIFT			 1
181 
182 #define OR_UPM_AM			0xFFFF8000
183 #define OR_UPM_AM_SHIFT			15
184 #define OR_UPM_XAM			0x00006000
185 #define OR_UPM_XAM_SHIFT		13
186 #define OR_UPM_BCTLD			0x00001000
187 #define OR_UPM_BCTLD_SHIFT		12
188 #define OR_UPM_BI			0x00000100
189 #define OR_UPM_BI_SHIFT			8
190 #define OR_UPM_TRLX			0x00000004
191 #define OR_UPM_TRLX_SHIFT		2
192 #define OR_UPM_EHTR			0x00000002
193 #define OR_UPM_EHTR_SHIFT		1
194 #define OR_UPM_EAD			0x00000001
195 #define OR_UPM_EAD_SHIFT		0
196 
197 #define OR_SDRAM_AM			0xFFFF8000
198 #define OR_SDRAM_AM_SHIFT		15
199 #define OR_SDRAM_XAM			0x00006000
200 #define OR_SDRAM_XAM_SHIFT		13
201 #define OR_SDRAM_COLS			0x00001C00
202 #define OR_SDRAM_COLS_SHIFT		10
203 #define OR_SDRAM_MIN_COLS		7
204 #define OR_SDRAM_ROWS			0x000001C0
205 #define OR_SDRAM_ROWS_SHIFT		6
206 #define OR_SDRAM_MIN_ROWS		9
207 #define OR_SDRAM_PMSEL			0x00000020
208 #define OR_SDRAM_PMSEL_SHIFT		5
209 #define OR_SDRAM_EAD			0x00000001
210 #define OR_SDRAM_EAD_SHIFT		0
211 
212 #define OR_AM_32KB			0xFFFF8000
213 #define OR_AM_64KB			0xFFFF0000
214 #define OR_AM_128KB			0xFFFE0000
215 #define OR_AM_256KB			0xFFFC0000
216 #define OR_AM_512KB			0xFFF80000
217 #define OR_AM_1MB			0xFFF00000
218 #define OR_AM_2MB			0xFFE00000
219 #define OR_AM_4MB			0xFFC00000
220 #define OR_AM_8MB			0xFF800000
221 #define OR_AM_16MB			0xFF000000
222 #define OR_AM_32MB			0xFE000000
223 #define OR_AM_64MB			0xFC000000
224 #define OR_AM_128MB			0xF8000000
225 #define OR_AM_256MB			0xF0000000
226 #define OR_AM_512MB			0xE0000000
227 #define OR_AM_1GB			0xC0000000
228 #define OR_AM_2GB			0x80000000
229 #define OR_AM_4GB			0x00000000
230 
231 /* MxMR - UPM Machine A/B/C Mode Registers
232  */
233 #define MxMR_MAD_MSK		0x0000003f /* Machine Address Mask	   */
234 #define MxMR_TLFx_MSK		0x000003c0 /* Refresh Loop Field Mask	   */
235 #define MxMR_WLFx_MSK		0x00003c00 /* Write Loop Field Mask	   */
236 #define MxMR_WLFx_1X		0x00000400 /*	executed 1 time		   */
237 #define MxMR_WLFx_2X		0x00000800 /*	executed 2 times	   */
238 #define MxMR_WLFx_3X		0x00000c00 /*	executed 3 times	   */
239 #define MxMR_WLFx_4X		0x00001000 /*	executed 4 times	   */
240 #define MxMR_WLFx_5X		0x00001400 /*	executed 5 times	   */
241 #define MxMR_WLFx_6X		0x00001800 /*	executed 6 times	   */
242 #define MxMR_WLFx_7X		0x00001c00 /*	executed 7 times	   */
243 #define MxMR_WLFx_8X		0x00002000 /*	executed 8 times	   */
244 #define MxMR_WLFx_9X		0x00002400 /*	executed 9 times	   */
245 #define MxMR_WLFx_10X		0x00002800 /*	executed 10 times	   */
246 #define MxMR_WLFx_11X		0x00002c00 /*	executed 11 times	   */
247 #define MxMR_WLFx_12X		0x00003000 /*	executed 12 times	   */
248 #define MxMR_WLFx_13X		0x00003400 /*	executed 13 times	   */
249 #define MxMR_WLFx_14X		0x00003800 /*	executed 14 times	   */
250 #define MxMR_WLFx_15X		0x00003c00 /*	executed 15 times	   */
251 #define MxMR_WLFx_16X		0x00000000 /*	executed 16 times	   */
252 #define MxMR_RLFx_MSK		0x0003c000 /* Read Loop Field Mask	   */
253 #define MxMR_GPL_x4DIS		0x00040000 /* GPL_A4 Ouput Line Disable	   */
254 #define MxMR_G0CLx_MSK		0x00380000 /* General Line 0 Control Mask  */
255 #define MxMR_DSx_1_CYCL		0x00000000 /* 1 cycle Disable Period	   */
256 #define MxMR_DSx_2_CYCL		0x00400000 /* 2 cycle Disable Period	   */
257 #define MxMR_DSx_3_CYCL		0x00800000 /* 3 cycle Disable Period	   */
258 #define MxMR_DSx_4_CYCL		0x00c00000 /* 4 cycle Disable Period	   */
259 #define MxMR_DSx_MSK		0x00c00000 /* Disable Timer Period Mask	   */
260 #define MxMR_AMx_MSK		0x07000000 /* Addess Multiplex Size Mask   */
261 #define MxMR_UWPL		0x08000000 /* LUPWAIT Polarity Mask	   */
262 #define MxMR_OP_NORM		0x00000000 /* Normal Operation		   */
263 #define MxMR_OP_WARR		0x10000000 /* Write to Array		   */
264 #define MxMR_OP_RARR		0x20000000 /* Read from Array		   */
265 #define MxMR_OP_RUNP		0x30000000 /* Run Pattern		   */
266 #define MxMR_OP_MSK		0x30000000 /* Command Opcode Mask	   */
267 #define MxMR_RFEN		0x40000000 /* Refresh Enable		   */
268 #define MxMR_BSEL		0x80000000 /* Bus Select		   */
269 
270 #define LBLAWAR_EN			0x80000000
271 #define LBLAWAR_4KB			0x0000000B
272 #define LBLAWAR_8KB			0x0000000C
273 #define LBLAWAR_16KB			0x0000000D
274 #define LBLAWAR_32KB			0x0000000E
275 #define LBLAWAR_64KB			0x0000000F
276 #define LBLAWAR_128KB			0x00000010
277 #define LBLAWAR_256KB			0x00000011
278 #define LBLAWAR_512KB			0x00000012
279 #define LBLAWAR_1MB			0x00000013
280 #define LBLAWAR_2MB			0x00000014
281 #define LBLAWAR_4MB			0x00000015
282 #define LBLAWAR_8MB			0x00000016
283 #define LBLAWAR_16MB			0x00000017
284 #define LBLAWAR_32MB			0x00000018
285 #define LBLAWAR_64MB			0x00000019
286 #define LBLAWAR_128MB			0x0000001A
287 #define LBLAWAR_256MB			0x0000001B
288 #define LBLAWAR_512MB			0x0000001C
289 #define LBLAWAR_1GB			0x0000001D
290 #define LBLAWAR_2GB			0x0000001E
291 
292 /* LBCR - Local Bus Configuration Register
293  */
294 #define LBCR_LDIS			0x80000000
295 #define LBCR_LDIS_SHIFT			31
296 #define LBCR_BCTLC			0x00C00000
297 #define LBCR_BCTLC_SHIFT		22
298 #define LBCR_LPBSE			0x00020000
299 #define LBCR_LPBSE_SHIFT		17
300 #define LBCR_EPAR			0x00010000
301 #define LBCR_EPAR_SHIFT			16
302 #define LBCR_BMT			0x0000FF00
303 #define LBCR_BMT_SHIFT			8
304 #define LBCR_BMTPS	 		0x0000000F
305 #define LBCR_BMTPS_SHIFT 		0
306 
307 /* LCRR - Clock Ratio Register
308  */
309 #define LCRR_DBYP			0x80000000
310 #define LCRR_DBYP_SHIFT			31
311 #define LCRR_BUFCMDC			0x30000000
312 #define LCRR_BUFCMDC_SHIFT		28
313 #define LCRR_BUFCMDC_1			0x10000000
314 #define LCRR_BUFCMDC_2			0x20000000
315 #define LCRR_BUFCMDC_3			0x30000000
316 #define LCRR_BUFCMDC_4			0x00000000
317 #define LCRR_ECL			0x03000000
318 #define LCRR_ECL_SHIFT			24
319 #define LCRR_ECL_4			0x00000000
320 #define LCRR_ECL_5			0x01000000
321 #define LCRR_ECL_6			0x02000000
322 #define LCRR_ECL_7			0x03000000
323 #define LCRR_EADC			0x00030000
324 #define LCRR_EADC_SHIFT			16
325 #define LCRR_EADC_1			0x00010000
326 #define LCRR_EADC_2			0x00020000
327 #define LCRR_EADC_3			0x00030000
328 #define LCRR_EADC_4			0x00000000
329 /* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
330  * should always be zero on older parts that have a four bit CLKDIV.
331  */
332 #define LCRR_CLKDIV			0x0000001F
333 #define LCRR_CLKDIV_SHIFT		0
334 #if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
335     defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
336     defined(CONFIG_MPC8560)
337 #define LCRR_CLKDIV_2			0x00000002
338 #define LCRR_CLKDIV_4			0x00000004
339 #define LCRR_CLKDIV_8			0x00000008
340 #elif defined(CONFIG_FSL_CORENET)
341 #define LCRR_CLKDIV_8			0x00000002
342 #define LCRR_CLKDIV_16			0x00000004
343 #define LCRR_CLKDIV_32			0x00000008
344 #else
345 #define LCRR_CLKDIV_4			0x00000002
346 #define LCRR_CLKDIV_8			0x00000004
347 #define LCRR_CLKDIV_16			0x00000008
348 #endif
349 
350 /* LTEDR - Transfer Error Check Disable Register
351  */
352 #define LTEDR_BMD	0x80000000 /* Bus monitor disable				*/
353 #define LTEDR_PARD	0x20000000 /* Parity error checking disabled			*/
354 #define LTEDR_WPD	0x04000000 /* Write protect error checking diable		*/
355 #define LTEDR_WARA	0x00800000 /* Write-after-read-atomic error checking diable	*/
356 #define LTEDR_RAWA	0x00400000 /* Read-after-write-atomic error checking disable	*/
357 #define LTEDR_CSD	0x00080000 /* Chip select error checking disable		*/
358 
359 /* FMR - Flash Mode Register
360  */
361 #define FMR_CWTO               0x0000F000
362 #define FMR_CWTO_SHIFT         12
363 #define FMR_BOOT               0x00000800
364 #define FMR_ECCM               0x00000100
365 #define FMR_AL                 0x00000030
366 #define FMR_AL_SHIFT           4
367 #define FMR_OP                 0x00000003
368 #define FMR_OP_SHIFT           0
369 
370 /* FIR - Flash Instruction Register
371  */
372 #define FIR_OP0                        0xF0000000
373 #define FIR_OP0_SHIFT          28
374 #define FIR_OP1                        0x0F000000
375 #define FIR_OP1_SHIFT          24
376 #define FIR_OP2                        0x00F00000
377 #define FIR_OP2_SHIFT          20
378 #define FIR_OP3                        0x000F0000
379 #define FIR_OP3_SHIFT          16
380 #define FIR_OP4                        0x0000F000
381 #define FIR_OP4_SHIFT          12
382 #define FIR_OP5                        0x00000F00
383 #define FIR_OP5_SHIFT          8
384 #define FIR_OP6                        0x000000F0
385 #define FIR_OP6_SHIFT          4
386 #define FIR_OP7                        0x0000000F
387 #define FIR_OP7_SHIFT          0
388 #define FIR_OP_NOP             0x0 /* No operation and end of sequence */
389 #define FIR_OP_CA              0x1 /* Issue current column address */
390 #define FIR_OP_PA              0x2 /* Issue current block+page address */
391 #define FIR_OP_UA              0x3 /* Issue user defined address */
392 #define FIR_OP_CM0             0x4 /* Issue command from FCR[CMD0] */
393 #define FIR_OP_CM1             0x5 /* Issue command from FCR[CMD1] */
394 #define FIR_OP_CM2             0x6 /* Issue command from FCR[CMD2] */
395 #define FIR_OP_CM3             0x7 /* Issue command from FCR[CMD3] */
396 #define FIR_OP_WB              0x8 /* Write FBCR bytes from FCM buffer */
397 #define FIR_OP_WS              0x9 /* Write 1 or 2 bytes from MDR[AS] */
398 #define FIR_OP_RB              0xA /* Read FBCR bytes to FCM buffer */
399 #define FIR_OP_RS              0xB /* Read 1 or 2 bytes to MDR[AS] */
400 #define FIR_OP_CW0             0xC /* Wait then issue FCR[CMD0] */
401 #define FIR_OP_CW1             0xD /* Wait then issue FCR[CMD1] */
402 #define FIR_OP_RBW             0xE /* Wait then read FBCR bytes */
403 #define FIR_OP_RSW             0xF /* Wait then read 1 or 2 bytes */
404 
405 /* FCR - Flash Command Register
406  */
407 #define FCR_CMD0               0xFF000000
408 #define FCR_CMD0_SHIFT         24
409 #define FCR_CMD1               0x00FF0000
410 #define FCR_CMD1_SHIFT         16
411 #define FCR_CMD2               0x0000FF00
412 #define FCR_CMD2_SHIFT         8
413 #define FCR_CMD3               0x000000FF
414 #define FCR_CMD3_SHIFT         0
415 /* FBAR - Flash Block Address Register
416  */
417 #define FBAR_BLK               0x00FFFFFF
418 
419 /* FPAR - Flash Page Address Register
420  */
421 #define FPAR_SP_PI             0x00007C00
422 #define FPAR_SP_PI_SHIFT       10
423 #define FPAR_SP_MS             0x00000200
424 #define FPAR_SP_CI             0x000001FF
425 #define FPAR_SP_CI_SHIFT       0
426 #define FPAR_LP_PI             0x0003F000
427 #define FPAR_LP_PI_SHIFT       12
428 #define FPAR_LP_MS             0x00000800
429 #define FPAR_LP_CI             0x000007FF
430 #define FPAR_LP_CI_SHIFT       0
431 
432 /* LSDMR - SDRAM Machine Mode Register
433  */
434 #define LSDMR_RFEN	(1 << (31 -  1))
435 #define LSDMR_BSMA1516	(3 << (31 - 10))
436 #define LSDMR_BSMA1617	(4 << (31 - 10))
437 #define LSDMR_RFCR5	(3 << (31 - 16))
438 #define LSDMR_RFCR16	(7 << (31 - 16))
439 #define LSDMR_PRETOACT3 (3 << (31 - 19))
440 #define LSDMR_PRETOACT7	(7 << (31 - 19))
441 #define LSDMR_ACTTORW3	(3 << (31 - 22))
442 #define LSDMR_ACTTORW7	(7 << (31 - 22))
443 #define LSDMR_ACTTORW6	(6 << (31 - 22))
444 #define LSDMR_BL8	(1 << (31 - 23))
445 #define LSDMR_WRC2	(2 << (31 - 27))
446 #define LSDMR_WRC4	(0 << (31 - 27))
447 #define LSDMR_BUFCMD	(1 << (31 - 29))
448 #define LSDMR_CL3	(3 << (31 - 31))
449 
450 #define LSDMR_OP_NORMAL	(0 << (31 - 4))
451 #define LSDMR_OP_ARFRSH	(1 << (31 - 4))
452 #define LSDMR_OP_SRFRSH	(2 << (31 - 4))
453 #define LSDMR_OP_MRW	(3 << (31 - 4))
454 #define LSDMR_OP_PRECH	(4 << (31 - 4))
455 #define LSDMR_OP_PCHALL	(5 << (31 - 4))
456 #define LSDMR_OP_ACTBNK	(6 << (31 - 4))
457 #define LSDMR_OP_RWINV	(7 << (31 - 4))
458 
459 /* LTESR - Transfer Error Status Register
460  */
461 #define LTESR_BM               0x80000000
462 #define LTESR_FCT              0x40000000
463 #define LTESR_PAR              0x20000000
464 #define LTESR_WP               0x04000000
465 #define LTESR_ATMW             0x00800000
466 #define LTESR_ATMR             0x00400000
467 #define LTESR_CS               0x00080000
468 #define LTESR_CC               0x00000001
469 
470 #ifndef __ASSEMBLY__
471 #include <asm/io.h>
472 
473 extern void print_lbc_regs(void);
474 extern void init_early_memctl_regs(void);
475 extern void upmconfig(uint upm, uint *table, uint size);
476 
477 #define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
478 #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
479 #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
480 #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
481 #define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
482 #define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
483 #define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
484 
485 typedef struct lbc_bank {
486 	u32     br;
487 	u32     or;
488 } lbc_bank_t;
489 
490 /* Local Bus Controller Registers */
491 typedef struct fsl_lbc {
492 	lbc_bank_t      bank[8];
493 	u8	res1[40];
494 	u32     mar;            /* LBC UPM Addr */
495 	u8      res2[4];
496 	u32     mamr;           /* LBC UPMA Mode */
497 	u32     mbmr;           /* LBC UPMB Mode */
498 	u32     mcmr;           /* LBC UPMC Mode */
499 	u8      res3[8];
500 	u32     mrtpr;          /* LBC Memory Refresh Timer Prescaler */
501 	u32     mdr;            /* LBC UPM Data */
502 #ifdef CONFIG_FSL_ELBC
503 	u8      res4[4];
504 	u32     lsor;
505 	u8      res5[12];
506 	u32     lurt;           /* LBC UPM Refresh Timer */
507 	u8	res6[4];
508 #else
509 	u8	res4[8];
510 	u32     lsdmr;          /* LBC SDRAM Mode */
511 	u8	res5[8];
512 	u32     lurt;           /* LBC UPM Refresh Timer */
513 	u32     lsrt;           /* LBC SDRAM Refresh Timer */
514 #endif
515 	u8      res7[8];
516 	u32     ltesr;          /* LBC Transfer Error Status */
517 	u32     ltedr;          /* LBC Transfer Error Disable */
518 	u32     lteir;          /* LBC Transfer Error IRQ */
519 	u32     lteatr;         /* LBC Transfer Error Attrs */
520 	u32     ltear;          /* LBC Transfer Error Addr */
521 	u8      res8[12];
522 	u32     lbcr;           /* LBC Configuration */
523 	u32     lcrr;           /* LBC Clock Ratio */
524 #ifdef CONFIG_NAND_FSL_ELBC
525 	u8	res9[0x8];
526 	u32     fmr;            /* Flash Mode Register */
527 	u32     fir;            /* Flash Instruction Register */
528 	u32     fcr;            /* Flash Command Register */
529 	u32     fbar;           /* Flash Block Addr Register */
530 	u32     fpar;           /* Flash Page Addr Register */
531 	u32     fbcr;           /* Flash Byte Count Register */
532 	u8      res10[0xF08];
533 #else
534 	u8      res9[0xF28];
535 #endif
536 } fsl_lbc_t;
537 
538 #endif /* __ASSEMBLY__ */
539 #endif /* __ASM_PPC_FSL_LBC_H */
540