1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #ifndef _FSL_LAW_H_ 10 #define _FSL_LAW_H_ 11 12 #include <asm/io.h> 13 14 #define LAW_EN 0x80000000 15 16 #define SET_LAW_ENTRY(idx, a, sz, trgt) \ 17 { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } 18 19 #define SET_LAW(a, sz, trgt) \ 20 { .index = -1, .addr = a, .size = sz, .trgt_id = trgt } 21 22 enum law_size { 23 LAW_SIZE_4K = 0xb, 24 LAW_SIZE_8K, 25 LAW_SIZE_16K, 26 LAW_SIZE_32K, 27 LAW_SIZE_64K, 28 LAW_SIZE_128K, 29 LAW_SIZE_256K, 30 LAW_SIZE_512K, 31 LAW_SIZE_1M, 32 LAW_SIZE_2M, 33 LAW_SIZE_4M, 34 LAW_SIZE_8M, 35 LAW_SIZE_16M, 36 LAW_SIZE_32M, 37 LAW_SIZE_64M, 38 LAW_SIZE_128M, 39 LAW_SIZE_256M, 40 LAW_SIZE_512M, 41 LAW_SIZE_1G, 42 LAW_SIZE_2G, 43 LAW_SIZE_4G, 44 LAW_SIZE_8G, 45 LAW_SIZE_16G, 46 LAW_SIZE_32G, 47 }; 48 49 #define law_size_bits(sz) (__ilog2_u64(sz) - 1) 50 #define lawar_size(x) (1ULL << ((x & 0x3f) + 1)) 51 52 #ifdef CONFIG_FSL_CORENET 53 enum law_trgt_if { 54 LAW_TRGT_IF_PCIE_1 = 0x00, 55 LAW_TRGT_IF_PCIE_2 = 0x01, 56 LAW_TRGT_IF_PCIE_3 = 0x02, 57 LAW_TRGT_IF_PCIE_4 = 0x03, 58 LAW_TRGT_IF_RIO_1 = 0x08, 59 LAW_TRGT_IF_RIO_2 = 0x09, 60 61 LAW_TRGT_IF_DDR_1 = 0x10, 62 LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ 63 LAW_TRGT_IF_DDR_INTRLV = 0x14, 64 65 LAW_TRGT_IF_BMAN = 0x18, 66 LAW_TRGT_IF_DCSR = 0x1d, 67 LAW_TRGT_IF_LBC = 0x1f, 68 LAW_TRGT_IF_QMAN = 0x3c, 69 }; 70 #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 71 #else 72 enum law_trgt_if { 73 LAW_TRGT_IF_PCI = 0x00, 74 LAW_TRGT_IF_PCI_2 = 0x01, 75 #ifndef CONFIG_MPC8641 76 LAW_TRGT_IF_PCIE_1 = 0x02, 77 #endif 78 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) 79 LAW_TRGT_IF_PCIE_3 = 0x03, 80 #endif 81 LAW_TRGT_IF_LBC = 0x04, 82 LAW_TRGT_IF_CCSR = 0x08, 83 LAW_TRGT_IF_DDR_INTRLV = 0x0b, 84 LAW_TRGT_IF_RIO = 0x0c, 85 LAW_TRGT_IF_RIO_2 = 0x0d, 86 LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, 87 LAW_TRGT_IF_DDR = 0x0f, 88 LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ 89 }; 90 #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR 91 #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI 92 #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI 93 #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 94 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO 95 #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC 96 97 #ifdef CONFIG_MPC8641 98 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI 99 #endif 100 101 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) 102 #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI 103 #endif 104 #endif /* CONFIG_FSL_CORENET */ 105 106 struct law_entry { 107 int index; 108 phys_addr_t addr; 109 enum law_size size; 110 enum law_trgt_if trgt_id; 111 }; 112 113 extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 114 extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 115 extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); 116 extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); 117 extern struct law_entry find_law(phys_addr_t addr); 118 extern void disable_law(u8 idx); 119 extern void init_laws(void); 120 extern void print_laws(void); 121 122 /* define in board code */ 123 extern struct law_entry law_table[]; 124 extern int num_law_entries; 125 #endif 126