1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Freescale I2C Controller 4 * 5 * Copyright 2006 Freescale Semiconductor, Inc. 6 * 7 * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, 8 * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), 9 * and Jeff Brown. 10 * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. 11 */ 12 13 #ifndef _ASM_FSL_I2C_H_ 14 #define _ASM_FSL_I2C_H_ 15 16 #include <asm/types.h> 17 18 typedef struct fsl_i2c_base { 19 20 u8 adr; /* I2C slave address */ 21 u8 res0[3]; 22 #define I2C_ADR 0xFE 23 #define I2C_ADR_SHIFT 1 24 #define I2C_ADR_RES ~(I2C_ADR) 25 26 u8 fdr; /* I2C frequency divider register */ 27 u8 res1[3]; 28 #define IC2_FDR 0x3F 29 #define IC2_FDR_SHIFT 0 30 #define IC2_FDR_RES ~(IC2_FDR) 31 32 u8 cr; /* I2C control redister */ 33 u8 res2[3]; 34 #define I2C_CR_MEN 0x80 35 #define I2C_CR_MIEN 0x40 36 #define I2C_CR_MSTA 0x20 37 #define I2C_CR_MTX 0x10 38 #define I2C_CR_TXAK 0x08 39 #define I2C_CR_RSTA 0x04 40 #define I2C_CR_BIT6 0x02 /* required for workaround A004447 */ 41 #define I2C_CR_BCST 0x01 42 43 u8 sr; /* I2C status register */ 44 u8 res3[3]; 45 #define I2C_SR_MCF 0x80 46 #define I2C_SR_MAAS 0x40 47 #define I2C_SR_MBB 0x20 48 #define I2C_SR_MAL 0x10 49 #define I2C_SR_BCSTM 0x08 50 #define I2C_SR_SRW 0x04 51 #define I2C_SR_MIF 0x02 52 #define I2C_SR_RXAK 0x01 53 54 u8 dr; /* I2C data register */ 55 u8 res4[3]; 56 #define I2C_DR 0xFF 57 #define I2C_DR_SHIFT 0 58 #define I2C_DR_RES ~(I2C_DR) 59 60 u8 dfsrr; /* I2C digital filter sampling rate register */ 61 u8 res5[3]; 62 #define I2C_DFSRR 0x3F 63 #define I2C_DFSRR_SHIFT 0 64 #define I2C_DFSRR_RES ~(I2C_DR) 65 66 /* Fill out the reserved block */ 67 u8 res6[0xE8]; 68 } fsl_i2c_t; 69 70 #ifdef CONFIG_DM_I2C 71 struct fsl_i2c_dev { 72 struct fsl_i2c_base __iomem *base; /* register base */ 73 u32 i2c_clk; 74 u32 index; 75 u8 slaveadd; 76 uint speed; 77 }; 78 #endif 79 80 #endif /* _ASM_I2C_H_ */ 81