1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * Freescale I2C Controller 3a47a12beSStefan Roese * 4a47a12beSStefan Roese * Copyright 2006 Freescale Semiconductor, Inc. 5a47a12beSStefan Roese * 6a47a12beSStefan Roese * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, 7a47a12beSStefan Roese * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), 8a47a12beSStefan Roese * and Jeff Brown. 9a47a12beSStefan Roese * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. 10a47a12beSStefan Roese * 115b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 12a47a12beSStefan Roese */ 13a47a12beSStefan Roese 14a47a12beSStefan Roese #ifndef _ASM_FSL_I2C_H_ 15a47a12beSStefan Roese #define _ASM_FSL_I2C_H_ 16a47a12beSStefan Roese 17a47a12beSStefan Roese #include <asm/types.h> 18a47a12beSStefan Roese 19*ec2c81c5Smario.six@gdsys.cc typedef struct fsl_i2c_base { 20a47a12beSStefan Roese 21a47a12beSStefan Roese u8 adr; /* I2C slave address */ 22a47a12beSStefan Roese u8 res0[3]; 23a47a12beSStefan Roese #define I2C_ADR 0xFE 24a47a12beSStefan Roese #define I2C_ADR_SHIFT 1 25a47a12beSStefan Roese #define I2C_ADR_RES ~(I2C_ADR) 26a47a12beSStefan Roese 27a47a12beSStefan Roese u8 fdr; /* I2C frequency divider register */ 28a47a12beSStefan Roese u8 res1[3]; 29a47a12beSStefan Roese #define IC2_FDR 0x3F 30a47a12beSStefan Roese #define IC2_FDR_SHIFT 0 31a47a12beSStefan Roese #define IC2_FDR_RES ~(IC2_FDR) 32a47a12beSStefan Roese 33a47a12beSStefan Roese u8 cr; /* I2C control redister */ 34a47a12beSStefan Roese u8 res2[3]; 35a47a12beSStefan Roese #define I2C_CR_MEN 0x80 36a47a12beSStefan Roese #define I2C_CR_MIEN 0x40 37a47a12beSStefan Roese #define I2C_CR_MSTA 0x20 38a47a12beSStefan Roese #define I2C_CR_MTX 0x10 39a47a12beSStefan Roese #define I2C_CR_TXAK 0x08 40a47a12beSStefan Roese #define I2C_CR_RSTA 0x04 419c3f77ebSChunhe Lan #define I2C_CR_BIT6 0x02 /* required for workaround A004447 */ 42a47a12beSStefan Roese #define I2C_CR_BCST 0x01 43a47a12beSStefan Roese 44a47a12beSStefan Roese u8 sr; /* I2C status register */ 45a47a12beSStefan Roese u8 res3[3]; 46a47a12beSStefan Roese #define I2C_SR_MCF 0x80 47a47a12beSStefan Roese #define I2C_SR_MAAS 0x40 48a47a12beSStefan Roese #define I2C_SR_MBB 0x20 49a47a12beSStefan Roese #define I2C_SR_MAL 0x10 50a47a12beSStefan Roese #define I2C_SR_BCSTM 0x08 51a47a12beSStefan Roese #define I2C_SR_SRW 0x04 52a47a12beSStefan Roese #define I2C_SR_MIF 0x02 53a47a12beSStefan Roese #define I2C_SR_RXAK 0x01 54a47a12beSStefan Roese 55a47a12beSStefan Roese u8 dr; /* I2C data register */ 56a47a12beSStefan Roese u8 res4[3]; 57a47a12beSStefan Roese #define I2C_DR 0xFF 58a47a12beSStefan Roese #define I2C_DR_SHIFT 0 59a47a12beSStefan Roese #define I2C_DR_RES ~(I2C_DR) 60a47a12beSStefan Roese 61a47a12beSStefan Roese u8 dfsrr; /* I2C digital filter sampling rate register */ 62a47a12beSStefan Roese u8 res5[3]; 63a47a12beSStefan Roese #define I2C_DFSRR 0x3F 64a47a12beSStefan Roese #define I2C_DFSRR_SHIFT 0 65a47a12beSStefan Roese #define I2C_DFSRR_RES ~(I2C_DR) 66a47a12beSStefan Roese 67a47a12beSStefan Roese /* Fill out the reserved block */ 68a47a12beSStefan Roese u8 res6[0xE8]; 69a47a12beSStefan Roese } fsl_i2c_t; 70a47a12beSStefan Roese 71a47a12beSStefan Roese #endif /* _ASM_I2C_H_ */ 72