1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #include <fsl_ddrc_version.h> 23 #define CONFIG_SYS_FSL_DDR_BE 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 28 /* Number of TLB CAM entries we have on FSL Book-E chips */ 29 #if defined(CONFIG_E500MC) 30 #define CONFIG_SYS_NUM_TLBCAMS 64 31 #elif defined(CONFIG_E500) 32 #define CONFIG_SYS_NUM_TLBCAMS 16 33 #endif 34 35 #if defined(CONFIG_MPC8536) 36 #define CONFIG_MAX_CPUS 1 37 #define CONFIG_SYS_FSL_NUM_LAWS 12 38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 39 #define CONFIG_SYS_FSL_SEC_COMPAT 2 40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 41 #define CONFIG_SYS_FSL_ERRATUM_A005125 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_FSL_DDRC_GEN1 47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 48 49 #elif defined(CONFIG_MPC8541) 50 #define CONFIG_MAX_CPUS 1 51 #define CONFIG_SYS_FSL_NUM_LAWS 8 52 #define CONFIG_SYS_FSL_DDRC_GEN1 53 #define CONFIG_SYS_FSL_SEC_COMPAT 2 54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 55 56 #elif defined(CONFIG_MPC8544) 57 #define CONFIG_MAX_CPUS 1 58 #define CONFIG_SYS_FSL_NUM_LAWS 10 59 #define CONFIG_SYS_FSL_DDRC_GEN2 60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 61 #define CONFIG_SYS_FSL_SEC_COMPAT 2 62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 63 #define CONFIG_SYS_FSL_ERRATUM_A005125 64 65 #elif defined(CONFIG_MPC8548) 66 #define CONFIG_MAX_CPUS 1 67 #define CONFIG_SYS_FSL_NUM_LAWS 10 68 #define CONFIG_SYS_FSL_DDRC_GEN2 69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 70 #define CONFIG_SYS_FSL_SEC_COMPAT 2 71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 78 #define CONFIG_SYS_FSL_RMU 79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 80 #define CONFIG_SYS_FSL_ERRATUM_A005125 81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 83 84 #elif defined(CONFIG_MPC8555) 85 #define CONFIG_MAX_CPUS 1 86 #define CONFIG_SYS_FSL_NUM_LAWS 8 87 #define CONFIG_SYS_FSL_DDRC_GEN1 88 #define CONFIG_SYS_FSL_SEC_COMPAT 2 89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 90 91 #elif defined(CONFIG_MPC8560) 92 #define CONFIG_MAX_CPUS 1 93 #define CONFIG_SYS_FSL_NUM_LAWS 8 94 #define CONFIG_SYS_FSL_DDRC_GEN1 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 96 97 #elif defined(CONFIG_MPC8568) 98 #define CONFIG_MAX_CPUS 1 99 #define CONFIG_SYS_FSL_NUM_LAWS 10 100 #define CONFIG_SYS_FSL_DDRC_GEN2 101 #define CONFIG_SYS_FSL_SEC_COMPAT 2 102 #define QE_MURAM_SIZE 0x10000UL 103 #define MAX_QE_RISC 2 104 #define QE_NUM_OF_SNUM 28 105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 109 #define CONFIG_SYS_FSL_RMU 110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 111 112 #elif defined(CONFIG_MPC8569) 113 #define CONFIG_MAX_CPUS 1 114 #define CONFIG_SYS_FSL_NUM_LAWS 10 115 #define CONFIG_SYS_FSL_SEC_COMPAT 2 116 #define QE_MURAM_SIZE 0x20000UL 117 #define MAX_QE_RISC 4 118 #define QE_NUM_OF_SNUM 46 119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 123 #define CONFIG_SYS_FSL_RMU 124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 125 #define CONFIG_SYS_FSL_ERRATUM_A005125 126 127 #elif defined(CONFIG_MPC8572) 128 #define CONFIG_MAX_CPUS 2 129 #define CONFIG_SYS_FSL_NUM_LAWS 12 130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 131 #define CONFIG_SYS_FSL_SEC_COMPAT 2 132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 135 #define CONFIG_SYS_FSL_ERRATUM_A005125 136 137 #elif defined(CONFIG_P1010) 138 #define CONFIG_MAX_CPUS 1 139 #define CONFIG_FSL_SDHC_V2_3 140 #define CONFIG_SYS_FSL_NUM_LAWS 12 141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 142 #define CONFIG_TSECV2 143 #define CONFIG_SYS_FSL_SEC_COMPAT 4 144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 145 #define CONFIG_NUM_DDR_CONTROLLERS 1 146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 155 #define CONFIG_SYS_FSL_ERRATUM_A005125 156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 157 #define CONFIG_SYS_FSL_ERRATUM_A007075 158 #define CONFIG_SYS_FSL_ERRATUM_A006261 159 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 160 #define CONFIG_ESDHC_HC_BLK_ADDR 161 162 /* P1011 is single core version of P1020 */ 163 #elif defined(CONFIG_P1011) 164 #define CONFIG_MAX_CPUS 1 165 #define CONFIG_SYS_FSL_NUM_LAWS 12 166 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 167 #define CONFIG_TSECV2 168 #define CONFIG_FSL_PCIE_DISABLE_ASPM 169 #define CONFIG_SYS_FSL_SEC_COMPAT 2 170 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 171 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 172 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 173 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 174 #define CONFIG_SYS_FSL_ERRATUM_A005125 175 176 /* P1012 is single core version of P1021 */ 177 #elif defined(CONFIG_P1012) 178 #define CONFIG_MAX_CPUS 1 179 #define CONFIG_SYS_FSL_NUM_LAWS 12 180 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 181 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 182 #define CONFIG_TSECV2 183 #define CONFIG_FSL_PCIE_DISABLE_ASPM 184 #define CONFIG_SYS_FSL_SEC_COMPAT 2 185 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 186 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 187 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 188 #define QE_MURAM_SIZE 0x6000UL 189 #define MAX_QE_RISC 1 190 #define QE_NUM_OF_SNUM 28 191 #define CONFIG_SYS_FSL_ERRATUM_A005125 192 193 /* P1013 is single core version of P1022 */ 194 #elif defined(CONFIG_P1013) 195 #define CONFIG_MAX_CPUS 1 196 #define CONFIG_SYS_FSL_NUM_LAWS 12 197 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 198 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 199 #define CONFIG_TSECV2 200 #define CONFIG_SYS_FSL_SEC_COMPAT 2 201 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 202 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 203 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 204 #define CONFIG_FSL_SATA_ERRATUM_A001 205 #define CONFIG_SYS_FSL_ERRATUM_A005125 206 207 #elif defined(CONFIG_P1014) 208 #define CONFIG_MAX_CPUS 1 209 #define CONFIG_FSL_SDHC_V2_3 210 #define CONFIG_SYS_FSL_NUM_LAWS 12 211 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 212 #define CONFIG_TSECV2 213 #define CONFIG_SYS_FSL_SEC_COMPAT 4 214 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 215 #define CONFIG_NUM_DDR_CONTROLLERS 1 216 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 217 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 218 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 219 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 220 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 221 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 222 223 /* P1017 is single core version of P1023 */ 224 #elif defined(CONFIG_P1017) 225 #define CONFIG_MAX_CPUS 1 226 #define CONFIG_SYS_FSL_NUM_LAWS 12 227 #define CONFIG_SYS_FSL_SEC_COMPAT 4 228 #define CONFIG_SYS_NUM_FMAN 1 229 #define CONFIG_SYS_NUM_FM1_DTSEC 2 230 #define CONFIG_NUM_DDR_CONTROLLERS 1 231 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 232 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 233 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 234 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 235 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 236 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 237 #define CONFIG_SYS_FSL_ERRATUM_A005125 238 239 #elif defined(CONFIG_P1020) 240 #define CONFIG_MAX_CPUS 2 241 #define CONFIG_SYS_FSL_NUM_LAWS 12 242 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 243 #define CONFIG_TSECV2 244 #define CONFIG_FSL_PCIE_DISABLE_ASPM 245 #define CONFIG_SYS_FSL_SEC_COMPAT 2 246 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 247 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 248 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 249 #define CONFIG_SYS_FSL_ERRATUM_A005125 250 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 251 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 252 #endif 253 254 #elif defined(CONFIG_P1021) 255 #define CONFIG_MAX_CPUS 2 256 #define CONFIG_SYS_FSL_NUM_LAWS 12 257 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 258 #define CONFIG_TSECV2 259 #define CONFIG_FSL_PCIE_DISABLE_ASPM 260 #define CONFIG_SYS_FSL_SEC_COMPAT 2 261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 262 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 263 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 264 #define QE_MURAM_SIZE 0x6000UL 265 #define MAX_QE_RISC 1 266 #define QE_NUM_OF_SNUM 28 267 #define CONFIG_SYS_FSL_ERRATUM_A005125 268 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 269 270 #elif defined(CONFIG_P1022) 271 #define CONFIG_MAX_CPUS 2 272 #define CONFIG_SYS_FSL_NUM_LAWS 12 273 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 274 #define CONFIG_TSECV2 275 #define CONFIG_SYS_FSL_SEC_COMPAT 2 276 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 277 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 278 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 279 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 280 #define CONFIG_FSL_SATA_ERRATUM_A001 281 #define CONFIG_SYS_FSL_ERRATUM_A005125 282 283 #elif defined(CONFIG_P1023) 284 #define CONFIG_MAX_CPUS 2 285 #define CONFIG_SYS_FSL_NUM_LAWS 12 286 #define CONFIG_SYS_FSL_SEC_COMPAT 4 287 #define CONFIG_SYS_NUM_FMAN 1 288 #define CONFIG_SYS_NUM_FM1_DTSEC 2 289 #define CONFIG_NUM_DDR_CONTROLLERS 1 290 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 291 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 292 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 293 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 294 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 295 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 296 #define CONFIG_SYS_FSL_ERRATUM_A005125 297 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 298 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 299 300 /* P1024 is lower end variant of P1020 */ 301 #elif defined(CONFIG_P1024) 302 #define CONFIG_MAX_CPUS 2 303 #define CONFIG_SYS_FSL_NUM_LAWS 12 304 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 305 #define CONFIG_TSECV2 306 #define CONFIG_FSL_PCIE_DISABLE_ASPM 307 #define CONFIG_SYS_FSL_SEC_COMPAT 2 308 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 309 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 310 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 311 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 312 #define CONFIG_SYS_FSL_ERRATUM_A005125 313 314 /* P1025 is lower end variant of P1021 */ 315 #elif defined(CONFIG_P1025) 316 #define CONFIG_MAX_CPUS 2 317 #define CONFIG_SYS_FSL_NUM_LAWS 12 318 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 319 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 320 #define CONFIG_TSECV2 321 #define CONFIG_FSL_PCIE_DISABLE_ASPM 322 #define CONFIG_SYS_FSL_SEC_COMPAT 2 323 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 324 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 325 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 326 #define QE_MURAM_SIZE 0x6000UL 327 #define MAX_QE_RISC 1 328 #define QE_NUM_OF_SNUM 28 329 #define CONFIG_SYS_FSL_ERRATUM_A005125 330 331 /* P2010 is single core version of P2020 */ 332 #elif defined(CONFIG_P2010) 333 #define CONFIG_MAX_CPUS 1 334 #define CONFIG_SYS_FSL_NUM_LAWS 12 335 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 336 #define CONFIG_SYS_FSL_SEC_COMPAT 2 337 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 338 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 339 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 340 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 341 #define CONFIG_SYS_FSL_ERRATUM_A005125 342 343 #elif defined(CONFIG_P2020) 344 #define CONFIG_MAX_CPUS 2 345 #define CONFIG_SYS_FSL_NUM_LAWS 12 346 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 347 #define CONFIG_SYS_FSL_SEC_COMPAT 2 348 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 349 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 350 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 351 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 352 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 353 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 354 #define CONFIG_SYS_FSL_RMU 355 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 356 #define CONFIG_SYS_FSL_ERRATUM_A005125 357 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 358 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 359 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 360 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 361 #define CONFIG_MAX_CPUS 4 362 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 363 #define CONFIG_SYS_FSL_NUM_LAWS 32 364 #define CONFIG_SYS_FSL_SEC_COMPAT 4 365 #define CONFIG_SYS_NUM_FMAN 1 366 #define CONFIG_SYS_NUM_FM1_DTSEC 5 367 #define CONFIG_SYS_NUM_FM1_10GEC 1 368 #define CONFIG_NUM_DDR_CONTROLLERS 1 369 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 370 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 371 #define CONFIG_SYS_FSL_TBCLK_DIV 32 372 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 373 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 374 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 375 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 376 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 377 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 378 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 379 #define CONFIG_SYS_FSL_ERRATUM_USB14 380 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 381 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 382 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 383 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 384 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 385 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 386 #define CONFIG_SYS_FSL_ERRATUM_A004510 387 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 388 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 389 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 390 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 391 #define CONFIG_SYS_FSL_ERRATUM_A004849 392 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 393 #define CONFIG_SYS_FSL_ERRATUM_A006261 394 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 395 396 #elif defined(CONFIG_PPC_P3041) 397 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 398 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 399 #define CONFIG_MAX_CPUS 4 400 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 401 #define CONFIG_SYS_FSL_NUM_LAWS 32 402 #define CONFIG_SYS_FSL_SEC_COMPAT 4 403 #define CONFIG_SYS_NUM_FMAN 1 404 #define CONFIG_SYS_NUM_FM1_DTSEC 5 405 #define CONFIG_SYS_NUM_FM1_10GEC 1 406 #define CONFIG_NUM_DDR_CONTROLLERS 1 407 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 408 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 409 #define CONFIG_SYS_FSL_TBCLK_DIV 32 410 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 411 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 412 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 413 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 414 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 415 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 416 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 417 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 418 #define CONFIG_SYS_FSL_ERRATUM_USB14 419 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 420 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 421 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 422 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 423 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 424 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 425 #define CONFIG_SYS_FSL_ERRATUM_A004510 426 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 427 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 428 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 429 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 430 #define CONFIG_SYS_FSL_ERRATUM_A004849 431 #define CONFIG_SYS_FSL_ERRATUM_A005812 432 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 433 #define CONFIG_SYS_FSL_ERRATUM_A006261 434 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 435 436 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 437 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 438 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 439 #define CONFIG_MAX_CPUS 8 440 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 441 #define CONFIG_SYS_FSL_NUM_LAWS 32 442 #define CONFIG_SYS_FSL_SEC_COMPAT 4 443 #define CONFIG_SYS_NUM_FMAN 2 444 #define CONFIG_SYS_NUM_FM1_DTSEC 4 445 #define CONFIG_SYS_NUM_FM2_DTSEC 4 446 #define CONFIG_SYS_NUM_FM1_10GEC 1 447 #define CONFIG_SYS_NUM_FM2_10GEC 1 448 #define CONFIG_NUM_DDR_CONTROLLERS 2 449 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 450 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 451 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 452 #define CONFIG_SYS_FSL_TBCLK_DIV 16 453 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 454 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 455 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 456 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 457 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 458 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 459 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 460 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 461 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 462 #define CONFIG_SYS_P4080_ERRATUM_CPU22 463 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 464 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 465 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 466 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 467 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 468 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 469 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 470 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 471 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 472 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 473 #define CONFIG_SYS_FSL_RMU 474 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 475 #define CONFIG_SYS_FSL_ERRATUM_A004510 476 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 477 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 478 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 479 #define CONFIG_SYS_FSL_ERRATUM_A004849 480 #define CONFIG_SYS_FSL_ERRATUM_A004580 481 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 482 #define CONFIG_SYS_FSL_ERRATUM_A005812 483 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 484 #define CONFIG_SYS_FSL_ERRATUM_A007075 485 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 486 487 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 488 #define CONFIG_SYS_PPC64 /* 64-bit core */ 489 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 490 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 491 #define CONFIG_MAX_CPUS 2 492 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 493 #define CONFIG_SYS_FSL_NUM_LAWS 32 494 #define CONFIG_SYS_FSL_SEC_COMPAT 4 495 #define CONFIG_SYS_NUM_FMAN 1 496 #define CONFIG_SYS_NUM_FM1_DTSEC 5 497 #define CONFIG_SYS_NUM_FM1_10GEC 1 498 #define CONFIG_NUM_DDR_CONTROLLERS 2 499 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 500 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 501 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 502 #define CONFIG_SYS_FSL_TBCLK_DIV 32 503 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 504 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 505 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 506 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 507 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 508 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 509 #define CONFIG_SYS_FSL_ERRATUM_USB14 510 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 511 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 512 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 513 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 514 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 515 #define CONFIG_SYS_FSL_ERRATUM_A004510 516 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 517 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 518 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 519 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 520 #define CONFIG_SYS_FSL_ERRATUM_A006261 521 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 522 523 #elif defined(CONFIG_PPC_P5040) 524 #define CONFIG_SYS_PPC64 525 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 526 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 527 #define CONFIG_MAX_CPUS 4 528 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 529 #define CONFIG_SYS_FSL_NUM_LAWS 32 530 #define CONFIG_SYS_FSL_SEC_COMPAT 4 531 #define CONFIG_SYS_NUM_FMAN 2 532 #define CONFIG_SYS_NUM_FM1_DTSEC 5 533 #define CONFIG_SYS_NUM_FM1_10GEC 1 534 #define CONFIG_SYS_NUM_FM2_DTSEC 5 535 #define CONFIG_SYS_NUM_FM2_10GEC 1 536 #define CONFIG_NUM_DDR_CONTROLLERS 2 537 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 538 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 539 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 540 #define CONFIG_SYS_FSL_TBCLK_DIV 16 541 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 542 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 543 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 544 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 545 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 546 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 547 #define CONFIG_SYS_FSL_ERRATUM_USB14 548 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 549 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 550 #define CONFIG_SYS_FSL_ERRATUM_A004699 551 #define CONFIG_SYS_FSL_ERRATUM_A004510 552 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 553 #define CONFIG_SYS_FSL_ERRATUM_A006261 554 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 555 #define CONFIG_SYS_FSL_ERRATUM_A005812 556 557 #elif defined(CONFIG_BSC9131) 558 #define CONFIG_MAX_CPUS 1 559 #define CONFIG_FSL_SDHC_V2_3 560 #define CONFIG_SYS_FSL_NUM_LAWS 12 561 #define CONFIG_TSECV2 562 #define CONFIG_SYS_FSL_SEC_COMPAT 4 563 #define CONFIG_NUM_DDR_CONTROLLERS 1 564 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 565 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 566 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 567 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 568 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 569 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 570 #define CONFIG_NAND_FSL_IFC 571 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 572 #define CONFIG_SYS_FSL_ERRATUM_A005125 573 #define CONFIG_ESDHC_HC_BLK_ADDR 574 575 #elif defined(CONFIG_BSC9132) 576 #define CONFIG_MAX_CPUS 2 577 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 578 #define CONFIG_FSL_SDHC_V2_3 579 #define CONFIG_SYS_FSL_NUM_LAWS 12 580 #define CONFIG_TSECV2 581 #define CONFIG_SYS_FSL_SEC_COMPAT 4 582 #define CONFIG_NUM_DDR_CONTROLLERS 2 583 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 584 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 585 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 586 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 587 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 588 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 589 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 590 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 591 #define CONFIG_NAND_FSL_IFC 592 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 593 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 594 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 595 #define CONFIG_SYS_FSL_ERRATUM_A005125 596 #define CONFIG_SYS_FSL_ERRATUM_A005434 597 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 598 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 599 #define CONFIG_ESDHC_HC_BLK_ADDR 600 601 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 602 defined(CONFIG_PPC_T4080) 603 #define CONFIG_E6500 604 #define CONFIG_SYS_PPC64 /* 64-bit core */ 605 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 606 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 607 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 608 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 609 #ifdef CONFIG_PPC_T4240 610 #define CONFIG_MAX_CPUS 12 611 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 612 #define CONFIG_SYS_NUM_FM1_DTSEC 8 613 #define CONFIG_SYS_NUM_FM1_10GEC 2 614 #define CONFIG_SYS_NUM_FM2_DTSEC 8 615 #define CONFIG_SYS_NUM_FM2_10GEC 2 616 #define CONFIG_NUM_DDR_CONTROLLERS 3 617 #else 618 #define CONFIG_SYS_NUM_FM1_DTSEC 6 619 #define CONFIG_SYS_NUM_FM1_10GEC 1 620 #define CONFIG_SYS_NUM_FM2_DTSEC 8 621 #define CONFIG_SYS_NUM_FM2_10GEC 1 622 #define CONFIG_NUM_DDR_CONTROLLERS 2 623 #if defined(CONFIG_PPC_T4160) 624 #define CONFIG_MAX_CPUS 8 625 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 626 #elif defined(CONFIG_PPC_T4080) 627 #define CONFIG_MAX_CPUS 4 628 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } 629 #endif 630 #endif 631 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 632 #define CONFIG_SYS_FSL_NUM_LAWS 32 633 #define CONFIG_SYS_FSL_SRDS_1 634 #define CONFIG_SYS_FSL_SRDS_2 635 #define CONFIG_SYS_FSL_SRDS_3 636 #define CONFIG_SYS_FSL_SRDS_4 637 #define CONFIG_SYS_FSL_SEC_COMPAT 4 638 #define CONFIG_SYS_NUM_FMAN 2 639 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 640 #define CONFIG_SYS_PME_CLK 0 641 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 642 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 643 #define CONFIG_SYS_FMAN_V3 644 #define CONFIG_SYS_FM1_CLK 3 645 #define CONFIG_SYS_FM2_CLK 3 646 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 647 #define CONFIG_SYS_FSL_TBCLK_DIV 16 648 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 649 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 650 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 651 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 652 #define CONFIG_SYS_FSL_SRIO_LIODN 653 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 654 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 655 #define CONFIG_SYS_FSL_ERRATUM_A004468 656 #define CONFIG_SYS_FSL_ERRATUM_A_004934 657 #define CONFIG_SYS_FSL_ERRATUM_A005871 658 #define CONFIG_SYS_FSL_ERRATUM_A006261 659 #define CONFIG_SYS_FSL_ERRATUM_A006379 660 #define CONFIG_SYS_FSL_ERRATUM_A006593 661 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 662 #define CONFIG_SYS_FSL_PCI_VER_3_X 663 664 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 665 #define CONFIG_E6500 666 #define CONFIG_SYS_PPC64 /* 64-bit core */ 667 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 668 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 669 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 670 #define CONFIG_SYS_FSL_NUM_LAWS 32 671 #define CONFIG_SYS_FSL_SRDS_1 672 #define CONFIG_SYS_FSL_SRDS_2 673 #define CONFIG_SYS_FSL_SEC_COMPAT 4 674 #define CONFIG_SYS_NUM_FMAN 1 675 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 676 #define CONFIG_SYS_FM1_CLK 0 677 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 678 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 679 #define CONFIG_SYS_FMAN_V3 680 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 681 #define CONFIG_SYS_FSL_TBCLK_DIV 16 682 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 683 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 684 #define CONFIG_SYS_FSL_ERRATUM_A_004934 685 #define CONFIG_SYS_FSL_ERRATUM_A005871 686 #define CONFIG_SYS_FSL_ERRATUM_A006379 687 #define CONFIG_SYS_FSL_ERRATUM_A006593 688 #define CONFIG_SYS_FSL_ERRATUM_A007075 689 #define CONFIG_SYS_FSL_ERRATUM_A006475 690 #define CONFIG_SYS_FSL_ERRATUM_A006384 691 #define CONFIG_SYS_FSL_ERRATUM_A007212 692 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 693 694 #ifdef CONFIG_PPC_B4860 695 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 696 #define CONFIG_MAX_CPUS 4 697 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 698 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 699 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 700 #define CONFIG_SYS_NUM_FM1_DTSEC 6 701 #define CONFIG_SYS_NUM_FM1_10GEC 2 702 #define CONFIG_NUM_DDR_CONTROLLERS 2 703 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 704 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 705 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 706 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 707 #define CONFIG_SYS_FSL_SRIO_LIODN 708 #else 709 #define CONFIG_MAX_CPUS 2 710 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 711 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 712 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 713 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 714 #define CONFIG_SYS_NUM_FM1_DTSEC 4 715 #define CONFIG_SYS_NUM_FM1_10GEC 0 716 #define CONFIG_NUM_DDR_CONTROLLERS 1 717 #endif 718 719 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 720 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 721 #define CONFIG_E5500 722 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 723 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 724 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 725 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 726 #ifdef CONFIG_SYS_FSL_DDR4 727 #define CONFIG_SYS_FSL_DDRC_GEN4 728 #endif 729 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 730 #define CONFIG_MAX_CPUS 4 731 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 732 #define CONFIG_MAX_CPUS 2 733 #endif 734 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 735 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 736 #define CONFIG_SYS_SDHC_CLOCK 0 737 #define CONFIG_SYS_FSL_NUM_LAWS 16 738 #define CONFIG_SYS_FSL_SRDS_1 739 #define CONFIG_SYS_FSL_SEC_COMPAT 5 740 #define CONFIG_SYS_NUM_FMAN 1 741 #define CONFIG_SYS_NUM_FM1_DTSEC 5 742 #define CONFIG_NUM_DDR_CONTROLLERS 1 743 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 744 #define CONFIG_PME_PLAT_CLK_DIV 2 745 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 746 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 747 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 748 #define CONFIG_SYS_FMAN_V3 749 #define CONFIG_FM_PLAT_CLK_DIV 1 750 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 751 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 752 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 753 #define CONFIG_SYS_FSL_TBCLK_DIV 16 754 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 755 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 756 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 757 #define CONFIG_SYS_FSL_ERRATUM_A006261 758 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 759 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 760 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 761 #define QE_MURAM_SIZE 0x6000UL 762 #define MAX_QE_RISC 1 763 #define QE_NUM_OF_SNUM 28 764 765 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 766 #define CONFIG_E6500 767 #define CONFIG_SYS_PPC64 /* 64-bit core */ 768 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 769 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 770 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 771 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 772 #define CONFIG_SYS_FSL_QMAN_V3 773 #define CONFIG_MAX_CPUS 4 774 #define CONFIG_SYS_FSL_NUM_LAWS 32 775 #define CONFIG_SYS_FSL_SEC_COMPAT 4 776 #define CONFIG_SYS_NUM_FMAN 1 777 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 778 #define CONFIG_SYS_FSL_SRDS_1 779 #define CONFIG_SYS_FSL_PCI_VER_3_X 780 #if defined(CONFIG_PPC_T2080) 781 #define CONFIG_SYS_NUM_FM1_DTSEC 8 782 #define CONFIG_SYS_NUM_FM1_10GEC 4 783 #define CONFIG_SYS_FSL_SRDS_2 784 #define CONFIG_SYS_FSL_SRIO_LIODN 785 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 786 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 787 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 788 #elif defined(CONFIG_PPC_T2081) 789 #define CONFIG_SYS_NUM_FM1_DTSEC 6 790 #define CONFIG_SYS_NUM_FM1_10GEC 2 791 #endif 792 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 793 #define CONFIG_NUM_DDR_CONTROLLERS 1 794 #define CONFIG_PME_PLAT_CLK_DIV 1 795 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 796 #define CONFIG_SYS_FM1_CLK 0 797 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 798 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 799 #define CONFIG_SYS_FMAN_V3 800 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 801 #define CONFIG_SYS_FSL_TBCLK_DIV 16 802 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 803 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 804 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 805 #define CONFIG_SYS_FSL_ERRATUM_A007212 806 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 807 #define CONFIG_SYS_FSL_SFP_VER_3_0 808 #define CONFIG_SYS_FSL_ISBC_VER 2 809 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 810 #define CONFIG_SYS_FSL_ERRATUM_A006261 811 #define CONFIG_SYS_FSL_ERRATUM_A006593 812 #define CONFIG_SYS_FSL_ERRATUM_A006379 813 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 814 815 816 #elif defined(CONFIG_PPC_C29X) 817 #define CONFIG_MAX_CPUS 1 818 #define CONFIG_FSL_SDHC_V2_3 819 #define CONFIG_SYS_FSL_NUM_LAWS 12 820 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 821 #define CONFIG_TSECV2_1 822 #define CONFIG_SYS_FSL_SEC_COMPAT 6 823 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 824 #define CONFIG_NUM_DDR_CONTROLLERS 1 825 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 826 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 827 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 828 #define CONFIG_SYS_FSL_ERRATUM_A005125 829 830 #elif defined(CONFIG_QEMU_E500) 831 #define CONFIG_MAX_CPUS 1 832 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 833 834 #else 835 #error Processor type not defined for this platform 836 #endif 837 838 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 839 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 840 #endif 841 842 #ifdef CONFIG_E6500 843 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 844 #else 845 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 846 #endif 847 848 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 849 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 850 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 851 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 852 #define CONFIG_SYS_FSL_DDRC_GEN3 853 #endif 854 855 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 856