1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #define FSL_DDR_VER_4_7 47 23 #define FSL_DDR_VER_5_0 50 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 28 /* Number of TLB CAM entries we have on FSL Book-E chips */ 29 #if defined(CONFIG_E500MC) 30 #define CONFIG_SYS_NUM_TLBCAMS 64 31 #elif defined(CONFIG_E500) 32 #define CONFIG_SYS_NUM_TLBCAMS 16 33 #endif 34 35 #if defined(CONFIG_MPC8536) 36 #define CONFIG_MAX_CPUS 1 37 #define CONFIG_SYS_FSL_NUM_LAWS 12 38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 39 #define CONFIG_SYS_FSL_SEC_COMPAT 2 40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 41 #define CONFIG_SYS_FSL_ERRATUM_A005125 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_FSL_DDRC_GEN1 47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 48 49 #elif defined(CONFIG_MPC8541) 50 #define CONFIG_MAX_CPUS 1 51 #define CONFIG_SYS_FSL_NUM_LAWS 8 52 #define CONFIG_SYS_FSL_DDRC_GEN1 53 #define CONFIG_SYS_FSL_SEC_COMPAT 2 54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 55 56 #elif defined(CONFIG_MPC8544) 57 #define CONFIG_MAX_CPUS 1 58 #define CONFIG_SYS_FSL_NUM_LAWS 10 59 #define CONFIG_SYS_FSL_DDRC_GEN2 60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 61 #define CONFIG_SYS_FSL_SEC_COMPAT 2 62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 63 #define CONFIG_SYS_FSL_ERRATUM_A005125 64 65 #elif defined(CONFIG_MPC8548) 66 #define CONFIG_MAX_CPUS 1 67 #define CONFIG_SYS_FSL_NUM_LAWS 10 68 #define CONFIG_SYS_FSL_DDRC_GEN2 69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 70 #define CONFIG_SYS_FSL_SEC_COMPAT 2 71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 78 #define CONFIG_SYS_FSL_RMU 79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 80 #define CONFIG_SYS_FSL_ERRATUM_A005125 81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 83 84 #elif defined(CONFIG_MPC8555) 85 #define CONFIG_MAX_CPUS 1 86 #define CONFIG_SYS_FSL_NUM_LAWS 8 87 #define CONFIG_SYS_FSL_DDRC_GEN1 88 #define CONFIG_SYS_FSL_SEC_COMPAT 2 89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 90 91 #elif defined(CONFIG_MPC8560) 92 #define CONFIG_MAX_CPUS 1 93 #define CONFIG_SYS_FSL_NUM_LAWS 8 94 #define CONFIG_SYS_FSL_DDRC_GEN1 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 96 97 #elif defined(CONFIG_MPC8568) 98 #define CONFIG_MAX_CPUS 1 99 #define CONFIG_SYS_FSL_NUM_LAWS 10 100 #define CONFIG_SYS_FSL_DDRC_GEN2 101 #define CONFIG_SYS_FSL_SEC_COMPAT 2 102 #define QE_MURAM_SIZE 0x10000UL 103 #define MAX_QE_RISC 2 104 #define QE_NUM_OF_SNUM 28 105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 109 #define CONFIG_SYS_FSL_RMU 110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 111 112 #elif defined(CONFIG_MPC8569) 113 #define CONFIG_MAX_CPUS 1 114 #define CONFIG_SYS_FSL_NUM_LAWS 10 115 #define CONFIG_SYS_FSL_SEC_COMPAT 2 116 #define QE_MURAM_SIZE 0x20000UL 117 #define MAX_QE_RISC 4 118 #define QE_NUM_OF_SNUM 46 119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 123 #define CONFIG_SYS_FSL_RMU 124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 125 #define CONFIG_SYS_FSL_ERRATUM_A005125 126 127 #elif defined(CONFIG_MPC8572) 128 #define CONFIG_MAX_CPUS 2 129 #define CONFIG_SYS_FSL_NUM_LAWS 12 130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 131 #define CONFIG_SYS_FSL_SEC_COMPAT 2 132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 135 #define CONFIG_SYS_FSL_ERRATUM_A005125 136 137 #elif defined(CONFIG_P1010) 138 #define CONFIG_MAX_CPUS 1 139 #define CONFIG_FSL_SDHC_V2_3 140 #define CONFIG_SYS_FSL_NUM_LAWS 12 141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 142 #define CONFIG_TSECV2 143 #define CONFIG_SYS_FSL_SEC_COMPAT 4 144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 145 #define CONFIG_NUM_DDR_CONTROLLERS 1 146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 155 #define CONFIG_SYS_FSL_ERRATUM_A005125 156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 157 #define CONFIG_SYS_FSL_ERRATUM_A006261 158 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 159 #define CONFIG_ESDHC_HC_BLK_ADDR 160 161 /* P1011 is single core version of P1020 */ 162 #elif defined(CONFIG_P1011) 163 #define CONFIG_MAX_CPUS 1 164 #define CONFIG_SYS_FSL_NUM_LAWS 12 165 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 166 #define CONFIG_TSECV2 167 #define CONFIG_FSL_PCIE_DISABLE_ASPM 168 #define CONFIG_SYS_FSL_SEC_COMPAT 2 169 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 170 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 171 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 172 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 173 #define CONFIG_SYS_FSL_ERRATUM_A005125 174 175 /* P1012 is single core version of P1021 */ 176 #elif defined(CONFIG_P1012) 177 #define CONFIG_MAX_CPUS 1 178 #define CONFIG_SYS_FSL_NUM_LAWS 12 179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 180 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 181 #define CONFIG_TSECV2 182 #define CONFIG_FSL_PCIE_DISABLE_ASPM 183 #define CONFIG_SYS_FSL_SEC_COMPAT 2 184 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 187 #define QE_MURAM_SIZE 0x6000UL 188 #define MAX_QE_RISC 1 189 #define QE_NUM_OF_SNUM 28 190 #define CONFIG_SYS_FSL_ERRATUM_A005125 191 192 /* P1013 is single core version of P1022 */ 193 #elif defined(CONFIG_P1013) 194 #define CONFIG_MAX_CPUS 1 195 #define CONFIG_SYS_FSL_NUM_LAWS 12 196 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 197 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 198 #define CONFIG_TSECV2 199 #define CONFIG_SYS_FSL_SEC_COMPAT 2 200 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 201 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 202 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 203 #define CONFIG_FSL_SATA_ERRATUM_A001 204 #define CONFIG_SYS_FSL_ERRATUM_A005125 205 206 #elif defined(CONFIG_P1014) 207 #define CONFIG_MAX_CPUS 1 208 #define CONFIG_FSL_SDHC_V2_3 209 #define CONFIG_SYS_FSL_NUM_LAWS 12 210 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 211 #define CONFIG_TSECV2 212 #define CONFIG_SYS_FSL_SEC_COMPAT 4 213 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 214 #define CONFIG_NUM_DDR_CONTROLLERS 1 215 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 216 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 217 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 218 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 219 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 220 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 221 222 /* P1017 is single core version of P1023 */ 223 #elif defined(CONFIG_P1017) 224 #define CONFIG_MAX_CPUS 1 225 #define CONFIG_SYS_FSL_NUM_LAWS 12 226 #define CONFIG_SYS_FSL_SEC_COMPAT 4 227 #define CONFIG_SYS_NUM_FMAN 1 228 #define CONFIG_SYS_NUM_FM1_DTSEC 2 229 #define CONFIG_NUM_DDR_CONTROLLERS 1 230 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 231 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 232 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 233 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 234 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 235 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 236 #define CONFIG_SYS_FSL_ERRATUM_A005125 237 238 #elif defined(CONFIG_P1020) 239 #define CONFIG_MAX_CPUS 2 240 #define CONFIG_SYS_FSL_NUM_LAWS 12 241 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 242 #define CONFIG_TSECV2 243 #define CONFIG_FSL_PCIE_DISABLE_ASPM 244 #define CONFIG_SYS_FSL_SEC_COMPAT 2 245 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 246 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 247 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 248 #define CONFIG_SYS_FSL_ERRATUM_A005125 249 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 250 251 #elif defined(CONFIG_P1021) 252 #define CONFIG_MAX_CPUS 2 253 #define CONFIG_SYS_FSL_NUM_LAWS 12 254 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 255 #define CONFIG_TSECV2 256 #define CONFIG_FSL_PCIE_DISABLE_ASPM 257 #define CONFIG_SYS_FSL_SEC_COMPAT 2 258 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 259 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 260 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 261 #define QE_MURAM_SIZE 0x6000UL 262 #define MAX_QE_RISC 1 263 #define QE_NUM_OF_SNUM 28 264 #define CONFIG_SYS_FSL_ERRATUM_A005125 265 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 266 267 #elif defined(CONFIG_P1022) 268 #define CONFIG_MAX_CPUS 2 269 #define CONFIG_SYS_FSL_NUM_LAWS 12 270 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 271 #define CONFIG_TSECV2 272 #define CONFIG_SYS_FSL_SEC_COMPAT 2 273 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 274 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 275 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 276 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 277 #define CONFIG_FSL_SATA_ERRATUM_A001 278 #define CONFIG_SYS_FSL_ERRATUM_A005125 279 280 #elif defined(CONFIG_P1023) 281 #define CONFIG_MAX_CPUS 2 282 #define CONFIG_SYS_FSL_NUM_LAWS 12 283 #define CONFIG_SYS_FSL_SEC_COMPAT 4 284 #define CONFIG_SYS_NUM_FMAN 1 285 #define CONFIG_SYS_NUM_FM1_DTSEC 2 286 #define CONFIG_NUM_DDR_CONTROLLERS 1 287 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 288 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 289 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 290 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 291 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 292 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 293 #define CONFIG_SYS_FSL_ERRATUM_A005125 294 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 295 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 296 297 /* P1024 is lower end variant of P1020 */ 298 #elif defined(CONFIG_P1024) 299 #define CONFIG_MAX_CPUS 2 300 #define CONFIG_SYS_FSL_NUM_LAWS 12 301 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 302 #define CONFIG_TSECV2 303 #define CONFIG_FSL_PCIE_DISABLE_ASPM 304 #define CONFIG_SYS_FSL_SEC_COMPAT 2 305 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 306 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 307 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 308 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 309 #define CONFIG_SYS_FSL_ERRATUM_A005125 310 311 /* P1025 is lower end variant of P1021 */ 312 #elif defined(CONFIG_P1025) 313 #define CONFIG_MAX_CPUS 2 314 #define CONFIG_SYS_FSL_NUM_LAWS 12 315 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 316 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 317 #define CONFIG_TSECV2 318 #define CONFIG_FSL_PCIE_DISABLE_ASPM 319 #define CONFIG_SYS_FSL_SEC_COMPAT 2 320 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 321 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 322 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 323 #define QE_MURAM_SIZE 0x6000UL 324 #define MAX_QE_RISC 1 325 #define QE_NUM_OF_SNUM 28 326 #define CONFIG_SYS_FSL_ERRATUM_A005125 327 328 /* P2010 is single core version of P2020 */ 329 #elif defined(CONFIG_P2010) 330 #define CONFIG_MAX_CPUS 1 331 #define CONFIG_SYS_FSL_NUM_LAWS 12 332 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 333 #define CONFIG_SYS_FSL_SEC_COMPAT 2 334 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 335 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 336 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 337 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 338 #define CONFIG_SYS_FSL_ERRATUM_A005125 339 340 #elif defined(CONFIG_P2020) 341 #define CONFIG_MAX_CPUS 2 342 #define CONFIG_SYS_FSL_NUM_LAWS 12 343 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 344 #define CONFIG_SYS_FSL_SEC_COMPAT 2 345 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 346 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 347 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 348 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 349 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 350 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 351 #define CONFIG_SYS_FSL_RMU 352 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 353 #define CONFIG_SYS_FSL_ERRATUM_A005125 354 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 355 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 356 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 357 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 358 #define CONFIG_MAX_CPUS 4 359 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 360 #define CONFIG_SYS_FSL_NUM_LAWS 32 361 #define CONFIG_SYS_FSL_SEC_COMPAT 4 362 #define CONFIG_SYS_NUM_FMAN 1 363 #define CONFIG_SYS_NUM_FM1_DTSEC 5 364 #define CONFIG_SYS_NUM_FM1_10GEC 1 365 #define CONFIG_NUM_DDR_CONTROLLERS 1 366 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 367 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 368 #define CONFIG_SYS_FSL_TBCLK_DIV 32 369 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 370 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 371 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 372 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 373 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 374 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 375 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 376 #define CONFIG_SYS_FSL_ERRATUM_USB14 377 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 378 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 379 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 380 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 381 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 382 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 383 #define CONFIG_SYS_FSL_ERRATUM_A004510 384 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 385 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 386 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 387 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 388 #define CONFIG_SYS_FSL_ERRATUM_A004849 389 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 390 #define CONFIG_SYS_FSL_ERRATUM_A006261 391 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 392 393 #elif defined(CONFIG_PPC_P3041) 394 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 395 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 396 #define CONFIG_MAX_CPUS 4 397 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 398 #define CONFIG_SYS_FSL_NUM_LAWS 32 399 #define CONFIG_SYS_FSL_SEC_COMPAT 4 400 #define CONFIG_SYS_NUM_FMAN 1 401 #define CONFIG_SYS_NUM_FM1_DTSEC 5 402 #define CONFIG_SYS_NUM_FM1_10GEC 1 403 #define CONFIG_NUM_DDR_CONTROLLERS 1 404 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 405 #define CONFIG_SYS_FSL_TBCLK_DIV 32 406 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 407 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 408 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 409 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 410 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 411 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 412 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 413 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 414 #define CONFIG_SYS_FSL_ERRATUM_USB14 415 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 416 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 417 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 418 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 419 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 420 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 421 #define CONFIG_SYS_FSL_ERRATUM_A004510 422 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 423 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 424 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 425 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 426 #define CONFIG_SYS_FSL_ERRATUM_A004849 427 #define CONFIG_SYS_FSL_ERRATUM_A005812 428 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 429 #define CONFIG_SYS_FSL_ERRATUM_A006261 430 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 431 432 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 433 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 434 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 435 #define CONFIG_MAX_CPUS 8 436 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 437 #define CONFIG_SYS_FSL_NUM_LAWS 32 438 #define CONFIG_SYS_FSL_SEC_COMPAT 4 439 #define CONFIG_SYS_NUM_FMAN 2 440 #define CONFIG_SYS_NUM_FM1_DTSEC 4 441 #define CONFIG_SYS_NUM_FM2_DTSEC 4 442 #define CONFIG_SYS_NUM_FM1_10GEC 1 443 #define CONFIG_SYS_NUM_FM2_10GEC 1 444 #define CONFIG_NUM_DDR_CONTROLLERS 2 445 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 446 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 447 #define CONFIG_SYS_FSL_TBCLK_DIV 16 448 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 449 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 450 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 451 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 452 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 453 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 454 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 455 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 456 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 457 #define CONFIG_SYS_P4080_ERRATUM_CPU22 458 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 459 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 460 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 461 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 462 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 463 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 464 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 465 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 466 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 467 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 468 #define CONFIG_SYS_FSL_RMU 469 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 470 #define CONFIG_SYS_FSL_ERRATUM_A004510 471 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 472 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 473 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 474 #define CONFIG_SYS_FSL_ERRATUM_A004849 475 #define CONFIG_SYS_FSL_ERRATUM_A004580 476 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 477 #define CONFIG_SYS_FSL_ERRATUM_A005812 478 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 479 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 480 481 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 482 #define CONFIG_SYS_PPC64 /* 64-bit core */ 483 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 484 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 485 #define CONFIG_MAX_CPUS 2 486 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 487 #define CONFIG_SYS_FSL_NUM_LAWS 32 488 #define CONFIG_SYS_FSL_SEC_COMPAT 4 489 #define CONFIG_SYS_NUM_FMAN 1 490 #define CONFIG_SYS_NUM_FM1_DTSEC 5 491 #define CONFIG_SYS_NUM_FM1_10GEC 1 492 #define CONFIG_NUM_DDR_CONTROLLERS 2 493 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 494 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 495 #define CONFIG_SYS_FSL_TBCLK_DIV 32 496 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 497 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 498 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 499 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 500 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 501 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 502 #define CONFIG_SYS_FSL_ERRATUM_USB14 503 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 504 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 505 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 506 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 507 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 508 #define CONFIG_SYS_FSL_ERRATUM_A004510 509 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 510 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 511 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 512 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 513 #define CONFIG_SYS_FSL_ERRATUM_A006261 514 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 515 516 #elif defined(CONFIG_PPC_P5040) 517 #define CONFIG_SYS_PPC64 518 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 519 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 520 #define CONFIG_MAX_CPUS 4 521 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 522 #define CONFIG_SYS_FSL_NUM_LAWS 32 523 #define CONFIG_SYS_FSL_SEC_COMPAT 4 524 #define CONFIG_SYS_NUM_FMAN 2 525 #define CONFIG_SYS_NUM_FM1_DTSEC 5 526 #define CONFIG_SYS_NUM_FM1_10GEC 1 527 #define CONFIG_SYS_NUM_FM2_DTSEC 5 528 #define CONFIG_SYS_NUM_FM2_10GEC 1 529 #define CONFIG_NUM_DDR_CONTROLLERS 2 530 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 531 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 532 #define CONFIG_SYS_FSL_TBCLK_DIV 16 533 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 534 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 535 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 536 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 537 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 538 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 539 #define CONFIG_SYS_FSL_ERRATUM_USB14 540 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 541 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 542 #define CONFIG_SYS_FSL_ERRATUM_A004699 543 #define CONFIG_SYS_FSL_ERRATUM_A004510 544 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 545 #define CONFIG_SYS_FSL_ERRATUM_A006261 546 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 547 #define CONFIG_SYS_FSL_ERRATUM_A005812 548 549 #elif defined(CONFIG_BSC9131) 550 #define CONFIG_MAX_CPUS 1 551 #define CONFIG_FSL_SDHC_V2_3 552 #define CONFIG_SYS_FSL_NUM_LAWS 12 553 #define CONFIG_TSECV2 554 #define CONFIG_SYS_FSL_SEC_COMPAT 4 555 #define CONFIG_NUM_DDR_CONTROLLERS 1 556 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 557 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 558 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 559 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 560 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 561 #define CONFIG_NAND_FSL_IFC 562 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 563 #define CONFIG_SYS_FSL_ERRATUM_A005125 564 #define CONFIG_ESDHC_HC_BLK_ADDR 565 566 #elif defined(CONFIG_BSC9132) 567 #define CONFIG_MAX_CPUS 2 568 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 569 #define CONFIG_FSL_SDHC_V2_3 570 #define CONFIG_SYS_FSL_NUM_LAWS 12 571 #define CONFIG_TSECV2 572 #define CONFIG_SYS_FSL_SEC_COMPAT 4 573 #define CONFIG_NUM_DDR_CONTROLLERS 2 574 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 575 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 576 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 577 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 578 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 579 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 580 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 581 #define CONFIG_NAND_FSL_IFC 582 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 583 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 584 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 585 #define CONFIG_SYS_FSL_ERRATUM_A005125 586 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 587 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 588 #define CONFIG_ESDHC_HC_BLK_ADDR 589 590 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 591 #define CONFIG_E6500 592 #define CONFIG_SYS_PPC64 /* 64-bit core */ 593 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 594 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 595 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 596 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 597 #ifdef CONFIG_PPC_T4240 598 #define CONFIG_MAX_CPUS 12 599 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 600 #define CONFIG_SYS_NUM_FM1_DTSEC 8 601 #define CONFIG_SYS_NUM_FM1_10GEC 2 602 #define CONFIG_SYS_NUM_FM2_DTSEC 8 603 #define CONFIG_SYS_NUM_FM2_10GEC 2 604 #define CONFIG_NUM_DDR_CONTROLLERS 3 605 #else 606 #define CONFIG_MAX_CPUS 8 607 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 608 #define CONFIG_SYS_NUM_FM1_DTSEC 7 609 #define CONFIG_SYS_NUM_FM1_10GEC 1 610 #define CONFIG_SYS_NUM_FM2_DTSEC 7 611 #define CONFIG_SYS_NUM_FM2_10GEC 1 612 #define CONFIG_NUM_DDR_CONTROLLERS 2 613 #endif 614 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 615 #define CONFIG_SYS_FSL_NUM_LAWS 32 616 #define CONFIG_SYS_FSL_SRDS_1 617 #define CONFIG_SYS_FSL_SRDS_2 618 #define CONFIG_SYS_FSL_SRDS_3 619 #define CONFIG_SYS_FSL_SRDS_4 620 #define CONFIG_SYS_FSL_SEC_COMPAT 4 621 #define CONFIG_SYS_NUM_FMAN 2 622 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 623 #define CONFIG_SYS_PME_CLK 0 624 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 625 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 626 #define CONFIG_SYS_FMAN_V3 627 #define CONFIG_SYS_FM1_CLK 3 628 #define CONFIG_SYS_FM2_CLK 3 629 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 630 #define CONFIG_SYS_FSL_TBCLK_DIV 16 631 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 632 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 633 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 634 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 635 #define CONFIG_SYS_FSL_SRIO_LIODN 636 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 637 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 638 #define CONFIG_SYS_FSL_ERRATUM_A004468 639 #define CONFIG_SYS_FSL_ERRATUM_A_004934 640 #define CONFIG_SYS_FSL_ERRATUM_A005871 641 #define CONFIG_SYS_FSL_ERRATUM_A006261 642 #define CONFIG_SYS_FSL_ERRATUM_A006379 643 #define CONFIG_SYS_FSL_ERRATUM_A006593 644 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 645 #define CONFIG_SYS_FSL_PCI_VER_3_X 646 647 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 648 #define CONFIG_E6500 649 #define CONFIG_SYS_PPC64 /* 64-bit core */ 650 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 651 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 652 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 653 #define CONFIG_SYS_FSL_NUM_LAWS 32 654 #define CONFIG_SYS_FSL_SRDS_1 655 #define CONFIG_SYS_FSL_SRDS_2 656 #define CONFIG_SYS_FSL_SEC_COMPAT 4 657 #define CONFIG_SYS_NUM_FMAN 1 658 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 659 #define CONFIG_SYS_FM1_CLK 0 660 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 661 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 662 #define CONFIG_SYS_FMAN_V3 663 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 664 #define CONFIG_SYS_FSL_TBCLK_DIV 16 665 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 666 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 667 #define CONFIG_SYS_FSL_ERRATUM_A_004934 668 #define CONFIG_SYS_FSL_ERRATUM_A005871 669 #define CONFIG_SYS_FSL_ERRATUM_A006379 670 #define CONFIG_SYS_FSL_ERRATUM_A006593 671 #define CONFIG_SYS_FSL_ERRATUM_A006475 672 #define CONFIG_SYS_FSL_ERRATUM_A006384 673 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 674 675 #ifdef CONFIG_PPC_B4860 676 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 677 #define CONFIG_MAX_CPUS 4 678 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 679 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 680 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 681 #define CONFIG_SYS_NUM_FM1_DTSEC 6 682 #define CONFIG_SYS_NUM_FM1_10GEC 2 683 #define CONFIG_NUM_DDR_CONTROLLERS 2 684 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 685 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 686 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 687 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 688 #define CONFIG_SYS_FSL_SRIO_LIODN 689 #else 690 #define CONFIG_MAX_CPUS 2 691 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 692 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 693 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 694 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 695 #define CONFIG_SYS_NUM_FM1_DTSEC 4 696 #define CONFIG_SYS_NUM_FM1_10GEC 0 697 #define CONFIG_NUM_DDR_CONTROLLERS 1 698 #endif 699 700 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 701 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 702 #define CONFIG_E5500 703 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 704 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 705 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 706 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 707 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 708 #define CONFIG_MAX_CPUS 4 709 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 710 #define CONFIG_MAX_CPUS 2 711 #endif 712 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 713 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 714 #define CONFIG_SYS_SDHC_CLOCK 0 715 #define CONFIG_SYS_FSL_NUM_LAWS 16 716 #define CONFIG_SYS_FSL_SRDS_1 717 #define CONFIG_SYS_FSL_SEC_COMPAT 5 718 #define CONFIG_SYS_NUM_FMAN 1 719 #define CONFIG_SYS_NUM_FM1_DTSEC 5 720 #define CONFIG_NUM_DDR_CONTROLLERS 1 721 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 722 #define CONFIG_PME_PLAT_CLK_DIV 2 723 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 724 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 725 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 726 #define CONFIG_SYS_FMAN_V3 727 #define CONFIG_FM_PLAT_CLK_DIV 1 728 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 729 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 730 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 731 #define CONFIG_SYS_FSL_TBCLK_DIV 16 732 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 733 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 734 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 735 #define CONFIG_SYS_FSL_ERRATUM_A006261 736 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 737 738 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 739 #define CONFIG_E6500 740 #define CONFIG_SYS_PPC64 /* 64-bit core */ 741 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 742 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 743 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 744 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 745 #define CONFIG_SYS_FSL_QMAN_V3 746 #define CONFIG_MAX_CPUS 4 747 #define CONFIG_SYS_FSL_NUM_LAWS 32 748 #define CONFIG_SYS_FSL_SEC_COMPAT 4 749 #define CONFIG_SYS_NUM_FMAN 1 750 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 751 #define CONFIG_SYS_FSL_SRDS_1 752 #define CONFIG_SYS_FSL_PCI_VER_3_X 753 #if defined(CONFIG_PPC_T2080) 754 #define CONFIG_SYS_NUM_FM1_DTSEC 8 755 #define CONFIG_SYS_NUM_FM1_10GEC 4 756 #define CONFIG_SYS_FSL_SRDS_2 757 #define CONFIG_SYS_FSL_SRIO_LIODN 758 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 759 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 760 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 761 #elif defined(CONFIG_PPC_T2081) 762 #define CONFIG_SYS_NUM_FM1_DTSEC 6 763 #define CONFIG_SYS_NUM_FM1_10GEC 2 764 #endif 765 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 766 #define CONFIG_NUM_DDR_CONTROLLERS 1 767 #define CONFIG_PME_PLAT_CLK_DIV 1 768 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 769 #define CONFIG_SYS_FM1_CLK 0 770 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 771 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 772 #define CONFIG_SYS_FMAN_V3 773 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 774 #define CONFIG_SYS_FSL_TBCLK_DIV 16 775 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 776 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 777 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 778 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 779 #define CONFIG_SYS_FSL_SFP_VER_3_0 780 #define CONFIG_SYS_FSL_ISBC_VER 2 781 782 #elif defined(CONFIG_PPC_C29X) 783 #define CONFIG_MAX_CPUS 1 784 #define CONFIG_FSL_SDHC_V2_3 785 #define CONFIG_SYS_FSL_NUM_LAWS 12 786 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 787 #define CONFIG_TSECV2_1 788 #define CONFIG_SYS_FSL_SEC_COMPAT 6 789 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 790 #define CONFIG_NUM_DDR_CONTROLLERS 1 791 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 792 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 793 #define CONFIG_SYS_FSL_ERRATUM_A005125 794 795 #else 796 #error Processor type not defined for this platform 797 #endif 798 799 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 800 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 801 #endif 802 803 #ifdef CONFIG_E6500 804 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 805 #else 806 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 807 #endif 808 809 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 810 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 811 !defined(CONFIG_SYS_FSL_DDRC_GEN3) 812 #define CONFIG_SYS_FSL_DDRC_GEN3 813 #endif 814 815 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 816