1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #define FSL_DDR_VER_4_7 47 23 #define FSL_DDR_VER_5_0 50 24 25 /* Number of TLB CAM entries we have on FSL Book-E chips */ 26 #if defined(CONFIG_E500MC) 27 #define CONFIG_SYS_NUM_TLBCAMS 64 28 #elif defined(CONFIG_E500) 29 #define CONFIG_SYS_NUM_TLBCAMS 16 30 #endif 31 32 #if defined(CONFIG_MPC8536) 33 #define CONFIG_MAX_CPUS 1 34 #define CONFIG_SYS_FSL_NUM_LAWS 12 35 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 37 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 38 #define CONFIG_SYS_FSL_ERRATUM_A005125 39 40 #elif defined(CONFIG_MPC8540) 41 #define CONFIG_MAX_CPUS 1 42 #define CONFIG_SYS_FSL_NUM_LAWS 8 43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 44 45 #elif defined(CONFIG_MPC8541) 46 #define CONFIG_MAX_CPUS 1 47 #define CONFIG_SYS_FSL_NUM_LAWS 8 48 #define CONFIG_SYS_FSL_SEC_COMPAT 2 49 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 50 51 #elif defined(CONFIG_MPC8544) 52 #define CONFIG_MAX_CPUS 1 53 #define CONFIG_SYS_FSL_NUM_LAWS 10 54 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 55 #define CONFIG_SYS_FSL_SEC_COMPAT 2 56 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 57 #define CONFIG_SYS_FSL_ERRATUM_A005125 58 59 #elif defined(CONFIG_MPC8548) 60 #define CONFIG_MAX_CPUS 1 61 #define CONFIG_SYS_FSL_NUM_LAWS 10 62 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 66 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 67 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 68 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 69 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 70 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 71 #define CONFIG_SYS_FSL_RMU 72 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 73 #define CONFIG_SYS_FSL_ERRATUM_A005125 74 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 75 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 76 77 #elif defined(CONFIG_MPC8555) 78 #define CONFIG_MAX_CPUS 1 79 #define CONFIG_SYS_FSL_NUM_LAWS 8 80 #define CONFIG_SYS_FSL_SEC_COMPAT 2 81 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 82 83 #elif defined(CONFIG_MPC8560) 84 #define CONFIG_MAX_CPUS 1 85 #define CONFIG_SYS_FSL_NUM_LAWS 8 86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 87 88 #elif defined(CONFIG_MPC8568) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 10 91 #define CONFIG_SYS_FSL_SEC_COMPAT 2 92 #define QE_MURAM_SIZE 0x10000UL 93 #define MAX_QE_RISC 2 94 #define QE_NUM_OF_SNUM 28 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 96 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 97 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 98 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 99 #define CONFIG_SYS_FSL_RMU 100 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 101 102 #elif defined(CONFIG_MPC8569) 103 #define CONFIG_MAX_CPUS 1 104 #define CONFIG_SYS_FSL_NUM_LAWS 10 105 #define CONFIG_SYS_FSL_SEC_COMPAT 2 106 #define QE_MURAM_SIZE 0x20000UL 107 #define MAX_QE_RISC 4 108 #define QE_NUM_OF_SNUM 46 109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 113 #define CONFIG_SYS_FSL_RMU 114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 115 #define CONFIG_SYS_FSL_ERRATUM_A005125 116 117 #elif defined(CONFIG_MPC8572) 118 #define CONFIG_MAX_CPUS 2 119 #define CONFIG_SYS_FSL_NUM_LAWS 12 120 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 121 #define CONFIG_SYS_FSL_SEC_COMPAT 2 122 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 123 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 124 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 125 #define CONFIG_SYS_FSL_ERRATUM_A005125 126 127 #elif defined(CONFIG_P1010) 128 #define CONFIG_MAX_CPUS 1 129 #define CONFIG_FSL_SDHC_V2_3 130 #define CONFIG_SYS_FSL_NUM_LAWS 12 131 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 132 #define CONFIG_TSECV2 133 #define CONFIG_SYS_FSL_SEC_COMPAT 4 134 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 135 #define CONFIG_NUM_DDR_CONTROLLERS 1 136 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 137 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 138 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 139 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 140 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 141 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 142 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 143 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 144 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 145 #define CONFIG_SYS_FSL_ERRATUM_A005125 146 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 147 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 148 149 /* P1011 is single core version of P1020 */ 150 #elif defined(CONFIG_P1011) 151 #define CONFIG_MAX_CPUS 1 152 #define CONFIG_SYS_FSL_NUM_LAWS 12 153 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 154 #define CONFIG_TSECV2 155 #define CONFIG_FSL_PCIE_DISABLE_ASPM 156 #define CONFIG_SYS_FSL_SEC_COMPAT 2 157 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 158 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 159 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 160 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 161 #define CONFIG_SYS_FSL_ERRATUM_A005125 162 163 /* P1012 is single core version of P1021 */ 164 #elif defined(CONFIG_P1012) 165 #define CONFIG_MAX_CPUS 1 166 #define CONFIG_SYS_FSL_NUM_LAWS 12 167 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 168 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 169 #define CONFIG_TSECV2 170 #define CONFIG_FSL_PCIE_DISABLE_ASPM 171 #define CONFIG_SYS_FSL_SEC_COMPAT 2 172 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 173 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 174 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 175 #define QE_MURAM_SIZE 0x6000UL 176 #define MAX_QE_RISC 1 177 #define QE_NUM_OF_SNUM 28 178 #define CONFIG_SYS_FSL_ERRATUM_A005125 179 180 /* P1013 is single core version of P1022 */ 181 #elif defined(CONFIG_P1013) 182 #define CONFIG_MAX_CPUS 1 183 #define CONFIG_SYS_FSL_NUM_LAWS 12 184 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 185 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 186 #define CONFIG_TSECV2 187 #define CONFIG_SYS_FSL_SEC_COMPAT 2 188 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 189 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 190 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 191 #define CONFIG_FSL_SATA_ERRATUM_A001 192 #define CONFIG_SYS_FSL_ERRATUM_A005125 193 194 #elif defined(CONFIG_P1014) 195 #define CONFIG_MAX_CPUS 1 196 #define CONFIG_FSL_SDHC_V2_3 197 #define CONFIG_SYS_FSL_NUM_LAWS 12 198 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 199 #define CONFIG_TSECV2 200 #define CONFIG_SYS_FSL_SEC_COMPAT 4 201 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 202 #define CONFIG_NUM_DDR_CONTROLLERS 1 203 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 204 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 205 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 206 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 207 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 208 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 209 210 /* P1017 is single core version of P1023 */ 211 #elif defined(CONFIG_P1017) 212 #define CONFIG_MAX_CPUS 1 213 #define CONFIG_SYS_FSL_NUM_LAWS 12 214 #define CONFIG_SYS_FSL_SEC_COMPAT 4 215 #define CONFIG_SYS_NUM_FMAN 1 216 #define CONFIG_SYS_NUM_FM1_DTSEC 2 217 #define CONFIG_NUM_DDR_CONTROLLERS 1 218 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 219 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 220 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 221 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 222 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 223 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 224 #define CONFIG_SYS_FSL_ERRATUM_A005125 225 226 #elif defined(CONFIG_P1020) 227 #define CONFIG_MAX_CPUS 2 228 #define CONFIG_SYS_FSL_NUM_LAWS 12 229 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 230 #define CONFIG_TSECV2 231 #define CONFIG_FSL_PCIE_DISABLE_ASPM 232 #define CONFIG_SYS_FSL_SEC_COMPAT 2 233 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 234 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 235 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 236 #define CONFIG_SYS_FSL_ERRATUM_A005125 237 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 238 239 #elif defined(CONFIG_P1021) 240 #define CONFIG_MAX_CPUS 2 241 #define CONFIG_SYS_FSL_NUM_LAWS 12 242 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 243 #define CONFIG_TSECV2 244 #define CONFIG_FSL_PCIE_DISABLE_ASPM 245 #define CONFIG_SYS_FSL_SEC_COMPAT 2 246 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 247 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 248 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 249 #define QE_MURAM_SIZE 0x6000UL 250 #define MAX_QE_RISC 1 251 #define QE_NUM_OF_SNUM 28 252 #define CONFIG_SYS_FSL_ERRATUM_A005125 253 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 254 255 #elif defined(CONFIG_P1022) 256 #define CONFIG_MAX_CPUS 2 257 #define CONFIG_SYS_FSL_NUM_LAWS 12 258 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 259 #define CONFIG_TSECV2 260 #define CONFIG_SYS_FSL_SEC_COMPAT 2 261 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 262 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 263 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 264 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 265 #define CONFIG_FSL_SATA_ERRATUM_A001 266 #define CONFIG_SYS_FSL_ERRATUM_A005125 267 268 #elif defined(CONFIG_P1023) 269 #define CONFIG_MAX_CPUS 2 270 #define CONFIG_SYS_FSL_NUM_LAWS 12 271 #define CONFIG_SYS_FSL_SEC_COMPAT 4 272 #define CONFIG_SYS_NUM_FMAN 1 273 #define CONFIG_SYS_NUM_FM1_DTSEC 2 274 #define CONFIG_NUM_DDR_CONTROLLERS 1 275 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 276 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 277 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 278 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 279 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 280 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 281 #define CONFIG_SYS_FSL_ERRATUM_A005125 282 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 283 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 284 285 /* P1024 is lower end variant of P1020 */ 286 #elif defined(CONFIG_P1024) 287 #define CONFIG_MAX_CPUS 2 288 #define CONFIG_SYS_FSL_NUM_LAWS 12 289 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 290 #define CONFIG_TSECV2 291 #define CONFIG_FSL_PCIE_DISABLE_ASPM 292 #define CONFIG_SYS_FSL_SEC_COMPAT 2 293 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 294 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 295 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 296 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 297 #define CONFIG_SYS_FSL_ERRATUM_A005125 298 299 /* P1025 is lower end variant of P1021 */ 300 #elif defined(CONFIG_P1025) 301 #define CONFIG_MAX_CPUS 2 302 #define CONFIG_SYS_FSL_NUM_LAWS 12 303 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 304 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 305 #define CONFIG_TSECV2 306 #define CONFIG_FSL_PCIE_DISABLE_ASPM 307 #define CONFIG_SYS_FSL_SEC_COMPAT 2 308 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 309 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 310 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 311 #define QE_MURAM_SIZE 0x6000UL 312 #define MAX_QE_RISC 1 313 #define QE_NUM_OF_SNUM 28 314 #define CONFIG_SYS_FSL_ERRATUM_A005125 315 316 /* P2010 is single core version of P2020 */ 317 #elif defined(CONFIG_P2010) 318 #define CONFIG_MAX_CPUS 1 319 #define CONFIG_SYS_FSL_NUM_LAWS 12 320 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 321 #define CONFIG_SYS_FSL_SEC_COMPAT 2 322 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 323 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 324 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 325 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 326 #define CONFIG_SYS_FSL_ERRATUM_A005125 327 328 #elif defined(CONFIG_P2020) 329 #define CONFIG_MAX_CPUS 2 330 #define CONFIG_SYS_FSL_NUM_LAWS 12 331 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 332 #define CONFIG_SYS_FSL_SEC_COMPAT 2 333 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 334 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 335 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 336 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 337 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 338 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 339 #define CONFIG_SYS_FSL_RMU 340 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 341 #define CONFIG_SYS_FSL_ERRATUM_A005125 342 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 343 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 344 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 345 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 346 #define CONFIG_MAX_CPUS 4 347 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 348 #define CONFIG_SYS_FSL_NUM_LAWS 32 349 #define CONFIG_SYS_FSL_SEC_COMPAT 4 350 #define CONFIG_SYS_NUM_FMAN 1 351 #define CONFIG_SYS_NUM_FM1_DTSEC 5 352 #define CONFIG_SYS_NUM_FM1_10GEC 1 353 #define CONFIG_NUM_DDR_CONTROLLERS 1 354 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 355 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 356 #define CONFIG_SYS_FSL_TBCLK_DIV 32 357 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 358 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 359 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 360 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 361 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 362 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 363 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 364 #define CONFIG_SYS_FSL_ERRATUM_USB14 365 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 366 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 367 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 368 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 369 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 370 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 371 #define CONFIG_SYS_FSL_ERRATUM_A004510 372 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 373 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 374 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 375 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 376 #define CONFIG_SYS_FSL_ERRATUM_A004849 377 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 378 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 379 380 #elif defined(CONFIG_PPC_P3041) 381 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 382 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 383 #define CONFIG_MAX_CPUS 4 384 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 385 #define CONFIG_SYS_FSL_NUM_LAWS 32 386 #define CONFIG_SYS_FSL_SEC_COMPAT 4 387 #define CONFIG_SYS_NUM_FMAN 1 388 #define CONFIG_SYS_NUM_FM1_DTSEC 5 389 #define CONFIG_SYS_NUM_FM1_10GEC 1 390 #define CONFIG_NUM_DDR_CONTROLLERS 1 391 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 392 #define CONFIG_SYS_FSL_TBCLK_DIV 32 393 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 394 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 395 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 396 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 397 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 398 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 399 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 400 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 401 #define CONFIG_SYS_FSL_ERRATUM_USB14 402 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 403 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 404 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 405 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 406 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 407 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 408 #define CONFIG_SYS_FSL_ERRATUM_A004510 409 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 410 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 411 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 412 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 413 #define CONFIG_SYS_FSL_ERRATUM_A004849 414 #define CONFIG_SYS_FSL_ERRATUM_A005812 415 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 416 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 417 418 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 419 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 420 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 421 #define CONFIG_MAX_CPUS 8 422 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 423 #define CONFIG_SYS_FSL_NUM_LAWS 32 424 #define CONFIG_SYS_FSL_SEC_COMPAT 4 425 #define CONFIG_SYS_NUM_FMAN 2 426 #define CONFIG_SYS_NUM_FM1_DTSEC 4 427 #define CONFIG_SYS_NUM_FM2_DTSEC 4 428 #define CONFIG_SYS_NUM_FM1_10GEC 1 429 #define CONFIG_SYS_NUM_FM2_10GEC 1 430 #define CONFIG_NUM_DDR_CONTROLLERS 2 431 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 432 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 433 #define CONFIG_SYS_FSL_TBCLK_DIV 16 434 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 435 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 436 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 437 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 438 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 439 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 440 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 441 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 442 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 443 #define CONFIG_SYS_P4080_ERRATUM_CPU22 444 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 445 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 446 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 447 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 448 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 449 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 450 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 451 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 452 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 453 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 454 #define CONFIG_SYS_FSL_RMU 455 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 456 #define CONFIG_SYS_FSL_ERRATUM_A004510 457 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 458 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 459 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 460 #define CONFIG_SYS_FSL_ERRATUM_A004849 461 #define CONFIG_SYS_FSL_ERRATUM_A004580 462 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 463 #define CONFIG_SYS_FSL_ERRATUM_A005812 464 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 465 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 466 467 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 468 #define CONFIG_SYS_PPC64 /* 64-bit core */ 469 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 470 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 471 #define CONFIG_MAX_CPUS 2 472 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 473 #define CONFIG_SYS_FSL_NUM_LAWS 32 474 #define CONFIG_SYS_FSL_SEC_COMPAT 4 475 #define CONFIG_SYS_NUM_FMAN 1 476 #define CONFIG_SYS_NUM_FM1_DTSEC 5 477 #define CONFIG_SYS_NUM_FM1_10GEC 1 478 #define CONFIG_NUM_DDR_CONTROLLERS 2 479 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 480 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 481 #define CONFIG_SYS_FSL_TBCLK_DIV 32 482 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 483 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 484 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 485 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 486 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 487 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 488 #define CONFIG_SYS_FSL_ERRATUM_USB14 489 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 490 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 491 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 492 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 493 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 494 #define CONFIG_SYS_FSL_ERRATUM_A004510 495 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 496 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 497 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 498 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 499 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 500 501 #elif defined(CONFIG_PPC_P5040) 502 #define CONFIG_SYS_PPC64 503 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 504 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 505 #define CONFIG_MAX_CPUS 4 506 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 507 #define CONFIG_SYS_FSL_NUM_LAWS 32 508 #define CONFIG_SYS_FSL_SEC_COMPAT 4 509 #define CONFIG_SYS_NUM_FMAN 2 510 #define CONFIG_SYS_NUM_FM1_DTSEC 5 511 #define CONFIG_SYS_NUM_FM1_10GEC 1 512 #define CONFIG_SYS_NUM_FM2_DTSEC 5 513 #define CONFIG_SYS_NUM_FM2_10GEC 1 514 #define CONFIG_NUM_DDR_CONTROLLERS 2 515 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 516 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 517 #define CONFIG_SYS_FSL_TBCLK_DIV 16 518 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 519 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 520 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 521 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 522 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 523 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 524 #define CONFIG_SYS_FSL_ERRATUM_USB14 525 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 526 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 527 #define CONFIG_SYS_FSL_ERRATUM_A004699 528 #define CONFIG_SYS_FSL_ERRATUM_A004510 529 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 530 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 531 #define CONFIG_SYS_FSL_ERRATUM_A005812 532 533 #elif defined(CONFIG_BSC9131) 534 #define CONFIG_MAX_CPUS 1 535 #define CONFIG_FSL_SDHC_V2_3 536 #define CONFIG_SYS_FSL_NUM_LAWS 12 537 #define CONFIG_TSECV2 538 #define CONFIG_SYS_FSL_SEC_COMPAT 4 539 #define CONFIG_NUM_DDR_CONTROLLERS 1 540 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 541 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 542 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 543 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 544 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 545 #define CONFIG_NAND_FSL_IFC 546 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 547 #define CONFIG_SYS_FSL_ERRATUM_A005125 548 549 #elif defined(CONFIG_BSC9132) 550 #define CONFIG_MAX_CPUS 2 551 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 552 #define CONFIG_FSL_SDHC_V2_3 553 #define CONFIG_SYS_FSL_NUM_LAWS 12 554 #define CONFIG_TSECV2 555 #define CONFIG_SYS_FSL_SEC_COMPAT 4 556 #define CONFIG_NUM_DDR_CONTROLLERS 2 557 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 558 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 559 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 560 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 561 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 562 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 563 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 564 #define CONFIG_NAND_FSL_IFC 565 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 566 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 567 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 568 #define CONFIG_SYS_FSL_ERRATUM_A005125 569 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 570 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 571 572 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 573 #define CONFIG_E6500 574 #define CONFIG_SYS_PPC64 /* 64-bit core */ 575 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 576 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 577 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 578 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 579 #ifdef CONFIG_PPC_T4240 580 #define CONFIG_MAX_CPUS 12 581 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 582 #define CONFIG_SYS_NUM_FM1_DTSEC 8 583 #define CONFIG_SYS_NUM_FM1_10GEC 2 584 #define CONFIG_SYS_NUM_FM2_DTSEC 8 585 #define CONFIG_SYS_NUM_FM2_10GEC 2 586 #define CONFIG_NUM_DDR_CONTROLLERS 3 587 #else 588 #define CONFIG_MAX_CPUS 8 589 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 590 #define CONFIG_SYS_NUM_FM1_DTSEC 7 591 #define CONFIG_SYS_NUM_FM1_10GEC 1 592 #define CONFIG_SYS_NUM_FM2_DTSEC 7 593 #define CONFIG_SYS_NUM_FM2_10GEC 1 594 #define CONFIG_NUM_DDR_CONTROLLERS 2 595 #endif 596 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 597 #define CONFIG_SYS_FSL_NUM_LAWS 32 598 #define CONFIG_SYS_FSL_SRDS_1 599 #define CONFIG_SYS_FSL_SRDS_2 600 #define CONFIG_SYS_FSL_SRDS_3 601 #define CONFIG_SYS_FSL_SRDS_4 602 #define CONFIG_SYS_FSL_SEC_COMPAT 4 603 #define CONFIG_SYS_NUM_FMAN 2 604 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 605 #define CONFIG_SYS_PME_CLK 0 606 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 607 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 608 #define CONFIG_SYS_FMAN_V3 609 #define CONFIG_SYS_FM1_CLK 3 610 #define CONFIG_SYS_FM2_CLK 3 611 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 612 #define CONFIG_SYS_FSL_TBCLK_DIV 16 613 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 614 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 615 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 616 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 617 #define CONFIG_SYS_FSL_SRIO_LIODN 618 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 619 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 620 #define CONFIG_SYS_FSL_ERRATUM_A004468 621 #define CONFIG_SYS_FSL_ERRATUM_A_004934 622 #define CONFIG_SYS_FSL_ERRATUM_A005871 623 #define CONFIG_SYS_FSL_ERRATUM_A006379 624 #define CONFIG_SYS_FSL_ERRATUM_A006593 625 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 626 #define CONFIG_SYS_FSL_PCI_VER_3_X 627 628 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 629 #define CONFIG_E6500 630 #define CONFIG_SYS_PPC64 /* 64-bit core */ 631 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 632 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 633 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 634 #define CONFIG_SYS_FSL_NUM_LAWS 32 635 #define CONFIG_SYS_FSL_SRDS_1 636 #define CONFIG_SYS_FSL_SRDS_2 637 #define CONFIG_SYS_FSL_SEC_COMPAT 4 638 #define CONFIG_SYS_NUM_FMAN 1 639 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 640 #define CONFIG_SYS_FM1_CLK 0 641 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 642 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 643 #define CONFIG_SYS_FMAN_V3 644 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 645 #define CONFIG_SYS_FSL_TBCLK_DIV 16 646 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 647 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 648 #define CONFIG_SYS_FSL_ERRATUM_A_004934 649 #define CONFIG_SYS_FSL_ERRATUM_A005871 650 #define CONFIG_SYS_FSL_ERRATUM_A006379 651 #define CONFIG_SYS_FSL_ERRATUM_A006593 652 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 653 654 #ifdef CONFIG_PPC_B4860 655 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 656 #define CONFIG_MAX_CPUS 4 657 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 658 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 659 #define CONFIG_SYS_NUM_FM1_DTSEC 6 660 #define CONFIG_SYS_NUM_FM1_10GEC 2 661 #define CONFIG_NUM_DDR_CONTROLLERS 2 662 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 663 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 664 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 665 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 666 #define CONFIG_SYS_FSL_SRIO_LIODN 667 #else 668 #define CONFIG_MAX_CPUS 2 669 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 670 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 671 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 672 #define CONFIG_SYS_NUM_FM1_DTSEC 4 673 #define CONFIG_SYS_NUM_FM1_10GEC 0 674 #define CONFIG_NUM_DDR_CONTROLLERS 1 675 #endif 676 677 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 678 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 679 #define CONFIG_E5500 680 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 681 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 682 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 683 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 684 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 685 #define CONFIG_MAX_CPUS 4 686 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 687 #define CONFIG_MAX_CPUS 2 688 #endif 689 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 690 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 691 #define CONFIG_SYS_SDHC_CLOCK 0 692 #define CONFIG_SYS_FSL_NUM_LAWS 16 693 #define CONFIG_SYS_FSL_SRDS_1 694 #define CONFIG_SYS_FSL_SEC_COMPAT 5 695 #define CONFIG_SYS_NUM_FMAN 1 696 #define CONFIG_SYS_NUM_FM1_DTSEC 5 697 #define CONFIG_NUM_DDR_CONTROLLERS 1 698 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 699 #define CONFIG_PME_PLAT_CLK_DIV 2 700 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 701 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 702 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 703 #define CONFIG_SYS_FMAN_V3 704 #define CONFIG_FM_PLAT_CLK_DIV 1 705 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 706 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 707 #define CONFIG_SYS_FSL_TBCLK_DIV 32 708 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 709 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 710 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 711 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 712 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 713 714 #elif defined(CONFIG_PPC_C29X) 715 #define CONFIG_MAX_CPUS 1 716 #define CONFIG_FSL_SDHC_V2_3 717 #define CONFIG_SYS_FSL_NUM_LAWS 12 718 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 719 #define CONFIG_TSECV2_1 720 #define CONFIG_SYS_FSL_SEC_COMPAT 6 721 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 722 #define CONFIG_NUM_DDR_CONTROLLERS 1 723 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 724 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 725 #define CONFIG_SYS_FSL_ERRATUM_A005125 726 727 #else 728 #error Processor type not defined for this platform 729 #endif 730 731 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 732 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 733 #endif 734 735 #ifdef CONFIG_E6500 736 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 737 #else 738 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 739 #endif 740 741 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 742