1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #define FSL_DDR_VER_4_7 47 23 #define FSL_DDR_VER_5_0 50 24 25 /* Number of TLB CAM entries we have on FSL Book-E chips */ 26 #if defined(CONFIG_E500MC) 27 #define CONFIG_SYS_NUM_TLBCAMS 64 28 #elif defined(CONFIG_E500) 29 #define CONFIG_SYS_NUM_TLBCAMS 16 30 #endif 31 32 #if defined(CONFIG_MPC8536) 33 #define CONFIG_MAX_CPUS 1 34 #define CONFIG_SYS_FSL_NUM_LAWS 12 35 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 37 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 38 #define CONFIG_SYS_FSL_ERRATUM_A005125 39 40 #elif defined(CONFIG_MPC8540) 41 #define CONFIG_MAX_CPUS 1 42 #define CONFIG_SYS_FSL_NUM_LAWS 8 43 #define CONFIG_SYS_FSL_DDRC_GEN1 44 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 45 46 #elif defined(CONFIG_MPC8541) 47 #define CONFIG_MAX_CPUS 1 48 #define CONFIG_SYS_FSL_NUM_LAWS 8 49 #define CONFIG_SYS_FSL_DDRC_GEN1 50 #define CONFIG_SYS_FSL_SEC_COMPAT 2 51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 52 53 #elif defined(CONFIG_MPC8544) 54 #define CONFIG_MAX_CPUS 1 55 #define CONFIG_SYS_FSL_NUM_LAWS 10 56 #define CONFIG_SYS_FSL_DDRC_GEN2 57 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 58 #define CONFIG_SYS_FSL_SEC_COMPAT 2 59 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 60 #define CONFIG_SYS_FSL_ERRATUM_A005125 61 62 #elif defined(CONFIG_MPC8548) 63 #define CONFIG_MAX_CPUS 1 64 #define CONFIG_SYS_FSL_NUM_LAWS 10 65 #define CONFIG_SYS_FSL_DDRC_GEN2 66 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 67 #define CONFIG_SYS_FSL_SEC_COMPAT 2 68 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 69 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 70 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 71 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 72 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 73 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 74 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 75 #define CONFIG_SYS_FSL_RMU 76 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 77 #define CONFIG_SYS_FSL_ERRATUM_A005125 78 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 79 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 80 81 #elif defined(CONFIG_MPC8555) 82 #define CONFIG_MAX_CPUS 1 83 #define CONFIG_SYS_FSL_NUM_LAWS 8 84 #define CONFIG_SYS_FSL_DDRC_GEN1 85 #define CONFIG_SYS_FSL_SEC_COMPAT 2 86 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 87 88 #elif defined(CONFIG_MPC8560) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 8 91 #define CONFIG_SYS_FSL_DDRC_GEN1 92 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 93 94 #elif defined(CONFIG_MPC8568) 95 #define CONFIG_MAX_CPUS 1 96 #define CONFIG_SYS_FSL_NUM_LAWS 10 97 #define CONFIG_SYS_FSL_DDRC_GEN2 98 #define CONFIG_SYS_FSL_SEC_COMPAT 2 99 #define QE_MURAM_SIZE 0x10000UL 100 #define MAX_QE_RISC 2 101 #define QE_NUM_OF_SNUM 28 102 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 103 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 104 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 105 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 106 #define CONFIG_SYS_FSL_RMU 107 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 108 109 #elif defined(CONFIG_MPC8569) 110 #define CONFIG_MAX_CPUS 1 111 #define CONFIG_SYS_FSL_NUM_LAWS 10 112 #define CONFIG_SYS_FSL_SEC_COMPAT 2 113 #define QE_MURAM_SIZE 0x20000UL 114 #define MAX_QE_RISC 4 115 #define QE_NUM_OF_SNUM 46 116 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 117 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 118 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 119 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 120 #define CONFIG_SYS_FSL_RMU 121 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 122 #define CONFIG_SYS_FSL_ERRATUM_A005125 123 124 #elif defined(CONFIG_MPC8572) 125 #define CONFIG_MAX_CPUS 2 126 #define CONFIG_SYS_FSL_NUM_LAWS 12 127 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 128 #define CONFIG_SYS_FSL_SEC_COMPAT 2 129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 130 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 131 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 132 #define CONFIG_SYS_FSL_ERRATUM_A005125 133 134 #elif defined(CONFIG_P1010) 135 #define CONFIG_MAX_CPUS 1 136 #define CONFIG_FSL_SDHC_V2_3 137 #define CONFIG_SYS_FSL_NUM_LAWS 12 138 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 139 #define CONFIG_TSECV2 140 #define CONFIG_SYS_FSL_SEC_COMPAT 4 141 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 142 #define CONFIG_NUM_DDR_CONTROLLERS 1 143 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 144 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 145 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 146 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 147 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 148 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 149 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 150 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 152 #define CONFIG_SYS_FSL_ERRATUM_A005125 153 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 154 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 155 #define CONFIG_ESDHC_HC_BLK_ADDR 156 157 /* P1011 is single core version of P1020 */ 158 #elif defined(CONFIG_P1011) 159 #define CONFIG_MAX_CPUS 1 160 #define CONFIG_SYS_FSL_NUM_LAWS 12 161 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 162 #define CONFIG_TSECV2 163 #define CONFIG_FSL_PCIE_DISABLE_ASPM 164 #define CONFIG_SYS_FSL_SEC_COMPAT 2 165 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 166 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 167 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 168 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 169 #define CONFIG_SYS_FSL_ERRATUM_A005125 170 171 /* P1012 is single core version of P1021 */ 172 #elif defined(CONFIG_P1012) 173 #define CONFIG_MAX_CPUS 1 174 #define CONFIG_SYS_FSL_NUM_LAWS 12 175 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 176 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 177 #define CONFIG_TSECV2 178 #define CONFIG_FSL_PCIE_DISABLE_ASPM 179 #define CONFIG_SYS_FSL_SEC_COMPAT 2 180 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 181 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 183 #define QE_MURAM_SIZE 0x6000UL 184 #define MAX_QE_RISC 1 185 #define QE_NUM_OF_SNUM 28 186 #define CONFIG_SYS_FSL_ERRATUM_A005125 187 188 /* P1013 is single core version of P1022 */ 189 #elif defined(CONFIG_P1013) 190 #define CONFIG_MAX_CPUS 1 191 #define CONFIG_SYS_FSL_NUM_LAWS 12 192 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 193 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 194 #define CONFIG_TSECV2 195 #define CONFIG_SYS_FSL_SEC_COMPAT 2 196 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 197 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 198 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 199 #define CONFIG_FSL_SATA_ERRATUM_A001 200 #define CONFIG_SYS_FSL_ERRATUM_A005125 201 202 #elif defined(CONFIG_P1014) 203 #define CONFIG_MAX_CPUS 1 204 #define CONFIG_FSL_SDHC_V2_3 205 #define CONFIG_SYS_FSL_NUM_LAWS 12 206 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 207 #define CONFIG_TSECV2 208 #define CONFIG_SYS_FSL_SEC_COMPAT 4 209 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 210 #define CONFIG_NUM_DDR_CONTROLLERS 1 211 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 213 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 214 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 215 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 216 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 217 218 /* P1017 is single core version of P1023 */ 219 #elif defined(CONFIG_P1017) 220 #define CONFIG_MAX_CPUS 1 221 #define CONFIG_SYS_FSL_NUM_LAWS 12 222 #define CONFIG_SYS_FSL_SEC_COMPAT 4 223 #define CONFIG_SYS_NUM_FMAN 1 224 #define CONFIG_SYS_NUM_FM1_DTSEC 2 225 #define CONFIG_NUM_DDR_CONTROLLERS 1 226 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 227 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 228 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 229 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 230 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 231 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 232 #define CONFIG_SYS_FSL_ERRATUM_A005125 233 234 #elif defined(CONFIG_P1020) 235 #define CONFIG_MAX_CPUS 2 236 #define CONFIG_SYS_FSL_NUM_LAWS 12 237 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 238 #define CONFIG_TSECV2 239 #define CONFIG_FSL_PCIE_DISABLE_ASPM 240 #define CONFIG_SYS_FSL_SEC_COMPAT 2 241 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 242 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 243 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 244 #define CONFIG_SYS_FSL_ERRATUM_A005125 245 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 246 247 #elif defined(CONFIG_P1021) 248 #define CONFIG_MAX_CPUS 2 249 #define CONFIG_SYS_FSL_NUM_LAWS 12 250 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 251 #define CONFIG_TSECV2 252 #define CONFIG_FSL_PCIE_DISABLE_ASPM 253 #define CONFIG_SYS_FSL_SEC_COMPAT 2 254 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 255 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 256 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 257 #define QE_MURAM_SIZE 0x6000UL 258 #define MAX_QE_RISC 1 259 #define QE_NUM_OF_SNUM 28 260 #define CONFIG_SYS_FSL_ERRATUM_A005125 261 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 262 263 #elif defined(CONFIG_P1022) 264 #define CONFIG_MAX_CPUS 2 265 #define CONFIG_SYS_FSL_NUM_LAWS 12 266 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 267 #define CONFIG_TSECV2 268 #define CONFIG_SYS_FSL_SEC_COMPAT 2 269 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 270 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 271 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 272 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 273 #define CONFIG_FSL_SATA_ERRATUM_A001 274 #define CONFIG_SYS_FSL_ERRATUM_A005125 275 276 #elif defined(CONFIG_P1023) 277 #define CONFIG_MAX_CPUS 2 278 #define CONFIG_SYS_FSL_NUM_LAWS 12 279 #define CONFIG_SYS_FSL_SEC_COMPAT 4 280 #define CONFIG_SYS_NUM_FMAN 1 281 #define CONFIG_SYS_NUM_FM1_DTSEC 2 282 #define CONFIG_NUM_DDR_CONTROLLERS 1 283 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 284 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 285 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 286 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 287 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 288 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 289 #define CONFIG_SYS_FSL_ERRATUM_A005125 290 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 291 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 292 293 /* P1024 is lower end variant of P1020 */ 294 #elif defined(CONFIG_P1024) 295 #define CONFIG_MAX_CPUS 2 296 #define CONFIG_SYS_FSL_NUM_LAWS 12 297 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 298 #define CONFIG_TSECV2 299 #define CONFIG_FSL_PCIE_DISABLE_ASPM 300 #define CONFIG_SYS_FSL_SEC_COMPAT 2 301 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 302 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 303 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 304 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 305 #define CONFIG_SYS_FSL_ERRATUM_A005125 306 307 /* P1025 is lower end variant of P1021 */ 308 #elif defined(CONFIG_P1025) 309 #define CONFIG_MAX_CPUS 2 310 #define CONFIG_SYS_FSL_NUM_LAWS 12 311 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 312 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 313 #define CONFIG_TSECV2 314 #define CONFIG_FSL_PCIE_DISABLE_ASPM 315 #define CONFIG_SYS_FSL_SEC_COMPAT 2 316 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 317 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 318 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 319 #define QE_MURAM_SIZE 0x6000UL 320 #define MAX_QE_RISC 1 321 #define QE_NUM_OF_SNUM 28 322 #define CONFIG_SYS_FSL_ERRATUM_A005125 323 324 /* P2010 is single core version of P2020 */ 325 #elif defined(CONFIG_P2010) 326 #define CONFIG_MAX_CPUS 1 327 #define CONFIG_SYS_FSL_NUM_LAWS 12 328 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 329 #define CONFIG_SYS_FSL_SEC_COMPAT 2 330 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 331 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 332 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 333 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 334 #define CONFIG_SYS_FSL_ERRATUM_A005125 335 336 #elif defined(CONFIG_P2020) 337 #define CONFIG_MAX_CPUS 2 338 #define CONFIG_SYS_FSL_NUM_LAWS 12 339 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 340 #define CONFIG_SYS_FSL_SEC_COMPAT 2 341 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 342 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 343 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 344 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 345 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 346 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 347 #define CONFIG_SYS_FSL_RMU 348 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 349 #define CONFIG_SYS_FSL_ERRATUM_A005125 350 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 351 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 352 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 353 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 354 #define CONFIG_MAX_CPUS 4 355 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 356 #define CONFIG_SYS_FSL_NUM_LAWS 32 357 #define CONFIG_SYS_FSL_SEC_COMPAT 4 358 #define CONFIG_SYS_NUM_FMAN 1 359 #define CONFIG_SYS_NUM_FM1_DTSEC 5 360 #define CONFIG_SYS_NUM_FM1_10GEC 1 361 #define CONFIG_NUM_DDR_CONTROLLERS 1 362 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 363 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 364 #define CONFIG_SYS_FSL_TBCLK_DIV 32 365 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 366 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 367 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 368 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 369 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 370 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 371 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 372 #define CONFIG_SYS_FSL_ERRATUM_USB14 373 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 374 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 375 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 376 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 377 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 378 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 379 #define CONFIG_SYS_FSL_ERRATUM_A004510 380 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 381 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 382 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 383 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 384 #define CONFIG_SYS_FSL_ERRATUM_A004849 385 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 386 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 387 388 #elif defined(CONFIG_PPC_P3041) 389 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 390 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 391 #define CONFIG_MAX_CPUS 4 392 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 393 #define CONFIG_SYS_FSL_NUM_LAWS 32 394 #define CONFIG_SYS_FSL_SEC_COMPAT 4 395 #define CONFIG_SYS_NUM_FMAN 1 396 #define CONFIG_SYS_NUM_FM1_DTSEC 5 397 #define CONFIG_SYS_NUM_FM1_10GEC 1 398 #define CONFIG_NUM_DDR_CONTROLLERS 1 399 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 400 #define CONFIG_SYS_FSL_TBCLK_DIV 32 401 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 402 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 403 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 404 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 405 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 406 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 407 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 408 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 409 #define CONFIG_SYS_FSL_ERRATUM_USB14 410 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 411 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 412 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 413 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 414 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 415 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 416 #define CONFIG_SYS_FSL_ERRATUM_A004510 417 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 418 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 419 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 420 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 421 #define CONFIG_SYS_FSL_ERRATUM_A004849 422 #define CONFIG_SYS_FSL_ERRATUM_A005812 423 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 424 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 425 426 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 427 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 428 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 429 #define CONFIG_MAX_CPUS 8 430 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 431 #define CONFIG_SYS_FSL_NUM_LAWS 32 432 #define CONFIG_SYS_FSL_SEC_COMPAT 4 433 #define CONFIG_SYS_NUM_FMAN 2 434 #define CONFIG_SYS_NUM_FM1_DTSEC 4 435 #define CONFIG_SYS_NUM_FM2_DTSEC 4 436 #define CONFIG_SYS_NUM_FM1_10GEC 1 437 #define CONFIG_SYS_NUM_FM2_10GEC 1 438 #define CONFIG_NUM_DDR_CONTROLLERS 2 439 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 440 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 441 #define CONFIG_SYS_FSL_TBCLK_DIV 16 442 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 443 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 444 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 445 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 446 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 447 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 448 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 449 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 450 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 451 #define CONFIG_SYS_P4080_ERRATUM_CPU22 452 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 453 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 454 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 455 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 456 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 457 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 458 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 459 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 460 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 461 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 462 #define CONFIG_SYS_FSL_RMU 463 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 464 #define CONFIG_SYS_FSL_ERRATUM_A004510 465 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 466 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 467 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 468 #define CONFIG_SYS_FSL_ERRATUM_A004849 469 #define CONFIG_SYS_FSL_ERRATUM_A004580 470 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 471 #define CONFIG_SYS_FSL_ERRATUM_A005812 472 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 473 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 474 475 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 476 #define CONFIG_SYS_PPC64 /* 64-bit core */ 477 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 478 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 479 #define CONFIG_MAX_CPUS 2 480 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 481 #define CONFIG_SYS_FSL_NUM_LAWS 32 482 #define CONFIG_SYS_FSL_SEC_COMPAT 4 483 #define CONFIG_SYS_NUM_FMAN 1 484 #define CONFIG_SYS_NUM_FM1_DTSEC 5 485 #define CONFIG_SYS_NUM_FM1_10GEC 1 486 #define CONFIG_NUM_DDR_CONTROLLERS 2 487 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 488 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 489 #define CONFIG_SYS_FSL_TBCLK_DIV 32 490 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 491 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 492 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 493 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 494 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 495 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 496 #define CONFIG_SYS_FSL_ERRATUM_USB14 497 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 498 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 499 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 500 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 501 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 502 #define CONFIG_SYS_FSL_ERRATUM_A004510 503 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 504 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 505 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 506 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 507 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 508 509 #elif defined(CONFIG_PPC_P5040) 510 #define CONFIG_SYS_PPC64 511 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 512 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 513 #define CONFIG_MAX_CPUS 4 514 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 515 #define CONFIG_SYS_FSL_NUM_LAWS 32 516 #define CONFIG_SYS_FSL_SEC_COMPAT 4 517 #define CONFIG_SYS_NUM_FMAN 2 518 #define CONFIG_SYS_NUM_FM1_DTSEC 5 519 #define CONFIG_SYS_NUM_FM1_10GEC 1 520 #define CONFIG_SYS_NUM_FM2_DTSEC 5 521 #define CONFIG_SYS_NUM_FM2_10GEC 1 522 #define CONFIG_NUM_DDR_CONTROLLERS 2 523 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 524 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 525 #define CONFIG_SYS_FSL_TBCLK_DIV 16 526 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 527 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 528 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 529 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 530 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 531 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 532 #define CONFIG_SYS_FSL_ERRATUM_USB14 533 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 534 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 535 #define CONFIG_SYS_FSL_ERRATUM_A004699 536 #define CONFIG_SYS_FSL_ERRATUM_A004510 537 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 538 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 539 #define CONFIG_SYS_FSL_ERRATUM_A005812 540 541 #elif defined(CONFIG_BSC9131) 542 #define CONFIG_MAX_CPUS 1 543 #define CONFIG_FSL_SDHC_V2_3 544 #define CONFIG_SYS_FSL_NUM_LAWS 12 545 #define CONFIG_TSECV2 546 #define CONFIG_SYS_FSL_SEC_COMPAT 4 547 #define CONFIG_NUM_DDR_CONTROLLERS 1 548 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 549 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 550 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 551 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 552 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 553 #define CONFIG_NAND_FSL_IFC 554 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 555 #define CONFIG_SYS_FSL_ERRATUM_A005125 556 #define CONFIG_ESDHC_HC_BLK_ADDR 557 558 #elif defined(CONFIG_BSC9132) 559 #define CONFIG_MAX_CPUS 2 560 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 561 #define CONFIG_FSL_SDHC_V2_3 562 #define CONFIG_SYS_FSL_NUM_LAWS 12 563 #define CONFIG_TSECV2 564 #define CONFIG_SYS_FSL_SEC_COMPAT 4 565 #define CONFIG_NUM_DDR_CONTROLLERS 2 566 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 567 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 568 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 569 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 570 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 571 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 572 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 573 #define CONFIG_NAND_FSL_IFC 574 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 575 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 576 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 577 #define CONFIG_SYS_FSL_ERRATUM_A005125 578 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 579 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 580 #define CONFIG_ESDHC_HC_BLK_ADDR 581 582 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 583 #define CONFIG_E6500 584 #define CONFIG_SYS_PPC64 /* 64-bit core */ 585 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 586 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 587 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 588 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 589 #ifdef CONFIG_PPC_T4240 590 #define CONFIG_MAX_CPUS 12 591 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 592 #define CONFIG_SYS_NUM_FM1_DTSEC 8 593 #define CONFIG_SYS_NUM_FM1_10GEC 2 594 #define CONFIG_SYS_NUM_FM2_DTSEC 8 595 #define CONFIG_SYS_NUM_FM2_10GEC 2 596 #define CONFIG_NUM_DDR_CONTROLLERS 3 597 #else 598 #define CONFIG_MAX_CPUS 8 599 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 600 #define CONFIG_SYS_NUM_FM1_DTSEC 7 601 #define CONFIG_SYS_NUM_FM1_10GEC 1 602 #define CONFIG_SYS_NUM_FM2_DTSEC 7 603 #define CONFIG_SYS_NUM_FM2_10GEC 1 604 #define CONFIG_NUM_DDR_CONTROLLERS 2 605 #endif 606 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 607 #define CONFIG_SYS_FSL_NUM_LAWS 32 608 #define CONFIG_SYS_FSL_SRDS_1 609 #define CONFIG_SYS_FSL_SRDS_2 610 #define CONFIG_SYS_FSL_SRDS_3 611 #define CONFIG_SYS_FSL_SRDS_4 612 #define CONFIG_SYS_FSL_SEC_COMPAT 4 613 #define CONFIG_SYS_NUM_FMAN 2 614 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 615 #define CONFIG_SYS_PME_CLK 0 616 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 617 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 618 #define CONFIG_SYS_FMAN_V3 619 #define CONFIG_SYS_FM1_CLK 3 620 #define CONFIG_SYS_FM2_CLK 3 621 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 622 #define CONFIG_SYS_FSL_TBCLK_DIV 16 623 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 624 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 625 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 626 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 627 #define CONFIG_SYS_FSL_SRIO_LIODN 628 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 629 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 630 #define CONFIG_SYS_FSL_ERRATUM_A004468 631 #define CONFIG_SYS_FSL_ERRATUM_A_004934 632 #define CONFIG_SYS_FSL_ERRATUM_A005871 633 #define CONFIG_SYS_FSL_ERRATUM_A006379 634 #define CONFIG_SYS_FSL_ERRATUM_A006593 635 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 636 #define CONFIG_SYS_FSL_PCI_VER_3_X 637 638 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 639 #define CONFIG_E6500 640 #define CONFIG_SYS_PPC64 /* 64-bit core */ 641 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 642 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 643 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 644 #define CONFIG_SYS_FSL_NUM_LAWS 32 645 #define CONFIG_SYS_FSL_SRDS_1 646 #define CONFIG_SYS_FSL_SRDS_2 647 #define CONFIG_SYS_FSL_SEC_COMPAT 4 648 #define CONFIG_SYS_NUM_FMAN 1 649 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 650 #define CONFIG_SYS_FM1_CLK 0 651 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 652 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 653 #define CONFIG_SYS_FMAN_V3 654 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 655 #define CONFIG_SYS_FSL_TBCLK_DIV 16 656 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 657 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 658 #define CONFIG_SYS_FSL_ERRATUM_A_004934 659 #define CONFIG_SYS_FSL_ERRATUM_A005871 660 #define CONFIG_SYS_FSL_ERRATUM_A006379 661 #define CONFIG_SYS_FSL_ERRATUM_A006593 662 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 663 664 #ifdef CONFIG_PPC_B4860 665 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 666 #define CONFIG_MAX_CPUS 4 667 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 668 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 669 #define CONFIG_SYS_NUM_FM1_DTSEC 6 670 #define CONFIG_SYS_NUM_FM1_10GEC 2 671 #define CONFIG_NUM_DDR_CONTROLLERS 2 672 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 673 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 674 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 675 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 676 #define CONFIG_SYS_FSL_SRIO_LIODN 677 #else 678 #define CONFIG_MAX_CPUS 2 679 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 680 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 681 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 682 #define CONFIG_SYS_NUM_FM1_DTSEC 4 683 #define CONFIG_SYS_NUM_FM1_10GEC 0 684 #define CONFIG_NUM_DDR_CONTROLLERS 1 685 #endif 686 687 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 688 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 689 #define CONFIG_E5500 690 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 691 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 692 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 693 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 694 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 695 #define CONFIG_MAX_CPUS 4 696 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 697 #define CONFIG_MAX_CPUS 2 698 #endif 699 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 700 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 701 #define CONFIG_SYS_SDHC_CLOCK 0 702 #define CONFIG_SYS_FSL_NUM_LAWS 16 703 #define CONFIG_SYS_FSL_SRDS_1 704 #define CONFIG_SYS_FSL_SEC_COMPAT 5 705 #define CONFIG_SYS_NUM_FMAN 1 706 #define CONFIG_SYS_NUM_FM1_DTSEC 5 707 #define CONFIG_NUM_DDR_CONTROLLERS 1 708 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 709 #define CONFIG_PME_PLAT_CLK_DIV 2 710 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 711 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 712 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 713 #define CONFIG_SYS_FMAN_V3 714 #define CONFIG_FM_PLAT_CLK_DIV 1 715 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 716 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 717 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 718 #define CONFIG_SYS_FSL_TBCLK_DIV 16 719 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 720 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 721 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 722 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 723 724 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 725 #define CONFIG_E6500 726 #define CONFIG_SYS_PPC64 /* 64-bit core */ 727 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 728 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 729 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 730 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 731 #define CONFIG_SYS_FSL_QMAN_V3 732 #define CONFIG_MAX_CPUS 4 733 #define CONFIG_SYS_FSL_NUM_LAWS 32 734 #define CONFIG_SYS_FSL_SEC_COMPAT 4 735 #define CONFIG_SYS_NUM_FMAN 1 736 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 737 #define CONFIG_SYS_FSL_SRDS_1 738 #define CONFIG_SYS_FSL_PCI_VER_3_X 739 #if defined(CONFIG_PPC_T2080) 740 #define CONFIG_SYS_NUM_FM1_DTSEC 8 741 #define CONFIG_SYS_NUM_FM1_10GEC 4 742 #define CONFIG_SYS_FSL_SRDS_2 743 #define CONFIG_SYS_FSL_SRIO_LIODN 744 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 745 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 746 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 747 #elif defined(CONFIG_PPC_T2081) 748 #define CONFIG_SYS_NUM_FM1_DTSEC 6 749 #define CONFIG_SYS_NUM_FM1_10GEC 2 750 #endif 751 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 752 #define CONFIG_NUM_DDR_CONTROLLERS 1 753 #define CONFIG_PME_PLAT_CLK_DIV 1 754 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 755 #define CONFIG_SYS_FM1_CLK 0 756 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 757 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 758 #define CONFIG_SYS_FMAN_V3 759 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 760 #define CONFIG_SYS_FSL_TBCLK_DIV 16 761 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 762 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 763 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 764 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 765 #define CONFIG_SYS_FSL_SFP_VER_3_0 766 #define CONFIG_SYS_FSL_ISBC_VER 2 767 768 #elif defined(CONFIG_PPC_C29X) 769 #define CONFIG_MAX_CPUS 1 770 #define CONFIG_FSL_SDHC_V2_3 771 #define CONFIG_SYS_FSL_NUM_LAWS 12 772 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 773 #define CONFIG_TSECV2_1 774 #define CONFIG_SYS_FSL_SEC_COMPAT 6 775 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 776 #define CONFIG_NUM_DDR_CONTROLLERS 1 777 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 778 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 779 #define CONFIG_SYS_FSL_ERRATUM_A005125 780 781 #else 782 #error Processor type not defined for this platform 783 #endif 784 785 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 786 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 787 #endif 788 789 #ifdef CONFIG_E6500 790 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 791 #else 792 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 793 #endif 794 795 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 796 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 797 !defined(CONFIG_SYS_FSL_DDRC_GEN3) 798 #define CONFIG_SYS_FSL_DDRC_GEN3 799 #endif 800 801 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 802