1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 /* Number of TLB CAM entries we have on FSL Book-E chips */ 31 #if defined(CONFIG_E500MC) 32 #define CONFIG_SYS_NUM_TLBCAMS 64 33 #elif defined(CONFIG_E500) 34 #define CONFIG_SYS_NUM_TLBCAMS 16 35 #endif 36 37 #if defined(CONFIG_MPC8536) 38 #define CONFIG_MAX_CPUS 1 39 #define CONFIG_SYS_FSL_NUM_LAWS 12 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 48 #elif defined(CONFIG_MPC8541) 49 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_SEC_COMPAT 2 52 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 53 54 #elif defined(CONFIG_MPC8544) 55 #define CONFIG_MAX_CPUS 1 56 #define CONFIG_SYS_FSL_NUM_LAWS 10 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8548) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 66 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 67 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 68 69 #elif defined(CONFIG_MPC8555) 70 #define CONFIG_MAX_CPUS 1 71 #define CONFIG_SYS_FSL_NUM_LAWS 8 72 #define CONFIG_SYS_FSL_SEC_COMPAT 2 73 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 74 75 #elif defined(CONFIG_MPC8560) 76 #define CONFIG_MAX_CPUS 1 77 #define CONFIG_SYS_FSL_NUM_LAWS 8 78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 79 80 #elif defined(CONFIG_MPC8568) 81 #define CONFIG_MAX_CPUS 1 82 #define CONFIG_SYS_FSL_NUM_LAWS 10 83 #define CONFIG_SYS_FSL_SEC_COMPAT 2 84 #define QE_MURAM_SIZE 0x10000UL 85 #define MAX_QE_RISC 2 86 #define QE_NUM_OF_SNUM 28 87 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 88 89 #elif defined(CONFIG_MPC8569) 90 #define CONFIG_MAX_CPUS 1 91 #define CONFIG_SYS_FSL_NUM_LAWS 10 92 #define CONFIG_SYS_FSL_SEC_COMPAT 2 93 #define QE_MURAM_SIZE 0x20000UL 94 #define MAX_QE_RISC 4 95 #define QE_NUM_OF_SNUM 46 96 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 97 98 #elif defined(CONFIG_MPC8572) 99 #define CONFIG_MAX_CPUS 2 100 #define CONFIG_SYS_FSL_NUM_LAWS 12 101 #define CONFIG_SYS_FSL_SEC_COMPAT 2 102 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 103 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 104 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 105 106 #elif defined(CONFIG_P1010) 107 #define CONFIG_MAX_CPUS 1 108 #define CONFIG_FSL_SDHC_V2_3 109 #define CONFIG_SYS_FSL_NUM_LAWS 12 110 #define CONFIG_TSECV2 111 #define CONFIG_SYS_FSL_SEC_COMPAT 4 112 #define CONFIG_FSL_SATA_V2 113 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 114 #define CONFIG_NUM_DDR_CONTROLLERS 1 115 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 116 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 117 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 118 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 119 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 120 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 121 122 /* P1011 is single core version of P1020 */ 123 #elif defined(CONFIG_P1011) 124 #define CONFIG_MAX_CPUS 1 125 #define CONFIG_SYS_FSL_NUM_LAWS 12 126 #define CONFIG_TSECV2 127 #define CONFIG_FSL_PCIE_DISABLE_ASPM 128 #define CONFIG_SYS_FSL_SEC_COMPAT 2 129 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 130 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 131 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 132 133 /* P1012 is single core version of P1021 */ 134 #elif defined(CONFIG_P1012) 135 #define CONFIG_MAX_CPUS 1 136 #define CONFIG_SYS_FSL_NUM_LAWS 12 137 #define CONFIG_TSECV2 138 #define CONFIG_FSL_PCIE_DISABLE_ASPM 139 #define CONFIG_SYS_FSL_SEC_COMPAT 2 140 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 141 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 142 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 143 #define QE_MURAM_SIZE 0x6000UL 144 #define MAX_QE_RISC 1 145 #define QE_NUM_OF_SNUM 28 146 147 /* P1013 is single core version of P1022 */ 148 #elif defined(CONFIG_P1013) 149 #define CONFIG_MAX_CPUS 1 150 #define CONFIG_SYS_FSL_NUM_LAWS 12 151 #define CONFIG_TSECV2 152 #define CONFIG_SYS_FSL_SEC_COMPAT 2 153 #define CONFIG_FSL_SATA_V2 154 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 155 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 156 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 157 #define CONFIG_FSL_SATA_ERRATUM_A001 158 159 #elif defined(CONFIG_P1014) 160 #define CONFIG_MAX_CPUS 1 161 #define CONFIG_FSL_SDHC_V2_3 162 #define CONFIG_SYS_FSL_NUM_LAWS 12 163 #define CONFIG_TSECV2 164 #define CONFIG_SYS_FSL_SEC_COMPAT 4 165 #define CONFIG_FSL_SATA_V2 166 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 167 #define CONFIG_NUM_DDR_CONTROLLERS 1 168 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 169 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 170 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 171 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 172 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 173 174 /* P1015 is single core version of P1024 */ 175 #elif defined(CONFIG_P1015) 176 #define CONFIG_MAX_CPUS 1 177 #define CONFIG_SYS_FSL_NUM_LAWS 12 178 #define CONFIG_TSECV2 179 #define CONFIG_FSL_PCIE_DISABLE_ASPM 180 #define CONFIG_SYS_FSL_SEC_COMPAT 2 181 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 182 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 183 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 184 185 /* P1016 is single core version of P1025 */ 186 #elif defined(CONFIG_P1016) 187 #define CONFIG_MAX_CPUS 1 188 #define CONFIG_SYS_FSL_NUM_LAWS 12 189 #define CONFIG_TSECV2 190 #define CONFIG_FSL_PCIE_DISABLE_ASPM 191 #define CONFIG_SYS_FSL_SEC_COMPAT 2 192 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 193 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 194 #define QE_MURAM_SIZE 0x6000UL 195 #define MAX_QE_RISC 1 196 #define QE_NUM_OF_SNUM 28 197 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 198 199 /* P1017 is single core version of P1023 */ 200 #elif defined(CONFIG_P1017) 201 #define CONFIG_MAX_CPUS 1 202 #define CONFIG_SYS_FSL_NUM_LAWS 12 203 #define CONFIG_SYS_FSL_SEC_COMPAT 4 204 #define CONFIG_SYS_NUM_FMAN 1 205 #define CONFIG_SYS_NUM_FM1_DTSEC 2 206 #define CONFIG_NUM_DDR_CONTROLLERS 1 207 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 208 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 209 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 210 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 211 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 212 213 #elif defined(CONFIG_P1020) 214 #define CONFIG_MAX_CPUS 2 215 #define CONFIG_SYS_FSL_NUM_LAWS 12 216 #define CONFIG_TSECV2 217 #define CONFIG_FSL_PCIE_DISABLE_ASPM 218 #define CONFIG_SYS_FSL_SEC_COMPAT 2 219 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 220 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 221 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 222 223 #elif defined(CONFIG_P1021) 224 #define CONFIG_MAX_CPUS 2 225 #define CONFIG_SYS_FSL_NUM_LAWS 12 226 #define CONFIG_TSECV2 227 #define CONFIG_FSL_PCIE_DISABLE_ASPM 228 #define CONFIG_SYS_FSL_SEC_COMPAT 2 229 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 230 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 231 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 232 #define QE_MURAM_SIZE 0x6000UL 233 #define MAX_QE_RISC 1 234 #define QE_NUM_OF_SNUM 28 235 236 #elif defined(CONFIG_P1022) 237 #define CONFIG_MAX_CPUS 2 238 #define CONFIG_SYS_FSL_NUM_LAWS 12 239 #define CONFIG_TSECV2 240 #define CONFIG_SYS_FSL_SEC_COMPAT 2 241 #define CONFIG_FSL_SATA_V2 242 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 243 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 244 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 245 #define CONFIG_FSL_SATA_ERRATUM_A001 246 247 #elif defined(CONFIG_P1023) 248 #define CONFIG_MAX_CPUS 2 249 #define CONFIG_SYS_FSL_NUM_LAWS 12 250 #define CONFIG_SYS_FSL_SEC_COMPAT 4 251 #define CONFIG_SYS_NUM_FMAN 1 252 #define CONFIG_SYS_NUM_FM1_DTSEC 2 253 #define CONFIG_NUM_DDR_CONTROLLERS 1 254 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 255 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 256 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 257 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 258 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 259 260 /* P1024 is lower end variant of P1020 */ 261 #elif defined(CONFIG_P1024) 262 #define CONFIG_MAX_CPUS 2 263 #define CONFIG_SYS_FSL_NUM_LAWS 12 264 #define CONFIG_TSECV2 265 #define CONFIG_FSL_PCIE_DISABLE_ASPM 266 #define CONFIG_SYS_FSL_SEC_COMPAT 2 267 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 268 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 269 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 270 271 /* P1025 is lower end variant of P1021 */ 272 #elif defined(CONFIG_P1025) 273 #define CONFIG_MAX_CPUS 2 274 #define CONFIG_SYS_FSL_NUM_LAWS 12 275 #define CONFIG_TSECV2 276 #define CONFIG_FSL_PCIE_DISABLE_ASPM 277 #define CONFIG_SYS_FSL_SEC_COMPAT 2 278 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 279 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 280 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 281 #define QE_MURAM_SIZE 0x6000UL 282 #define MAX_QE_RISC 1 283 #define QE_NUM_OF_SNUM 28 284 285 /* P2010 is single core version of P2020 */ 286 #elif defined(CONFIG_P2010) 287 #define CONFIG_MAX_CPUS 1 288 #define CONFIG_SYS_FSL_NUM_LAWS 12 289 #define CONFIG_SYS_FSL_SEC_COMPAT 2 290 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 291 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 292 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 293 294 #elif defined(CONFIG_P2020) 295 #define CONFIG_MAX_CPUS 2 296 #define CONFIG_SYS_FSL_NUM_LAWS 12 297 #define CONFIG_SYS_FSL_SEC_COMPAT 2 298 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 299 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 300 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 301 302 #elif defined(CONFIG_PPC_P2040) 303 #define CONFIG_MAX_CPUS 4 304 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 305 #define CONFIG_SYS_FSL_NUM_LAWS 32 306 #define CONFIG_SYS_FSL_SEC_COMPAT 4 307 #define CONFIG_SYS_NUM_FMAN 1 308 #define CONFIG_SYS_NUM_FM1_DTSEC 5 309 #define CONFIG_NUM_DDR_CONTROLLERS 1 310 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 311 #define CONFIG_SYS_FSL_TBCLK_DIV 32 312 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 313 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 314 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 315 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 316 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 317 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 318 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 319 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 320 321 #elif defined(CONFIG_PPC_P2041) 322 #define CONFIG_MAX_CPUS 4 323 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 324 #define CONFIG_SYS_FSL_NUM_LAWS 32 325 #define CONFIG_SYS_FSL_SEC_COMPAT 4 326 #define CONFIG_FSL_SATA_V2 327 #define CONFIG_SYS_NUM_FMAN 1 328 #define CONFIG_SYS_NUM_FM1_DTSEC 5 329 #define CONFIG_SYS_NUM_FM1_10GEC 1 330 #define CONFIG_NUM_DDR_CONTROLLERS 1 331 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 332 #define CONFIG_SYS_FSL_TBCLK_DIV 32 333 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 334 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 335 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 336 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 337 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 338 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 339 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 340 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 341 342 #elif defined(CONFIG_PPC_P3041) 343 #define CONFIG_MAX_CPUS 4 344 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 345 #define CONFIG_SYS_FSL_NUM_LAWS 32 346 #define CONFIG_SYS_FSL_SEC_COMPAT 4 347 #define CONFIG_FSL_SATA_V2 348 #define CONFIG_SYS_NUM_FMAN 1 349 #define CONFIG_SYS_NUM_FM1_DTSEC 5 350 #define CONFIG_SYS_NUM_FM1_10GEC 1 351 #define CONFIG_NUM_DDR_CONTROLLERS 1 352 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 353 #define CONFIG_SYS_FSL_TBCLK_DIV 32 354 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 355 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 356 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 357 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 358 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 359 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 360 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 361 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 362 363 #elif defined(CONFIG_PPC_P3060) 364 #define CONFIG_MAX_CPUS 8 365 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 366 #define CONFIG_SYS_FSL_NUM_LAWS 32 367 #define CONFIG_SYS_FSL_SEC_COMPAT 4 368 #define CONFIG_SYS_NUM_FMAN 2 369 #define CONFIG_SYS_NUM_FM1_DTSEC 4 370 #define CONFIG_SYS_NUM_FM2_DTSEC 4 371 #define CONFIG_NUM_DDR_CONTROLLERS 1 372 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 373 #define CONFIG_SYS_FSL_TBCLK_DIV 16 374 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 375 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 376 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 377 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 378 379 #elif defined(CONFIG_PPC_P4040) 380 #define CONFIG_MAX_CPUS 4 381 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 382 #define CONFIG_SYS_FSL_NUM_LAWS 32 383 #define CONFIG_SYS_FSL_SEC_COMPAT 4 384 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 385 #define CONFIG_SYS_FSL_TBCLK_DIV 16 386 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 387 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 388 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 389 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 390 391 #elif defined(CONFIG_PPC_P4080) 392 #define CONFIG_MAX_CPUS 8 393 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 394 #define CONFIG_SYS_FSL_NUM_LAWS 32 395 #define CONFIG_SYS_FSL_SEC_COMPAT 4 396 #define CONFIG_SYS_NUM_FMAN 2 397 #define CONFIG_SYS_NUM_FM1_DTSEC 4 398 #define CONFIG_SYS_NUM_FM2_DTSEC 4 399 #define CONFIG_SYS_NUM_FM1_10GEC 1 400 #define CONFIG_SYS_NUM_FM2_10GEC 1 401 #define CONFIG_NUM_DDR_CONTROLLERS 2 402 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 403 #define CONFIG_SYS_FSL_TBCLK_DIV 16 404 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 405 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 406 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 407 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 408 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 409 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 410 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 411 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 412 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 413 #define CONFIG_SYS_P4080_ERRATUM_CPU22 414 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 415 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 416 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 417 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 418 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 419 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 420 421 /* P5010 is single core version of P5020 */ 422 #elif defined(CONFIG_PPC_P5010) 423 #define CONFIG_MAX_CPUS 1 424 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 425 #define CONFIG_SYS_FSL_NUM_LAWS 32 426 #define CONFIG_SYS_FSL_SEC_COMPAT 4 427 #define CONFIG_FSL_SATA_V2 428 #define CONFIG_SYS_NUM_FMAN 1 429 #define CONFIG_SYS_NUM_FM1_DTSEC 5 430 #define CONFIG_SYS_NUM_FM1_10GEC 1 431 #define CONFIG_NUM_DDR_CONTROLLERS 1 432 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 433 #define CONFIG_SYS_FSL_TBCLK_DIV 32 434 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 435 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 436 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 437 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 438 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 439 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 440 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 441 442 #elif defined(CONFIG_PPC_P5020) 443 #define CONFIG_MAX_CPUS 2 444 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 445 #define CONFIG_SYS_FSL_NUM_LAWS 32 446 #define CONFIG_SYS_FSL_SEC_COMPAT 4 447 #define CONFIG_FSL_SATA_V2 448 #define CONFIG_SYS_NUM_FMAN 1 449 #define CONFIG_SYS_NUM_FM1_DTSEC 5 450 #define CONFIG_SYS_NUM_FM1_10GEC 1 451 #define CONFIG_NUM_DDR_CONTROLLERS 2 452 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 453 #define CONFIG_SYS_FSL_TBCLK_DIV 32 454 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 455 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 456 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 457 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 458 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 459 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 460 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 461 462 #else 463 #error Processor type not defined for this platform 464 #endif 465 466 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 467 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 468 #endif 469 470 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 471