1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #include <fsl_ddrc_version.h> 23 #define CONFIG_SYS_FSL_DDR_BE 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 #define CONFIG_SYS_FSL_SEC_BE 28 #define CONFIG_SYS_FSL_SFP_BE 29 #define CONFIG_SYS_FSL_SEC_MON_BE 30 31 /* Number of TLB CAM entries we have on FSL Book-E chips */ 32 #if defined(CONFIG_E500MC) 33 #define CONFIG_SYS_NUM_TLBCAMS 64 34 #elif defined(CONFIG_E500) 35 #define CONFIG_SYS_NUM_TLBCAMS 16 36 #endif 37 38 #if defined(CONFIG_MPC8536) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 12 41 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 42 #define CONFIG_SYS_FSL_SEC_COMPAT 2 43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 44 #define CONFIG_SYS_FSL_ERRATUM_A004508 45 #define CONFIG_SYS_FSL_ERRATUM_A005125 46 47 #elif defined(CONFIG_MPC8540) 48 #define CONFIG_MAX_CPUS 1 49 #define CONFIG_SYS_FSL_NUM_LAWS 8 50 #define CONFIG_SYS_FSL_DDRC_GEN1 51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 52 53 #elif defined(CONFIG_MPC8541) 54 #define CONFIG_MAX_CPUS 1 55 #define CONFIG_SYS_FSL_NUM_LAWS 8 56 #define CONFIG_SYS_FSL_DDRC_GEN1 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8544) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_DDRC_GEN2 64 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 65 #define CONFIG_SYS_FSL_SEC_COMPAT 2 66 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 67 #define CONFIG_SYS_FSL_ERRATUM_A005125 68 69 #elif defined(CONFIG_MPC8548) 70 #define CONFIG_MAX_CPUS 1 71 #define CONFIG_SYS_FSL_NUM_LAWS 10 72 #define CONFIG_SYS_FSL_DDRC_GEN2 73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 74 #define CONFIG_SYS_FSL_SEC_COMPAT 2 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 82 #define CONFIG_SYS_FSL_RMU 83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 84 #define CONFIG_SYS_FSL_ERRATUM_A005125 85 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 86 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 87 88 #elif defined(CONFIG_MPC8555) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 8 91 #define CONFIG_SYS_FSL_DDRC_GEN1 92 #define CONFIG_SYS_FSL_SEC_COMPAT 2 93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 94 95 #elif defined(CONFIG_MPC8560) 96 #define CONFIG_MAX_CPUS 1 97 #define CONFIG_SYS_FSL_NUM_LAWS 8 98 #define CONFIG_SYS_FSL_DDRC_GEN1 99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 100 101 #elif defined(CONFIG_MPC8568) 102 #define CONFIG_MAX_CPUS 1 103 #define CONFIG_SYS_FSL_NUM_LAWS 10 104 #define CONFIG_SYS_FSL_DDRC_GEN2 105 #define CONFIG_SYS_FSL_SEC_COMPAT 2 106 #define QE_MURAM_SIZE 0x10000UL 107 #define MAX_QE_RISC 2 108 #define QE_NUM_OF_SNUM 28 109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 113 #define CONFIG_SYS_FSL_RMU 114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 115 116 #elif defined(CONFIG_MPC8569) 117 #define CONFIG_MAX_CPUS 1 118 #define CONFIG_SYS_FSL_NUM_LAWS 10 119 #define CONFIG_SYS_FSL_SEC_COMPAT 2 120 #define QE_MURAM_SIZE 0x20000UL 121 #define MAX_QE_RISC 4 122 #define QE_NUM_OF_SNUM 46 123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 124 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 125 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 126 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 127 #define CONFIG_SYS_FSL_RMU 128 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 129 #define CONFIG_SYS_FSL_ERRATUM_A004508 130 #define CONFIG_SYS_FSL_ERRATUM_A005125 131 132 #elif defined(CONFIG_MPC8572) 133 #define CONFIG_MAX_CPUS 2 134 #define CONFIG_SYS_FSL_NUM_LAWS 12 135 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 136 #define CONFIG_SYS_FSL_SEC_COMPAT 2 137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 138 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 139 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 140 #define CONFIG_SYS_FSL_ERRATUM_A004508 141 #define CONFIG_SYS_FSL_ERRATUM_A005125 142 143 #elif defined(CONFIG_P1010) 144 #define CONFIG_MAX_CPUS 1 145 #define CONFIG_FSL_SDHC_V2_3 146 #define CONFIG_SYS_FSL_NUM_LAWS 12 147 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 148 #define CONFIG_TSECV2 149 #define CONFIG_SYS_FSL_SEC_COMPAT 4 150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 151 #define CONFIG_NUM_DDR_CONTROLLERS 1 152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 153 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 154 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 155 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 156 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 157 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 158 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 159 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 160 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 161 #define CONFIG_SYS_FSL_ERRATUM_A005125 162 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 163 #define CONFIG_SYS_FSL_ERRATUM_A004508 164 #define CONFIG_SYS_FSL_ERRATUM_A007075 165 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 166 #define CONFIG_SYS_FSL_ERRATUM_A006261 167 #define CONFIG_SYS_FSL_ERRATUM_A004477 168 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 169 #define CONFIG_ESDHC_HC_BLK_ADDR 170 171 /* P1011 is single core version of P1020 */ 172 #elif defined(CONFIG_P1011) 173 #define CONFIG_MAX_CPUS 1 174 #define CONFIG_SYS_FSL_NUM_LAWS 12 175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 176 #define CONFIG_TSECV2 177 #define CONFIG_FSL_PCIE_DISABLE_ASPM 178 #define CONFIG_SYS_FSL_SEC_COMPAT 2 179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 180 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 181 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 182 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 183 #define CONFIG_SYS_FSL_ERRATUM_A004508 184 #define CONFIG_SYS_FSL_ERRATUM_A005125 185 186 /* P1012 is single core version of P1021 */ 187 #elif defined(CONFIG_P1012) 188 #define CONFIG_MAX_CPUS 1 189 #define CONFIG_SYS_FSL_NUM_LAWS 12 190 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 191 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 192 #define CONFIG_TSECV2 193 #define CONFIG_FSL_PCIE_DISABLE_ASPM 194 #define CONFIG_SYS_FSL_SEC_COMPAT 2 195 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 196 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 197 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 198 #define QE_MURAM_SIZE 0x6000UL 199 #define MAX_QE_RISC 1 200 #define QE_NUM_OF_SNUM 28 201 #define CONFIG_SYS_FSL_ERRATUM_A004508 202 #define CONFIG_SYS_FSL_ERRATUM_A005125 203 204 /* P1013 is single core version of P1022 */ 205 #elif defined(CONFIG_P1013) 206 #define CONFIG_MAX_CPUS 1 207 #define CONFIG_SYS_FSL_NUM_LAWS 12 208 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 209 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 210 #define CONFIG_TSECV2 211 #define CONFIG_SYS_FSL_SEC_COMPAT 2 212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 213 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 214 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 215 #define CONFIG_FSL_SATA_ERRATUM_A001 216 #define CONFIG_SYS_FSL_ERRATUM_A004508 217 #define CONFIG_SYS_FSL_ERRATUM_A005125 218 219 #elif defined(CONFIG_P1014) 220 #define CONFIG_MAX_CPUS 1 221 #define CONFIG_FSL_SDHC_V2_3 222 #define CONFIG_SYS_FSL_NUM_LAWS 12 223 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 224 #define CONFIG_TSECV2 225 #define CONFIG_SYS_FSL_SEC_COMPAT 4 226 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 227 #define CONFIG_NUM_DDR_CONTROLLERS 1 228 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 229 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 230 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 231 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 232 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 233 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 234 #define CONFIG_SYS_FSL_ERRATUM_A004508 235 236 /* P1017 is single core version of P1023 */ 237 #elif defined(CONFIG_P1017) 238 #define CONFIG_MAX_CPUS 1 239 #define CONFIG_SYS_FSL_NUM_LAWS 12 240 #define CONFIG_SYS_FSL_SEC_COMPAT 4 241 #define CONFIG_SYS_NUM_FMAN 1 242 #define CONFIG_SYS_NUM_FM1_DTSEC 2 243 #define CONFIG_NUM_DDR_CONTROLLERS 1 244 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 245 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 246 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 247 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 248 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 249 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 250 #define CONFIG_SYS_FSL_ERRATUM_A004508 251 #define CONFIG_SYS_FSL_ERRATUM_A005125 252 253 #elif defined(CONFIG_P1020) 254 #define CONFIG_MAX_CPUS 2 255 #define CONFIG_SYS_FSL_NUM_LAWS 12 256 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 257 #define CONFIG_TSECV2 258 #define CONFIG_FSL_PCIE_DISABLE_ASPM 259 #define CONFIG_SYS_FSL_SEC_COMPAT 2 260 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 261 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 262 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 263 #define CONFIG_SYS_FSL_ERRATUM_A004508 264 #define CONFIG_SYS_FSL_ERRATUM_A005125 265 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 266 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 267 #endif 268 269 #elif defined(CONFIG_P1021) 270 #define CONFIG_MAX_CPUS 2 271 #define CONFIG_SYS_FSL_NUM_LAWS 12 272 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 273 #define CONFIG_TSECV2 274 #define CONFIG_FSL_PCIE_DISABLE_ASPM 275 #define CONFIG_SYS_FSL_SEC_COMPAT 2 276 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 277 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 278 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 279 #define QE_MURAM_SIZE 0x6000UL 280 #define MAX_QE_RISC 1 281 #define QE_NUM_OF_SNUM 28 282 #define CONFIG_SYS_FSL_ERRATUM_A004508 283 #define CONFIG_SYS_FSL_ERRATUM_A005125 284 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 285 286 #elif defined(CONFIG_P1022) 287 #define CONFIG_MAX_CPUS 2 288 #define CONFIG_SYS_FSL_NUM_LAWS 12 289 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 290 #define CONFIG_TSECV2 291 #define CONFIG_SYS_FSL_SEC_COMPAT 2 292 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 293 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 294 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 295 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 296 #define CONFIG_FSL_SATA_ERRATUM_A001 297 #define CONFIG_SYS_FSL_ERRATUM_A004508 298 #define CONFIG_SYS_FSL_ERRATUM_A005125 299 #define CONFIG_SYS_FSL_ERRATUM_A004477 300 301 #elif defined(CONFIG_P1023) 302 #define CONFIG_MAX_CPUS 2 303 #define CONFIG_SYS_FSL_NUM_LAWS 12 304 #define CONFIG_SYS_FSL_SEC_COMPAT 4 305 #define CONFIG_SYS_NUM_FMAN 1 306 #define CONFIG_SYS_NUM_FM1_DTSEC 2 307 #define CONFIG_NUM_DDR_CONTROLLERS 1 308 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 309 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 310 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 311 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 312 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 313 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 314 #define CONFIG_SYS_FSL_ERRATUM_A004508 315 #define CONFIG_SYS_FSL_ERRATUM_A005125 316 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 317 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 318 319 /* P1024 is lower end variant of P1020 */ 320 #elif defined(CONFIG_P1024) 321 #define CONFIG_MAX_CPUS 2 322 #define CONFIG_SYS_FSL_NUM_LAWS 12 323 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 324 #define CONFIG_TSECV2 325 #define CONFIG_FSL_PCIE_DISABLE_ASPM 326 #define CONFIG_SYS_FSL_SEC_COMPAT 2 327 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 328 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 329 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 330 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 331 #define CONFIG_SYS_FSL_ERRATUM_A004508 332 #define CONFIG_SYS_FSL_ERRATUM_A005125 333 334 /* P1025 is lower end variant of P1021 */ 335 #elif defined(CONFIG_P1025) 336 #define CONFIG_MAX_CPUS 2 337 #define CONFIG_SYS_FSL_NUM_LAWS 12 338 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 339 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 340 #define CONFIG_TSECV2 341 #define CONFIG_FSL_PCIE_DISABLE_ASPM 342 #define CONFIG_SYS_FSL_SEC_COMPAT 2 343 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 344 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 345 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 346 #define QE_MURAM_SIZE 0x6000UL 347 #define MAX_QE_RISC 1 348 #define QE_NUM_OF_SNUM 28 349 #define CONFIG_SYS_FSL_ERRATUM_A004508 350 #define CONFIG_SYS_FSL_ERRATUM_A005125 351 352 /* P2010 is single core version of P2020 */ 353 #elif defined(CONFIG_P2010) 354 #define CONFIG_MAX_CPUS 1 355 #define CONFIG_SYS_FSL_NUM_LAWS 12 356 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 357 #define CONFIG_SYS_FSL_SEC_COMPAT 2 358 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 359 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 360 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 361 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 362 #define CONFIG_SYS_FSL_ERRATUM_A004508 363 #define CONFIG_SYS_FSL_ERRATUM_A005125 364 365 #elif defined(CONFIG_P2020) 366 #define CONFIG_MAX_CPUS 2 367 #define CONFIG_SYS_FSL_NUM_LAWS 12 368 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 369 #define CONFIG_SYS_FSL_SEC_COMPAT 2 370 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 371 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 372 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 373 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 374 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 375 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 376 #define CONFIG_SYS_FSL_RMU 377 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 378 #define CONFIG_SYS_FSL_ERRATUM_A004508 379 #define CONFIG_SYS_FSL_ERRATUM_A005125 380 #define CONFIG_SYS_FSL_ERRATUM_A004477 381 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 382 383 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 384 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 385 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 386 #define CONFIG_MAX_CPUS 4 387 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 388 #define CONFIG_SYS_FSL_NUM_LAWS 32 389 #define CONFIG_SYS_FSL_SEC_COMPAT 4 390 #define CONFIG_SYS_NUM_FMAN 1 391 #define CONFIG_SYS_NUM_FM1_DTSEC 5 392 #define CONFIG_SYS_NUM_FM1_10GEC 1 393 #define CONFIG_NUM_DDR_CONTROLLERS 1 394 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 395 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 396 #define CONFIG_SYS_FSL_TBCLK_DIV 32 397 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 398 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 399 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 400 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 401 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 402 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 403 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 404 #define CONFIG_SYS_FSL_ERRATUM_USB14 405 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 406 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 407 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 408 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 409 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 410 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 411 #define CONFIG_SYS_FSL_ERRATUM_A004510 412 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 413 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 414 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 415 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 416 #define CONFIG_SYS_FSL_ERRATUM_A004849 417 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 418 #define CONFIG_SYS_FSL_ERRATUM_A006261 419 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 420 421 #elif defined(CONFIG_PPC_P3041) 422 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 423 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 424 #define CONFIG_MAX_CPUS 4 425 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 426 #define CONFIG_SYS_FSL_NUM_LAWS 32 427 #define CONFIG_SYS_FSL_SEC_COMPAT 4 428 #define CONFIG_SYS_NUM_FMAN 1 429 #define CONFIG_SYS_NUM_FM1_DTSEC 5 430 #define CONFIG_SYS_NUM_FM1_10GEC 1 431 #define CONFIG_NUM_DDR_CONTROLLERS 1 432 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 433 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 434 #define CONFIG_SYS_FSL_TBCLK_DIV 32 435 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 436 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 437 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 438 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 439 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 440 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 441 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 442 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 443 #define CONFIG_SYS_FSL_ERRATUM_USB14 444 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 445 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 446 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 447 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 448 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 449 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 450 #define CONFIG_SYS_FSL_ERRATUM_A004510 451 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 452 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 453 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 454 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 455 #define CONFIG_SYS_FSL_ERRATUM_A004849 456 #define CONFIG_SYS_FSL_ERRATUM_A005812 457 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 458 #define CONFIG_SYS_FSL_ERRATUM_A006261 459 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 460 461 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 462 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 463 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 464 #define CONFIG_MAX_CPUS 8 465 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 466 #define CONFIG_SYS_FSL_NUM_LAWS 32 467 #define CONFIG_SYS_FSL_SEC_COMPAT 4 468 #define CONFIG_SYS_NUM_FMAN 2 469 #define CONFIG_SYS_NUM_FM1_DTSEC 4 470 #define CONFIG_SYS_NUM_FM2_DTSEC 4 471 #define CONFIG_SYS_NUM_FM1_10GEC 1 472 #define CONFIG_SYS_NUM_FM2_10GEC 1 473 #define CONFIG_NUM_DDR_CONTROLLERS 2 474 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 475 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 476 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 477 #define CONFIG_SYS_FSL_TBCLK_DIV 16 478 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 479 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 480 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 481 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 482 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 483 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 484 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 485 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 486 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 487 #define CONFIG_SYS_P4080_ERRATUM_CPU22 488 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 489 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 490 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 491 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 492 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 493 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 494 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 495 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 496 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 497 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 498 #define CONFIG_SYS_FSL_RMU 499 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 500 #define CONFIG_SYS_FSL_ERRATUM_A004510 501 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 502 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 503 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 504 #define CONFIG_SYS_FSL_ERRATUM_A004849 505 #define CONFIG_SYS_FSL_ERRATUM_A004580 506 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 507 #define CONFIG_SYS_FSL_ERRATUM_A005812 508 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 509 #define CONFIG_SYS_FSL_ERRATUM_A007075 510 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 511 512 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 513 #define CONFIG_SYS_PPC64 /* 64-bit core */ 514 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 515 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 516 #define CONFIG_MAX_CPUS 2 517 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 518 #define CONFIG_SYS_FSL_NUM_LAWS 32 519 #define CONFIG_SYS_FSL_SEC_COMPAT 4 520 #define CONFIG_SYS_NUM_FMAN 1 521 #define CONFIG_SYS_NUM_FM1_DTSEC 5 522 #define CONFIG_SYS_NUM_FM1_10GEC 1 523 #define CONFIG_NUM_DDR_CONTROLLERS 2 524 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 525 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 526 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 527 #define CONFIG_SYS_FSL_TBCLK_DIV 32 528 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 529 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 530 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 531 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 532 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 533 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 534 #define CONFIG_SYS_FSL_ERRATUM_USB14 535 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 536 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 537 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 538 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 539 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 540 #define CONFIG_SYS_FSL_ERRATUM_A004510 541 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 542 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 543 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 544 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 545 #define CONFIG_SYS_FSL_ERRATUM_A006261 546 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 547 548 #elif defined(CONFIG_PPC_P5040) 549 #define CONFIG_SYS_PPC64 550 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 551 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 552 #define CONFIG_MAX_CPUS 4 553 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 554 #define CONFIG_SYS_FSL_NUM_LAWS 32 555 #define CONFIG_SYS_FSL_SEC_COMPAT 4 556 #define CONFIG_SYS_NUM_FMAN 2 557 #define CONFIG_SYS_NUM_FM1_DTSEC 5 558 #define CONFIG_SYS_NUM_FM1_10GEC 1 559 #define CONFIG_SYS_NUM_FM2_DTSEC 5 560 #define CONFIG_SYS_NUM_FM2_10GEC 1 561 #define CONFIG_NUM_DDR_CONTROLLERS 2 562 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 563 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 564 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 565 #define CONFIG_SYS_FSL_TBCLK_DIV 16 566 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 567 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 568 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 569 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 570 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 571 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 572 #define CONFIG_SYS_FSL_ERRATUM_USB14 573 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 574 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 575 #define CONFIG_SYS_FSL_ERRATUM_A004699 576 #define CONFIG_SYS_FSL_ERRATUM_A004510 577 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 578 #define CONFIG_SYS_FSL_ERRATUM_A006261 579 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 580 #define CONFIG_SYS_FSL_ERRATUM_A005812 581 582 #elif defined(CONFIG_BSC9131) 583 #define CONFIG_MAX_CPUS 1 584 #define CONFIG_FSL_SDHC_V2_3 585 #define CONFIG_SYS_FSL_NUM_LAWS 12 586 #define CONFIG_TSECV2 587 #define CONFIG_SYS_FSL_SEC_COMPAT 4 588 #define CONFIG_NUM_DDR_CONTROLLERS 1 589 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 590 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 591 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 592 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 593 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 594 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 595 #define CONFIG_NAND_FSL_IFC 596 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 597 #define CONFIG_SYS_FSL_ERRATUM_A005125 598 #define CONFIG_SYS_FSL_ERRATUM_A004477 599 #define CONFIG_ESDHC_HC_BLK_ADDR 600 601 #elif defined(CONFIG_BSC9132) 602 #define CONFIG_MAX_CPUS 2 603 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 604 #define CONFIG_FSL_SDHC_V2_3 605 #define CONFIG_SYS_FSL_NUM_LAWS 12 606 #define CONFIG_TSECV2 607 #define CONFIG_SYS_FSL_SEC_COMPAT 4 608 #define CONFIG_NUM_DDR_CONTROLLERS 2 609 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 610 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 611 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 612 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 613 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 614 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 615 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 616 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 617 #define CONFIG_NAND_FSL_IFC 618 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 619 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 620 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 621 #define CONFIG_SYS_FSL_ERRATUM_A005125 622 #define CONFIG_SYS_FSL_ERRATUM_A005434 623 #define CONFIG_SYS_FSL_ERRATUM_A004477 624 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 625 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 626 #define CONFIG_ESDHC_HC_BLK_ADDR 627 628 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 629 defined(CONFIG_PPC_T4080) 630 #define CONFIG_E6500 631 #define CONFIG_SYS_PPC64 /* 64-bit core */ 632 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 633 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 634 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 635 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 636 #ifdef CONFIG_PPC_T4240 637 #define CONFIG_MAX_CPUS 12 638 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 639 #define CONFIG_SYS_NUM_FM1_DTSEC 8 640 #define CONFIG_SYS_NUM_FM1_10GEC 2 641 #define CONFIG_SYS_NUM_FM2_DTSEC 8 642 #define CONFIG_SYS_NUM_FM2_10GEC 2 643 #define CONFIG_NUM_DDR_CONTROLLERS 3 644 #define CONFIG_SYS_FSL_ERRATUM_A006261 645 #else 646 #define CONFIG_SYS_NUM_FM1_DTSEC 6 647 #define CONFIG_SYS_NUM_FM1_10GEC 1 648 #define CONFIG_SYS_NUM_FM2_DTSEC 8 649 #define CONFIG_SYS_NUM_FM2_10GEC 1 650 #define CONFIG_NUM_DDR_CONTROLLERS 2 651 #if defined(CONFIG_PPC_T4160) 652 #define CONFIG_MAX_CPUS 8 653 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 654 #elif defined(CONFIG_PPC_T4080) 655 #define CONFIG_MAX_CPUS 4 656 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } 657 #endif 658 #endif 659 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 660 #define CONFIG_SYS_FSL_NUM_LAWS 32 661 #define CONFIG_SYS_FSL_SRDS_1 662 #define CONFIG_SYS_FSL_SRDS_2 663 #define CONFIG_SYS_FSL_SRDS_3 664 #define CONFIG_SYS_FSL_SRDS_4 665 #define CONFIG_SYS_FSL_SEC_COMPAT 4 666 #define CONFIG_SYS_NUM_FMAN 2 667 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 668 #define CONFIG_SYS_PME_CLK 0 669 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 670 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 671 #define CONFIG_SYS_FMAN_V3 672 #define CONFIG_SYS_FM1_CLK 3 673 #define CONFIG_SYS_FM2_CLK 3 674 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 675 #define CONFIG_SYS_FSL_TBCLK_DIV 16 676 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 677 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 678 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 679 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 680 #define CONFIG_SYS_FSL_SRIO_LIODN 681 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 682 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 683 #define CONFIG_SYS_FSL_ERRATUM_A004468 684 #define CONFIG_SYS_FSL_ERRATUM_A_004934 685 #define CONFIG_SYS_FSL_ERRATUM_A005871 686 #define CONFIG_SYS_FSL_ERRATUM_A006379 687 #define CONFIG_SYS_FSL_ERRATUM_A007186 688 #define CONFIG_SYS_FSL_ERRATUM_A006593 689 #define CONFIG_SYS_FSL_ERRATUM_A007798 690 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 691 #define CONFIG_SYS_FSL_SFP_VER_3_0 692 #define CONFIG_SYS_FSL_PCI_VER_3_X 693 694 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 695 #define CONFIG_E6500 696 #define CONFIG_SYS_PPC64 /* 64-bit core */ 697 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 698 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 699 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 700 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 701 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 702 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 703 #define CONFIG_SYS_FSL_NUM_LAWS 32 704 #define CONFIG_SYS_FSL_SRDS_1 705 #define CONFIG_SYS_FSL_SRDS_2 706 #define CONFIG_SYS_MAPLE 707 #define CONFIG_SYS_CPRI 708 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 709 #define CONFIG_SYS_FSL_SEC_COMPAT 4 710 #define CONFIG_SYS_NUM_FMAN 1 711 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 712 #define CONFIG_SYS_FM1_CLK 0 713 #define CONFIG_SYS_CPRI_CLK 3 714 #define CONFIG_SYS_ULB_CLK 4 715 #define CONFIG_SYS_ETVPE_CLK 1 716 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 717 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 718 #define CONFIG_SYS_FMAN_V3 719 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 720 #define CONFIG_SYS_FSL_TBCLK_DIV 16 721 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 722 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 723 #define CONFIG_SYS_FSL_ERRATUM_A_004934 724 #define CONFIG_SYS_FSL_ERRATUM_A005871 725 #define CONFIG_SYS_FSL_ERRATUM_A006379 726 #define CONFIG_SYS_FSL_ERRATUM_A007186 727 #define CONFIG_SYS_FSL_ERRATUM_A006593 728 #define CONFIG_SYS_FSL_ERRATUM_A007075 729 #define CONFIG_SYS_FSL_ERRATUM_A006475 730 #define CONFIG_SYS_FSL_ERRATUM_A006384 731 #define CONFIG_SYS_FSL_ERRATUM_A007212 732 #define CONFIG_SYS_FSL_ERRATUM_A004477 733 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 734 #define CONFIG_SYS_FSL_SFP_VER_3_0 735 736 #ifdef CONFIG_PPC_B4860 737 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 738 #define CONFIG_MAX_CPUS 4 739 #define CONFIG_MAX_DSP_CPUS 12 740 #define CONFIG_NUM_DSP_CPUS 6 741 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 742 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 743 #define CONFIG_SYS_NUM_FM1_DTSEC 6 744 #define CONFIG_SYS_NUM_FM1_10GEC 2 745 #define CONFIG_NUM_DDR_CONTROLLERS 2 746 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 747 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 748 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 749 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 750 #define CONFIG_SYS_FSL_SRIO_LIODN 751 #else 752 #define CONFIG_MAX_CPUS 2 753 #define CONFIG_MAX_DSP_CPUS 2 754 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 755 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 756 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 757 #define CONFIG_SYS_NUM_FM1_DTSEC 4 758 #define CONFIG_SYS_NUM_FM1_10GEC 0 759 #define CONFIG_NUM_DDR_CONTROLLERS 1 760 #endif 761 762 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 763 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 764 #define CONFIG_E5500 765 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 766 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 767 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 768 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 769 #ifdef CONFIG_SYS_FSL_DDR4 770 #define CONFIG_SYS_FSL_DDRC_GEN4 771 #endif 772 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 773 #define CONFIG_MAX_CPUS 4 774 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 775 #define CONFIG_MAX_CPUS 2 776 #endif 777 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 778 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 779 #define CONFIG_SYS_FSL_NUM_LAWS 16 780 #define CONFIG_SYS_FSL_SRDS_1 781 #define CONFIG_SYS_FSL_SEC_COMPAT 5 782 #define CONFIG_SYS_NUM_FMAN 1 783 #define CONFIG_SYS_NUM_FM1_DTSEC 5 784 #define CONFIG_NUM_DDR_CONTROLLERS 1 785 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 786 #define CONFIG_PME_PLAT_CLK_DIV 2 787 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 788 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 789 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 790 #define CONFIG_SYS_FSL_ERRATUM_A008044 791 #define CONFIG_SYS_FMAN_V3 792 #define CONFIG_FM_PLAT_CLK_DIV 1 793 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 794 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 795 per rcw field value */ 796 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 797 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 798 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 799 #define CONFIG_SYS_FSL_TBCLK_DIV 16 800 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 801 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 802 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 803 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 804 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 805 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 806 #define QE_MURAM_SIZE 0x6000UL 807 #define MAX_QE_RISC 1 808 #define QE_NUM_OF_SNUM 28 809 #define CONFIG_SYS_FSL_SFP_VER_3_0 810 #define CONFIG_SYS_FSL_ERRATUM_A008378 811 #define CONFIG_SYS_FSL_ERRATUM_A009663 812 813 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ 814 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 815 #define CONFIG_E5500 816 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 817 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 818 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 819 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 820 #define CONFIG_SYS_FMAN_V3 821 #ifdef CONFIG_SYS_FSL_DDR4 822 #define CONFIG_SYS_FSL_DDRC_GEN4 823 #endif 824 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) 825 #define CONFIG_MAX_CPUS 2 826 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 827 #define CONFIG_MAX_CPUS 1 828 #endif 829 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 830 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 831 #define CONFIG_SYS_FSL_NUM_LAWS 16 832 #define CONFIG_SYS_FSL_SRDS_1 833 #define CONFIG_SYS_FSL_SEC_COMPAT 5 834 #define CONFIG_SYS_NUM_FMAN 1 835 #define CONFIG_SYS_NUM_FM1_DTSEC 4 836 #define CONFIG_SYS_NUM_FM1_10GEC 1 837 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 838 #define CONFIG_NUM_DDR_CONTROLLERS 1 839 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 840 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 841 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 842 #define CONFIG_SYS_FM1_CLK 0 843 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 844 per rcw field value */ 845 #define CONFIG_QBMAN_CLK_DIV 1 846 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 847 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 848 #define CONFIG_SYS_FSL_TBCLK_DIV 16 849 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 850 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 851 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 852 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 853 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 854 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 855 #define QE_MURAM_SIZE 0x6000UL 856 #define MAX_QE_RISC 1 857 #define QE_NUM_OF_SNUM 28 858 #define CONFIG_SYS_FSL_SFP_VER_3_0 859 #define CONFIG_SYS_FSL_ERRATUM_A008378 860 #define CONFIG_SYS_FSL_ERRATUM_A009663 861 862 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 863 #define CONFIG_E6500 864 #define CONFIG_SYS_PPC64 /* 64-bit core */ 865 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 866 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 867 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 868 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 869 #define CONFIG_SYS_FSL_QMAN_V3 870 #define CONFIG_MAX_CPUS 4 871 #define CONFIG_SYS_FSL_NUM_LAWS 32 872 #define CONFIG_SYS_FSL_SEC_COMPAT 4 873 #define CONFIG_SYS_NUM_FMAN 1 874 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 875 #define CONFIG_SYS_FSL_SRDS_1 876 #define CONFIG_SYS_FSL_PCI_VER_3_X 877 #if defined(CONFIG_PPC_T2080) 878 #define CONFIG_SYS_NUM_FM1_DTSEC 8 879 #define CONFIG_SYS_NUM_FM1_10GEC 4 880 #define CONFIG_SYS_FSL_SRDS_2 881 #define CONFIG_SYS_FSL_SRIO_LIODN 882 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 883 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 884 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 885 #elif defined(CONFIG_PPC_T2081) 886 #define CONFIG_SYS_NUM_FM1_DTSEC 6 887 #define CONFIG_SYS_NUM_FM1_10GEC 2 888 #endif 889 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 890 #define CONFIG_NUM_DDR_CONTROLLERS 1 891 #define CONFIG_PME_PLAT_CLK_DIV 1 892 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 893 #define CONFIG_SYS_FM1_CLK 0 894 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 895 per rcw field value */ 896 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 897 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 898 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 899 #define CONFIG_SYS_FMAN_V3 900 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 901 #define CONFIG_SYS_FSL_TBCLK_DIV 16 902 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 903 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 904 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 905 #define CONFIG_SYS_FSL_ERRATUM_A007212 906 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 907 #define CONFIG_SYS_FSL_SFP_VER_3_0 908 #define CONFIG_SYS_FSL_ISBC_VER 2 909 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 910 #define CONFIG_SYS_FSL_ERRATUM_A006593 911 #define CONFIG_SYS_FSL_ERRATUM_A007186 912 #define CONFIG_SYS_FSL_ERRATUM_A006379 913 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 914 #define CONFIG_SYS_FSL_SFP_VER_3_0 915 916 917 #elif defined(CONFIG_PPC_C29X) 918 #define CONFIG_MAX_CPUS 1 919 #define CONFIG_FSL_SDHC_V2_3 920 #define CONFIG_SYS_FSL_NUM_LAWS 12 921 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 922 #define CONFIG_TSECV2_1 923 #define CONFIG_SYS_FSL_SEC_COMPAT 6 924 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 925 #define CONFIG_NUM_DDR_CONTROLLERS 1 926 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 927 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 928 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 929 #define CONFIG_SYS_FSL_ERRATUM_A005125 930 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 931 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 932 933 #elif defined(CONFIG_QEMU_E500) 934 #define CONFIG_MAX_CPUS 1 935 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 936 937 #else 938 #error Processor type not defined for this platform 939 #endif 940 941 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 942 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 943 #endif 944 945 #ifdef CONFIG_E6500 946 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 947 #else 948 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 949 #endif 950 951 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 952 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 953 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 954 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 955 #define CONFIG_SYS_FSL_DDRC_GEN3 956 #endif 957 958 #if !defined(CONFIG_PPC_C29X) 959 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 960 #endif 961 962 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 963