1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 /* Number of TLB CAM entries we have on FSL Book-E chips */ 27 #if defined(CONFIG_E500MC) 28 #define CONFIG_SYS_NUM_TLBCAMS 64 29 #elif defined(CONFIG_E500) 30 #define CONFIG_SYS_NUM_TLBCAMS 16 31 #endif 32 33 #if defined(CONFIG_MPC8536) 34 #define CONFIG_MAX_CPUS 1 35 #define CONFIG_SYS_FSL_NUM_LAWS 12 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 37 38 #elif defined(CONFIG_MPC8540) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 8 41 42 #elif defined(CONFIG_MPC8541) 43 #define CONFIG_MAX_CPUS 1 44 #define CONFIG_SYS_FSL_NUM_LAWS 8 45 #define CONFIG_SYS_FSL_SEC_COMPAT 2 46 47 #elif defined(CONFIG_MPC8544) 48 #define CONFIG_MAX_CPUS 1 49 #define CONFIG_SYS_FSL_NUM_LAWS 10 50 #define CONFIG_SYS_FSL_SEC_COMPAT 2 51 52 #elif defined(CONFIG_MPC8548) 53 #define CONFIG_MAX_CPUS 1 54 #define CONFIG_SYS_FSL_NUM_LAWS 10 55 #define CONFIG_SYS_FSL_SEC_COMPAT 2 56 57 #elif defined(CONFIG_MPC8555) 58 #define CONFIG_MAX_CPUS 1 59 #define CONFIG_SYS_FSL_NUM_LAWS 8 60 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 62 #elif defined(CONFIG_MPC8560) 63 #define CONFIG_MAX_CPUS 1 64 #define CONFIG_SYS_FSL_NUM_LAWS 8 65 66 #elif defined(CONFIG_MPC8568) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 10 69 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define QE_MURAM_SIZE 0x10000UL 71 #define MAX_QE_RISC 2 72 #define QE_NUM_OF_SNUM 28 73 74 #elif defined(CONFIG_MPC8569) 75 #define CONFIG_MAX_CPUS 1 76 #define CONFIG_SYS_FSL_NUM_LAWS 10 77 #define CONFIG_SYS_FSL_SEC_COMPAT 2 78 #define QE_MURAM_SIZE 0x20000UL 79 #define MAX_QE_RISC 4 80 #define QE_NUM_OF_SNUM 46 81 82 #elif defined(CONFIG_MPC8572) 83 #define CONFIG_MAX_CPUS 2 84 #define CONFIG_SYS_FSL_NUM_LAWS 12 85 #define CONFIG_SYS_FSL_SEC_COMPAT 2 86 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 87 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 88 89 #elif defined(CONFIG_P1010) 90 #define CONFIG_MAX_CPUS 1 91 #define CONFIG_FSL_SDHC_V2_3 92 #define CONFIG_SYS_FSL_NUM_LAWS 12 93 #define CONFIG_TSECV2 94 #define CONFIG_SYS_FSL_SEC_COMPAT 4 95 #define CONFIG_FSL_SATA_V2 96 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 97 #define CONFIG_NUM_DDR_CONTROLLERS 1 98 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 99 100 /* P1011 is single core version of P1020 */ 101 #elif defined(CONFIG_P1011) 102 #define CONFIG_MAX_CPUS 1 103 #define CONFIG_SYS_FSL_NUM_LAWS 12 104 #define CONFIG_TSECV2 105 #define CONFIG_FSL_PCIE_DISABLE_ASPM 106 #define CONFIG_SYS_FSL_SEC_COMPAT 2 107 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 108 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 109 110 /* P1012 is single core version of P1021 */ 111 #elif defined(CONFIG_P1012) 112 #define CONFIG_MAX_CPUS 1 113 #define CONFIG_SYS_FSL_NUM_LAWS 12 114 #define CONFIG_TSECV2 115 #define CONFIG_FSL_PCIE_DISABLE_ASPM 116 #define CONFIG_SYS_FSL_SEC_COMPAT 2 117 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 118 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 119 #define QE_MURAM_SIZE 0x6000UL 120 #define MAX_QE_RISC 1 121 #define QE_NUM_OF_SNUM 28 122 123 /* P1013 is single core version of P1022 */ 124 #elif defined(CONFIG_P1013) 125 #define CONFIG_MAX_CPUS 1 126 #define CONFIG_SYS_FSL_NUM_LAWS 12 127 #define CONFIG_TSECV2 128 #define CONFIG_SYS_FSL_SEC_COMPAT 2 129 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 130 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 131 #define CONFIG_FSL_SATA_ERRATUM_A001 132 133 #elif defined(CONFIG_P1014) 134 #define CONFIG_MAX_CPUS 1 135 #define CONFIG_FSL_SDHC_V2_3 136 #define CONFIG_SYS_FSL_NUM_LAWS 12 137 #define CONFIG_TSECV2 138 #define CONFIG_SYS_FSL_SEC_COMPAT 4 139 #define CONFIG_FSL_SATA_V2 140 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 141 #define CONFIG_NUM_DDR_CONTROLLERS 1 142 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 143 144 /* P1015 is single core version of P1024 */ 145 #elif defined(CONFIG_P1015) 146 #define CONFIG_MAX_CPUS 1 147 #define CONFIG_SYS_FSL_NUM_LAWS 12 148 #define CONFIG_TSECV2 149 #define CONFIG_FSL_PCIE_DISABLE_ASPM 150 #define CONFIG_SYS_FSL_SEC_COMPAT 2 151 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 152 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 153 154 /* P1016 is single core version of P1025 */ 155 #elif defined(CONFIG_P1016) 156 #define CONFIG_MAX_CPUS 1 157 #define CONFIG_SYS_FSL_NUM_LAWS 12 158 #define CONFIG_TSECV2 159 #define CONFIG_FSL_PCIE_DISABLE_ASPM 160 #define CONFIG_SYS_FSL_SEC_COMPAT 2 161 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 162 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 163 #define QE_MURAM_SIZE 0x6000UL 164 #define MAX_QE_RISC 1 165 #define QE_NUM_OF_SNUM 28 166 167 /* P1017 is single core version of P1023 */ 168 #elif defined(CONFIG_P1017) 169 #define CONFIG_MAX_CPUS 1 170 #define CONFIG_SYS_FSL_NUM_LAWS 12 171 #define CONFIG_SYS_FSL_SEC_COMPAT 4 172 #define CONFIG_SYS_NUM_FMAN 1 173 #define CONFIG_SYS_NUM_FM1_DTSEC 2 174 #define CONFIG_NUM_DDR_CONTROLLERS 1 175 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 176 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 177 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 178 179 #elif defined(CONFIG_P1020) 180 #define CONFIG_MAX_CPUS 2 181 #define CONFIG_SYS_FSL_NUM_LAWS 12 182 #define CONFIG_TSECV2 183 #define CONFIG_FSL_PCIE_DISABLE_ASPM 184 #define CONFIG_SYS_FSL_SEC_COMPAT 2 185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 187 188 #elif defined(CONFIG_P1021) 189 #define CONFIG_MAX_CPUS 2 190 #define CONFIG_SYS_FSL_NUM_LAWS 12 191 #define CONFIG_TSECV2 192 #define CONFIG_FSL_PCIE_DISABLE_ASPM 193 #define CONFIG_SYS_FSL_SEC_COMPAT 2 194 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 195 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 196 #define QE_MURAM_SIZE 0x6000UL 197 #define MAX_QE_RISC 1 198 #define QE_NUM_OF_SNUM 28 199 200 #elif defined(CONFIG_P1022) 201 #define CONFIG_MAX_CPUS 2 202 #define CONFIG_SYS_FSL_NUM_LAWS 12 203 #define CONFIG_TSECV2 204 #define CONFIG_SYS_FSL_SEC_COMPAT 2 205 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 206 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 207 #define CONFIG_FSL_SATA_ERRATUM_A001 208 209 #elif defined(CONFIG_P1023) 210 #define CONFIG_MAX_CPUS 2 211 #define CONFIG_SYS_FSL_NUM_LAWS 12 212 #define CONFIG_SYS_FSL_SEC_COMPAT 4 213 #define CONFIG_SYS_NUM_FMAN 1 214 #define CONFIG_SYS_NUM_FM1_DTSEC 2 215 #define CONFIG_NUM_DDR_CONTROLLERS 1 216 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 217 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 218 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 219 220 /* P1024 is lower end variant of P1020 */ 221 #elif defined(CONFIG_P1024) 222 #define CONFIG_MAX_CPUS 2 223 #define CONFIG_SYS_FSL_NUM_LAWS 12 224 #define CONFIG_TSECV2 225 #define CONFIG_FSL_PCIE_DISABLE_ASPM 226 #define CONFIG_SYS_FSL_SEC_COMPAT 2 227 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 228 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 229 230 /* P1025 is lower end variant of P1021 */ 231 #elif defined(CONFIG_P1025) 232 #define CONFIG_MAX_CPUS 2 233 #define CONFIG_SYS_FSL_NUM_LAWS 12 234 #define CONFIG_TSECV2 235 #define CONFIG_FSL_PCIE_DISABLE_ASPM 236 #define CONFIG_SYS_FSL_SEC_COMPAT 2 237 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 238 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 239 #define QE_MURAM_SIZE 0x6000UL 240 #define MAX_QE_RISC 1 241 #define QE_NUM_OF_SNUM 28 242 243 /* P2010 is single core version of P2020 */ 244 #elif defined(CONFIG_P2010) 245 #define CONFIG_MAX_CPUS 1 246 #define CONFIG_SYS_FSL_NUM_LAWS 12 247 #define CONFIG_SYS_FSL_SEC_COMPAT 2 248 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 249 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 250 251 #elif defined(CONFIG_P2020) 252 #define CONFIG_MAX_CPUS 2 253 #define CONFIG_SYS_FSL_NUM_LAWS 12 254 #define CONFIG_SYS_FSL_SEC_COMPAT 2 255 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 256 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 257 258 #elif defined(CONFIG_PPC_P2040) 259 #define CONFIG_MAX_CPUS 4 260 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 261 #define CONFIG_SYS_FSL_NUM_LAWS 32 262 #define CONFIG_SYS_FSL_SEC_COMPAT 4 263 #define CONFIG_SYS_NUM_FMAN 1 264 #define CONFIG_SYS_NUM_FM1_DTSEC 5 265 #define CONFIG_NUM_DDR_CONTROLLERS 1 266 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 267 268 #elif defined(CONFIG_PPC_P3041) 269 #define CONFIG_MAX_CPUS 4 270 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 271 #define CONFIG_SYS_FSL_NUM_LAWS 32 272 #define CONFIG_SYS_FSL_SEC_COMPAT 4 273 #define CONFIG_SYS_NUM_FMAN 1 274 #define CONFIG_SYS_NUM_FM1_DTSEC 5 275 #define CONFIG_SYS_NUM_FM1_10GEC 1 276 #define CONFIG_NUM_DDR_CONTROLLERS 1 277 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 278 279 #elif defined(CONFIG_PPC_P4040) 280 #define CONFIG_MAX_CPUS 4 281 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 282 #define CONFIG_SYS_FSL_NUM_LAWS 32 283 #define CONFIG_SYS_FSL_SEC_COMPAT 4 284 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 285 286 #elif defined(CONFIG_PPC_P4080) 287 #define CONFIG_MAX_CPUS 8 288 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 289 #define CONFIG_SYS_FSL_NUM_LAWS 32 290 #define CONFIG_SYS_FSL_SEC_COMPAT 4 291 #define CONFIG_SYS_NUM_FMAN 2 292 #define CONFIG_SYS_NUM_FM1_DTSEC 4 293 #define CONFIG_SYS_NUM_FM2_DTSEC 4 294 #define CONFIG_SYS_NUM_FM1_10GEC 1 295 #define CONFIG_SYS_NUM_FM2_10GEC 1 296 #define CONFIG_NUM_DDR_CONTROLLERS 2 297 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 298 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 299 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 300 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 301 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 302 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 303 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 304 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 305 #define CONFIG_SYS_P4080_ERRATUM_CPU22 306 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 307 308 /* P5010 is single core version of P5020 */ 309 #elif defined(CONFIG_PPC_P5010) 310 #define CONFIG_MAX_CPUS 1 311 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 312 #define CONFIG_SYS_FSL_NUM_LAWS 32 313 #define CONFIG_SYS_FSL_SEC_COMPAT 4 314 #define CONFIG_SYS_NUM_FMAN 1 315 #define CONFIG_SYS_NUM_FM1_DTSEC 5 316 #define CONFIG_SYS_NUM_FM1_10GEC 1 317 #define CONFIG_NUM_DDR_CONTROLLERS 1 318 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 319 320 #elif defined(CONFIG_PPC_P5020) 321 #define CONFIG_MAX_CPUS 2 322 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 323 #define CONFIG_SYS_FSL_NUM_LAWS 32 324 #define CONFIG_SYS_FSL_SEC_COMPAT 4 325 #define CONFIG_SYS_NUM_FMAN 1 326 #define CONFIG_SYS_NUM_FM1_DTSEC 5 327 #define CONFIG_SYS_NUM_FM1_10GEC 1 328 #define CONFIG_NUM_DDR_CONTROLLERS 2 329 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 330 331 #else 332 #error Processor type not defined for this platform 333 #endif 334 335 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 336