1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_MPC85xx_CONFIG_H_ 22 #define _ASM_MPC85xx_CONFIG_H_ 23 24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 25 26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 28 #endif 29 30 #define FSL_DDR_VER_4_7 47 31 32 /* Number of TLB CAM entries we have on FSL Book-E chips */ 33 #if defined(CONFIG_E500MC) 34 #define CONFIG_SYS_NUM_TLBCAMS 64 35 #elif defined(CONFIG_E500) 36 #define CONFIG_SYS_NUM_TLBCAMS 16 37 #endif 38 39 #if defined(CONFIG_MPC8536) 40 #define CONFIG_MAX_CPUS 1 41 #define CONFIG_SYS_FSL_NUM_LAWS 12 42 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 43 #define CONFIG_SYS_FSL_SEC_COMPAT 2 44 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 45 46 #elif defined(CONFIG_MPC8540) 47 #define CONFIG_MAX_CPUS 1 48 #define CONFIG_SYS_FSL_NUM_LAWS 8 49 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 50 51 #elif defined(CONFIG_MPC8541) 52 #define CONFIG_MAX_CPUS 1 53 #define CONFIG_SYS_FSL_NUM_LAWS 8 54 #define CONFIG_SYS_FSL_SEC_COMPAT 2 55 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 56 57 #elif defined(CONFIG_MPC8544) 58 #define CONFIG_MAX_CPUS 1 59 #define CONFIG_SYS_FSL_NUM_LAWS 10 60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 61 #define CONFIG_SYS_FSL_SEC_COMPAT 2 62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 63 64 #elif defined(CONFIG_MPC8548) 65 #define CONFIG_MAX_CPUS 1 66 #define CONFIG_SYS_FSL_NUM_LAWS 10 67 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 68 #define CONFIG_SYS_FSL_SEC_COMPAT 2 69 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 70 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 71 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 72 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 73 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 74 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 75 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 76 #define CONFIG_SYS_FSL_RMU 77 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 78 79 #elif defined(CONFIG_MPC8555) 80 #define CONFIG_MAX_CPUS 1 81 #define CONFIG_SYS_FSL_NUM_LAWS 8 82 #define CONFIG_SYS_FSL_SEC_COMPAT 2 83 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 84 85 #elif defined(CONFIG_MPC8560) 86 #define CONFIG_MAX_CPUS 1 87 #define CONFIG_SYS_FSL_NUM_LAWS 8 88 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 89 90 #elif defined(CONFIG_MPC8568) 91 #define CONFIG_MAX_CPUS 1 92 #define CONFIG_SYS_FSL_NUM_LAWS 10 93 #define CONFIG_SYS_FSL_SEC_COMPAT 2 94 #define QE_MURAM_SIZE 0x10000UL 95 #define MAX_QE_RISC 2 96 #define QE_NUM_OF_SNUM 28 97 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 98 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 99 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 100 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 101 #define CONFIG_SYS_FSL_RMU 102 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 103 104 #elif defined(CONFIG_MPC8569) 105 #define CONFIG_MAX_CPUS 1 106 #define CONFIG_SYS_FSL_NUM_LAWS 10 107 #define CONFIG_SYS_FSL_SEC_COMPAT 2 108 #define QE_MURAM_SIZE 0x20000UL 109 #define MAX_QE_RISC 4 110 #define QE_NUM_OF_SNUM 46 111 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 112 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 113 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 114 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 115 #define CONFIG_SYS_FSL_RMU 116 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 117 118 #elif defined(CONFIG_MPC8572) 119 #define CONFIG_MAX_CPUS 2 120 #define CONFIG_SYS_FSL_NUM_LAWS 12 121 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 122 #define CONFIG_SYS_FSL_SEC_COMPAT 2 123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 124 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 125 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 126 127 #elif defined(CONFIG_P1010) 128 #define CONFIG_MAX_CPUS 1 129 #define CONFIG_FSL_SDHC_V2_3 130 #define CONFIG_SYS_FSL_NUM_LAWS 12 131 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 132 #define CONFIG_TSECV2 133 #define CONFIG_SYS_FSL_SEC_COMPAT 4 134 #define CONFIG_FSL_SATA_V2 135 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 136 #define CONFIG_NUM_DDR_CONTROLLERS 1 137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 138 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 139 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 140 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 141 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 142 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 143 144 /* P1011 is single core version of P1020 */ 145 #elif defined(CONFIG_P1011) 146 #define CONFIG_MAX_CPUS 1 147 #define CONFIG_SYS_FSL_NUM_LAWS 12 148 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 149 #define CONFIG_TSECV2 150 #define CONFIG_FSL_PCIE_DISABLE_ASPM 151 #define CONFIG_SYS_FSL_SEC_COMPAT 2 152 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 153 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 154 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 155 156 /* P1012 is single core version of P1021 */ 157 #elif defined(CONFIG_P1012) 158 #define CONFIG_MAX_CPUS 1 159 #define CONFIG_SYS_FSL_NUM_LAWS 12 160 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 161 #define CONFIG_TSECV2 162 #define CONFIG_FSL_PCIE_DISABLE_ASPM 163 #define CONFIG_SYS_FSL_SEC_COMPAT 2 164 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 165 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 166 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 167 #define QE_MURAM_SIZE 0x6000UL 168 #define MAX_QE_RISC 1 169 #define QE_NUM_OF_SNUM 28 170 171 /* P1013 is single core version of P1022 */ 172 #elif defined(CONFIG_P1013) 173 #define CONFIG_MAX_CPUS 1 174 #define CONFIG_SYS_FSL_NUM_LAWS 12 175 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 176 #define CONFIG_TSECV2 177 #define CONFIG_SYS_FSL_SEC_COMPAT 2 178 #define CONFIG_FSL_SATA_V2 179 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 180 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 181 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 182 #define CONFIG_FSL_SATA_ERRATUM_A001 183 184 #elif defined(CONFIG_P1014) 185 #define CONFIG_MAX_CPUS 1 186 #define CONFIG_FSL_SDHC_V2_3 187 #define CONFIG_SYS_FSL_NUM_LAWS 12 188 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 189 #define CONFIG_TSECV2 190 #define CONFIG_SYS_FSL_SEC_COMPAT 4 191 #define CONFIG_FSL_SATA_V2 192 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 193 #define CONFIG_NUM_DDR_CONTROLLERS 1 194 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 195 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 196 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 197 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 198 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 199 200 /* P1017 is single core version of P1023 */ 201 #elif defined(CONFIG_P1017) 202 #define CONFIG_MAX_CPUS 1 203 #define CONFIG_SYS_FSL_NUM_LAWS 12 204 #define CONFIG_SYS_FSL_SEC_COMPAT 4 205 #define CONFIG_SYS_NUM_FMAN 1 206 #define CONFIG_SYS_NUM_FM1_DTSEC 2 207 #define CONFIG_NUM_DDR_CONTROLLERS 1 208 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 209 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 210 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 211 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 213 214 #elif defined(CONFIG_P1020) 215 #define CONFIG_MAX_CPUS 2 216 #define CONFIG_SYS_FSL_NUM_LAWS 12 217 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 218 #define CONFIG_TSECV2 219 #define CONFIG_FSL_PCIE_DISABLE_ASPM 220 #define CONFIG_SYS_FSL_SEC_COMPAT 2 221 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 222 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 223 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 224 225 #elif defined(CONFIG_P1021) 226 #define CONFIG_MAX_CPUS 2 227 #define CONFIG_SYS_FSL_NUM_LAWS 12 228 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 229 #define CONFIG_TSECV2 230 #define CONFIG_FSL_PCIE_DISABLE_ASPM 231 #define CONFIG_SYS_FSL_SEC_COMPAT 2 232 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 233 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 234 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 235 #define QE_MURAM_SIZE 0x6000UL 236 #define MAX_QE_RISC 1 237 #define QE_NUM_OF_SNUM 28 238 239 #elif defined(CONFIG_P1022) 240 #define CONFIG_MAX_CPUS 2 241 #define CONFIG_SYS_FSL_NUM_LAWS 12 242 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 243 #define CONFIG_TSECV2 244 #define CONFIG_SYS_FSL_SEC_COMPAT 2 245 #define CONFIG_FSL_SATA_V2 246 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 247 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 248 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 249 #define CONFIG_FSL_SATA_ERRATUM_A001 250 251 #elif defined(CONFIG_P1023) 252 #define CONFIG_MAX_CPUS 2 253 #define CONFIG_SYS_FSL_NUM_LAWS 12 254 #define CONFIG_SYS_FSL_SEC_COMPAT 4 255 #define CONFIG_SYS_NUM_FMAN 1 256 #define CONFIG_SYS_NUM_FM1_DTSEC 2 257 #define CONFIG_NUM_DDR_CONTROLLERS 1 258 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 259 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 260 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 261 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 262 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 263 264 /* P1024 is lower end variant of P1020 */ 265 #elif defined(CONFIG_P1024) 266 #define CONFIG_MAX_CPUS 2 267 #define CONFIG_SYS_FSL_NUM_LAWS 12 268 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 269 #define CONFIG_TSECV2 270 #define CONFIG_FSL_PCIE_DISABLE_ASPM 271 #define CONFIG_SYS_FSL_SEC_COMPAT 2 272 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 273 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 274 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 275 276 /* P1025 is lower end variant of P1021 */ 277 #elif defined(CONFIG_P1025) 278 #define CONFIG_MAX_CPUS 2 279 #define CONFIG_SYS_FSL_NUM_LAWS 12 280 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 281 #define CONFIG_TSECV2 282 #define CONFIG_FSL_PCIE_DISABLE_ASPM 283 #define CONFIG_SYS_FSL_SEC_COMPAT 2 284 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 285 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 286 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 287 #define QE_MURAM_SIZE 0x6000UL 288 #define MAX_QE_RISC 1 289 #define QE_NUM_OF_SNUM 28 290 291 /* P2010 is single core version of P2020 */ 292 #elif defined(CONFIG_P2010) 293 #define CONFIG_MAX_CPUS 1 294 #define CONFIG_SYS_FSL_NUM_LAWS 12 295 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 296 #define CONFIG_SYS_FSL_SEC_COMPAT 2 297 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 298 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 299 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 300 301 #elif defined(CONFIG_P2020) 302 #define CONFIG_MAX_CPUS 2 303 #define CONFIG_SYS_FSL_NUM_LAWS 12 304 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 305 #define CONFIG_SYS_FSL_SEC_COMPAT 2 306 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 307 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 308 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 309 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 310 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 311 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 312 #define CONFIG_SYS_FSL_RMU 313 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 314 315 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 316 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 317 #define CONFIG_MAX_CPUS 4 318 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 319 #define CONFIG_SYS_FSL_NUM_LAWS 32 320 #define CONFIG_SYS_FSL_SEC_COMPAT 4 321 #define CONFIG_FSL_SATA_V2 322 #define CONFIG_SYS_NUM_FMAN 1 323 #define CONFIG_SYS_NUM_FM1_DTSEC 5 324 #define CONFIG_SYS_NUM_FM1_10GEC 1 325 #define CONFIG_NUM_DDR_CONTROLLERS 1 326 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 327 #define CONFIG_SYS_FSL_TBCLK_DIV 32 328 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 329 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 330 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 331 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 332 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 333 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 334 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 335 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 336 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 337 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 338 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 339 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 340 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 341 #define CONFIG_SYS_FSL_ERRATUM_A004510 342 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 343 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 344 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 345 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 346 347 #elif defined(CONFIG_PPC_P3041) 348 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 349 #define CONFIG_MAX_CPUS 4 350 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 351 #define CONFIG_SYS_FSL_NUM_LAWS 32 352 #define CONFIG_SYS_FSL_SEC_COMPAT 4 353 #define CONFIG_FSL_SATA_V2 354 #define CONFIG_SYS_NUM_FMAN 1 355 #define CONFIG_SYS_NUM_FM1_DTSEC 5 356 #define CONFIG_SYS_NUM_FM1_10GEC 1 357 #define CONFIG_NUM_DDR_CONTROLLERS 1 358 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 359 #define CONFIG_SYS_FSL_TBCLK_DIV 32 360 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 361 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 362 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 363 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 364 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 365 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 366 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 367 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 368 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 369 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 370 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 371 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 372 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 373 #define CONFIG_SYS_FSL_ERRATUM_A004510 374 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 375 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 376 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 377 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 378 379 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 380 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 381 #define CONFIG_MAX_CPUS 8 382 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 383 #define CONFIG_SYS_FSL_NUM_LAWS 32 384 #define CONFIG_SYS_FSL_SEC_COMPAT 4 385 #define CONFIG_SYS_NUM_FMAN 2 386 #define CONFIG_SYS_NUM_FM1_DTSEC 4 387 #define CONFIG_SYS_NUM_FM2_DTSEC 4 388 #define CONFIG_SYS_NUM_FM1_10GEC 1 389 #define CONFIG_SYS_NUM_FM2_10GEC 1 390 #define CONFIG_NUM_DDR_CONTROLLERS 2 391 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 392 #define CONFIG_SYS_FSL_TBCLK_DIV 16 393 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 394 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 395 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 396 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 397 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 398 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 399 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 400 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 401 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 402 #define CONFIG_SYS_P4080_ERRATUM_CPU22 403 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 404 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 405 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 406 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 407 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 408 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 409 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 410 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 411 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 412 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 413 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 414 #define CONFIG_SYS_FSL_RMU 415 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 416 #define CONFIG_SYS_FSL_ERRATUM_A004510 417 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 418 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 419 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 420 421 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 422 #define CONFIG_SYS_PPC64 /* 64-bit core */ 423 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 424 #define CONFIG_MAX_CPUS 2 425 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 426 #define CONFIG_SYS_FSL_NUM_LAWS 32 427 #define CONFIG_SYS_FSL_SEC_COMPAT 4 428 #define CONFIG_FSL_SATA_V2 429 #define CONFIG_SYS_NUM_FMAN 1 430 #define CONFIG_SYS_NUM_FM1_DTSEC 5 431 #define CONFIG_SYS_NUM_FM1_10GEC 1 432 #define CONFIG_NUM_DDR_CONTROLLERS 2 433 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 434 #define CONFIG_SYS_FSL_TBCLK_DIV 32 435 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 436 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 437 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 438 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 439 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 440 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 441 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 442 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 443 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 444 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 445 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 446 #define CONFIG_SYS_FSL_ERRATUM_A004510 447 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 448 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 449 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 450 451 #elif defined(CONFIG_PPC_P5040) 452 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 453 #define CONFIG_MAX_CPUS 4 454 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 455 #define CONFIG_SYS_FSL_NUM_LAWS 32 456 #define CONFIG_SYS_FSL_SEC_COMPAT 4 457 #define CONFIG_SYS_NUM_FMAN 2 458 #define CONFIG_SYS_NUM_FM1_DTSEC 5 459 #define CONFIG_SYS_NUM_FM1_10GEC 1 460 #define CONFIG_SYS_NUM_FM2_DTSEC 5 461 #define CONFIG_SYS_NUM_FM2_10GEC 1 462 #define CONFIG_NUM_DDR_CONTROLLERS 2 463 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 464 #define CONFIG_SYS_FSL_TBCLK_DIV 16 465 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 466 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 467 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 468 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 469 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 470 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 471 #define CONFIG_SYS_FSL_ERRATUM_USB138 472 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 473 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 474 #define CONFIG_SYS_FSL_ERRATUM_A004699 475 #define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC 476 #define CONFIG_SYS_FSL_ERRATUM_A004510 477 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 478 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 479 480 #elif defined(CONFIG_BSC9131) 481 #define CONFIG_MAX_CPUS 1 482 #define CONFIG_FSL_SDHC_V2_3 483 #define CONFIG_SYS_FSL_NUM_LAWS 12 484 #define CONFIG_TSECV2 485 #define CONFIG_SYS_FSL_SEC_COMPAT 4 486 #define CONFIG_NUM_DDR_CONTROLLERS 1 487 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 488 #define CONFIG_NAND_FSL_IFC 489 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 490 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 491 492 #elif defined(CONFIG_PPC_T4240) 493 #define CONFIG_SYS_PPC64 /* 64-bit core */ 494 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 495 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 496 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 497 #define CONFIG_MAX_CPUS 12 498 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 499 #define CONFIG_SYS_FSL_NUM_LAWS 32 500 #define CONFIG_SYS_FSL_SRDS_3 501 #define CONFIG_SYS_FSL_SRDS_4 502 #define CONFIG_SYS_FSL_SEC_COMPAT 4 503 #define CONFIG_SYS_NUM_FMAN 2 504 #define CONFIG_SYS_NUM_FM1_DTSEC 8 505 #define CONFIG_SYS_NUM_FM1_10GEC 2 506 #define CONFIG_SYS_NUM_FM2_DTSEC 8 507 #define CONFIG_SYS_NUM_FM2_10GEC 2 508 #define CONFIG_NUM_DDR_CONTROLLERS 3 509 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 510 #define CONFIG_SYS_FMAN_V3 511 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 512 #define CONFIG_SYS_FSL_TBCLK_DIV 16 513 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 514 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 515 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 516 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 517 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 518 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 519 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 520 #define CONFIG_SYS_FSL_ERRATUM_A004468 521 #define CONFIG_SYS_FSL_ERRATUM_A_004934 522 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 523 524 #elif defined(CONFIG_PPC_B4860) 525 #define CONFIG_SYS_PPC64 /* 64-bit core */ 526 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 527 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 528 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 529 #define CONFIG_MAX_CPUS 4 530 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 531 #define CONFIG_SYS_FSL_NUM_LAWS 32 532 #define CONFIG_SYS_FSL_SEC_COMPAT 4 533 #define CONFIG_SYS_NUM_FMAN 1 534 #define CONFIG_SYS_NUM_FM1_DTSEC 6 535 #define CONFIG_SYS_NUM_FM1_10GEC 2 536 #define CONFIG_NUM_DDR_CONTROLLERS 1 537 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 538 #define CONFIG_SYS_FMAN_V3 539 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 540 #define CONFIG_SYS_FSL_TBCLK_DIV 16 541 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 542 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 543 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 544 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 545 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 546 #define CONFIG_SYS_FSL_ERRATUM_A_004934 547 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 548 549 #else 550 #error Processor type not defined for this platform 551 #endif 552 553 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 554 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 555 #endif 556 557 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 558