1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #define FSL_DDR_VER_4_7 47 23 24 /* Number of TLB CAM entries we have on FSL Book-E chips */ 25 #if defined(CONFIG_E500MC) 26 #define CONFIG_SYS_NUM_TLBCAMS 64 27 #elif defined(CONFIG_E500) 28 #define CONFIG_SYS_NUM_TLBCAMS 16 29 #endif 30 31 #if defined(CONFIG_MPC8536) 32 #define CONFIG_MAX_CPUS 1 33 #define CONFIG_SYS_FSL_NUM_LAWS 12 34 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 35 #define CONFIG_SYS_FSL_SEC_COMPAT 2 36 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 37 #define CONFIG_SYS_FSL_ERRATUM_A005125 38 39 #elif defined(CONFIG_MPC8540) 40 #define CONFIG_MAX_CPUS 1 41 #define CONFIG_SYS_FSL_NUM_LAWS 8 42 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 43 44 #elif defined(CONFIG_MPC8541) 45 #define CONFIG_MAX_CPUS 1 46 #define CONFIG_SYS_FSL_NUM_LAWS 8 47 #define CONFIG_SYS_FSL_SEC_COMPAT 2 48 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 49 50 #elif defined(CONFIG_MPC8544) 51 #define CONFIG_MAX_CPUS 1 52 #define CONFIG_SYS_FSL_NUM_LAWS 10 53 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 54 #define CONFIG_SYS_FSL_SEC_COMPAT 2 55 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 56 #define CONFIG_SYS_FSL_ERRATUM_A005125 57 58 #elif defined(CONFIG_MPC8548) 59 #define CONFIG_MAX_CPUS 1 60 #define CONFIG_SYS_FSL_NUM_LAWS 10 61 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 62 #define CONFIG_SYS_FSL_SEC_COMPAT 2 63 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 64 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 65 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 66 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 67 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 68 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 69 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 70 #define CONFIG_SYS_FSL_RMU 71 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 72 #define CONFIG_SYS_FSL_ERRATUM_A005125 73 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 74 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 75 76 #elif defined(CONFIG_MPC8555) 77 #define CONFIG_MAX_CPUS 1 78 #define CONFIG_SYS_FSL_NUM_LAWS 8 79 #define CONFIG_SYS_FSL_SEC_COMPAT 2 80 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 81 82 #elif defined(CONFIG_MPC8560) 83 #define CONFIG_MAX_CPUS 1 84 #define CONFIG_SYS_FSL_NUM_LAWS 8 85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 86 87 #elif defined(CONFIG_MPC8568) 88 #define CONFIG_MAX_CPUS 1 89 #define CONFIG_SYS_FSL_NUM_LAWS 10 90 #define CONFIG_SYS_FSL_SEC_COMPAT 2 91 #define QE_MURAM_SIZE 0x10000UL 92 #define MAX_QE_RISC 2 93 #define QE_NUM_OF_SNUM 28 94 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 95 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 96 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 97 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 98 #define CONFIG_SYS_FSL_RMU 99 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 100 101 #elif defined(CONFIG_MPC8569) 102 #define CONFIG_MAX_CPUS 1 103 #define CONFIG_SYS_FSL_NUM_LAWS 10 104 #define CONFIG_SYS_FSL_SEC_COMPAT 2 105 #define QE_MURAM_SIZE 0x20000UL 106 #define MAX_QE_RISC 4 107 #define QE_NUM_OF_SNUM 46 108 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 109 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 110 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 111 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 112 #define CONFIG_SYS_FSL_RMU 113 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 114 #define CONFIG_SYS_FSL_ERRATUM_A005125 115 116 #elif defined(CONFIG_MPC8572) 117 #define CONFIG_MAX_CPUS 2 118 #define CONFIG_SYS_FSL_NUM_LAWS 12 119 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 120 #define CONFIG_SYS_FSL_SEC_COMPAT 2 121 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 122 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 123 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 124 #define CONFIG_SYS_FSL_ERRATUM_A005125 125 126 #elif defined(CONFIG_P1010) 127 #define CONFIG_MAX_CPUS 1 128 #define CONFIG_FSL_SDHC_V2_3 129 #define CONFIG_SYS_FSL_NUM_LAWS 12 130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 131 #define CONFIG_TSECV2 132 #define CONFIG_SYS_FSL_SEC_COMPAT 4 133 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 134 #define CONFIG_NUM_DDR_CONTROLLERS 1 135 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 136 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 137 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 138 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 139 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 140 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 141 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 142 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 143 #define CONFIG_SYS_FSL_ERRATUM_A005125 144 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 145 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 146 147 /* P1011 is single core version of P1020 */ 148 #elif defined(CONFIG_P1011) 149 #define CONFIG_MAX_CPUS 1 150 #define CONFIG_SYS_FSL_NUM_LAWS 12 151 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 152 #define CONFIG_TSECV2 153 #define CONFIG_FSL_PCIE_DISABLE_ASPM 154 #define CONFIG_SYS_FSL_SEC_COMPAT 2 155 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 156 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 157 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 158 #define CONFIG_SYS_FSL_ERRATUM_A005125 159 160 /* P1012 is single core version of P1021 */ 161 #elif defined(CONFIG_P1012) 162 #define CONFIG_MAX_CPUS 1 163 #define CONFIG_SYS_FSL_NUM_LAWS 12 164 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 165 #define CONFIG_TSECV2 166 #define CONFIG_FSL_PCIE_DISABLE_ASPM 167 #define CONFIG_SYS_FSL_SEC_COMPAT 2 168 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 169 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 170 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 171 #define QE_MURAM_SIZE 0x6000UL 172 #define MAX_QE_RISC 1 173 #define QE_NUM_OF_SNUM 28 174 #define CONFIG_SYS_FSL_ERRATUM_A005125 175 176 /* P1013 is single core version of P1022 */ 177 #elif defined(CONFIG_P1013) 178 #define CONFIG_MAX_CPUS 1 179 #define CONFIG_SYS_FSL_NUM_LAWS 12 180 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 181 #define CONFIG_TSECV2 182 #define CONFIG_SYS_FSL_SEC_COMPAT 2 183 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 184 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 185 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 186 #define CONFIG_FSL_SATA_ERRATUM_A001 187 #define CONFIG_SYS_FSL_ERRATUM_A005125 188 189 #elif defined(CONFIG_P1014) 190 #define CONFIG_MAX_CPUS 1 191 #define CONFIG_FSL_SDHC_V2_3 192 #define CONFIG_SYS_FSL_NUM_LAWS 12 193 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 194 #define CONFIG_TSECV2 195 #define CONFIG_SYS_FSL_SEC_COMPAT 4 196 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 197 #define CONFIG_NUM_DDR_CONTROLLERS 1 198 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 199 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 200 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 201 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 202 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 203 204 /* P1017 is single core version of P1023 */ 205 #elif defined(CONFIG_P1017) 206 #define CONFIG_MAX_CPUS 1 207 #define CONFIG_SYS_FSL_NUM_LAWS 12 208 #define CONFIG_SYS_FSL_SEC_COMPAT 4 209 #define CONFIG_SYS_NUM_FMAN 1 210 #define CONFIG_SYS_NUM_FM1_DTSEC 2 211 #define CONFIG_NUM_DDR_CONTROLLERS 1 212 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 213 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 214 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 215 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 216 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 217 #define CONFIG_SYS_FSL_ERRATUM_A005125 218 219 #elif defined(CONFIG_P1020) 220 #define CONFIG_MAX_CPUS 2 221 #define CONFIG_SYS_FSL_NUM_LAWS 12 222 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 223 #define CONFIG_TSECV2 224 #define CONFIG_FSL_PCIE_DISABLE_ASPM 225 #define CONFIG_SYS_FSL_SEC_COMPAT 2 226 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 227 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 228 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 229 #define CONFIG_SYS_FSL_ERRATUM_A005125 230 231 #elif defined(CONFIG_P1021) 232 #define CONFIG_MAX_CPUS 2 233 #define CONFIG_SYS_FSL_NUM_LAWS 12 234 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 235 #define CONFIG_TSECV2 236 #define CONFIG_FSL_PCIE_DISABLE_ASPM 237 #define CONFIG_SYS_FSL_SEC_COMPAT 2 238 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 239 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 240 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 241 #define QE_MURAM_SIZE 0x6000UL 242 #define MAX_QE_RISC 1 243 #define QE_NUM_OF_SNUM 28 244 #define CONFIG_SYS_FSL_ERRATUM_A005125 245 246 #elif defined(CONFIG_P1022) 247 #define CONFIG_MAX_CPUS 2 248 #define CONFIG_SYS_FSL_NUM_LAWS 12 249 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 250 #define CONFIG_TSECV2 251 #define CONFIG_SYS_FSL_SEC_COMPAT 2 252 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 253 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 254 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 255 #define CONFIG_FSL_SATA_ERRATUM_A001 256 #define CONFIG_SYS_FSL_ERRATUM_A005125 257 258 #elif defined(CONFIG_P1023) 259 #define CONFIG_MAX_CPUS 2 260 #define CONFIG_SYS_FSL_NUM_LAWS 12 261 #define CONFIG_SYS_FSL_SEC_COMPAT 4 262 #define CONFIG_SYS_NUM_FMAN 1 263 #define CONFIG_SYS_NUM_FM1_DTSEC 2 264 #define CONFIG_NUM_DDR_CONTROLLERS 1 265 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 266 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 267 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 268 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 269 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 270 #define CONFIG_SYS_FSL_ERRATUM_A005125 271 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 272 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 273 274 /* P1024 is lower end variant of P1020 */ 275 #elif defined(CONFIG_P1024) 276 #define CONFIG_MAX_CPUS 2 277 #define CONFIG_SYS_FSL_NUM_LAWS 12 278 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 279 #define CONFIG_TSECV2 280 #define CONFIG_FSL_PCIE_DISABLE_ASPM 281 #define CONFIG_SYS_FSL_SEC_COMPAT 2 282 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 283 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 284 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 285 #define CONFIG_SYS_FSL_ERRATUM_A005125 286 287 /* P1025 is lower end variant of P1021 */ 288 #elif defined(CONFIG_P1025) 289 #define CONFIG_MAX_CPUS 2 290 #define CONFIG_SYS_FSL_NUM_LAWS 12 291 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 292 #define CONFIG_TSECV2 293 #define CONFIG_FSL_PCIE_DISABLE_ASPM 294 #define CONFIG_SYS_FSL_SEC_COMPAT 2 295 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 296 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 297 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 298 #define QE_MURAM_SIZE 0x6000UL 299 #define MAX_QE_RISC 1 300 #define QE_NUM_OF_SNUM 28 301 #define CONFIG_SYS_FSL_ERRATUM_A005125 302 303 /* P2010 is single core version of P2020 */ 304 #elif defined(CONFIG_P2010) 305 #define CONFIG_MAX_CPUS 1 306 #define CONFIG_SYS_FSL_NUM_LAWS 12 307 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 308 #define CONFIG_SYS_FSL_SEC_COMPAT 2 309 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 310 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 311 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 312 #define CONFIG_SYS_FSL_ERRATUM_A005125 313 314 #elif defined(CONFIG_P2020) 315 #define CONFIG_MAX_CPUS 2 316 #define CONFIG_SYS_FSL_NUM_LAWS 12 317 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 318 #define CONFIG_SYS_FSL_SEC_COMPAT 2 319 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 320 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 321 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 322 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 323 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 324 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 325 #define CONFIG_SYS_FSL_RMU 326 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 327 #define CONFIG_SYS_FSL_ERRATUM_A005125 328 329 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 330 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 331 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 332 #define CONFIG_MAX_CPUS 4 333 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 334 #define CONFIG_SYS_FSL_NUM_LAWS 32 335 #define CONFIG_SYS_FSL_SEC_COMPAT 4 336 #define CONFIG_SYS_NUM_FMAN 1 337 #define CONFIG_SYS_NUM_FM1_DTSEC 5 338 #define CONFIG_SYS_NUM_FM1_10GEC 1 339 #define CONFIG_NUM_DDR_CONTROLLERS 1 340 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 341 #define CONFIG_SYS_FSL_TBCLK_DIV 32 342 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 343 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 344 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 345 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 346 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 347 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 348 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 349 #define CONFIG_SYS_FSL_ERRATUM_USB14 350 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 351 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 352 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 353 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 354 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 355 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 356 #define CONFIG_SYS_FSL_ERRATUM_A004510 357 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 358 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 359 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 360 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 361 #define CONFIG_SYS_FSL_ERRATUM_A004849 362 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 363 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 364 365 #elif defined(CONFIG_PPC_P3041) 366 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 367 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 368 #define CONFIG_MAX_CPUS 4 369 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 370 #define CONFIG_SYS_FSL_NUM_LAWS 32 371 #define CONFIG_SYS_FSL_SEC_COMPAT 4 372 #define CONFIG_SYS_NUM_FMAN 1 373 #define CONFIG_SYS_NUM_FM1_DTSEC 5 374 #define CONFIG_SYS_NUM_FM1_10GEC 1 375 #define CONFIG_NUM_DDR_CONTROLLERS 1 376 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 377 #define CONFIG_SYS_FSL_TBCLK_DIV 32 378 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 379 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 380 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 381 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 382 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 383 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 384 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 385 #define CONFIG_SYS_FSL_ERRATUM_USB14 386 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 387 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 388 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 389 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 390 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 391 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 392 #define CONFIG_SYS_FSL_ERRATUM_A004510 393 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 394 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 395 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 396 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 397 #define CONFIG_SYS_FSL_ERRATUM_A004849 398 #define CONFIG_SYS_FSL_ERRATUM_A005812 399 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 400 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 401 402 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 403 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 404 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 405 #define CONFIG_MAX_CPUS 8 406 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 407 #define CONFIG_SYS_FSL_NUM_LAWS 32 408 #define CONFIG_SYS_FSL_SEC_COMPAT 4 409 #define CONFIG_SYS_NUM_FMAN 2 410 #define CONFIG_SYS_NUM_FM1_DTSEC 4 411 #define CONFIG_SYS_NUM_FM2_DTSEC 4 412 #define CONFIG_SYS_NUM_FM1_10GEC 1 413 #define CONFIG_SYS_NUM_FM2_10GEC 1 414 #define CONFIG_NUM_DDR_CONTROLLERS 2 415 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 416 #define CONFIG_SYS_FSL_TBCLK_DIV 16 417 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 418 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 419 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 420 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 421 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 422 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 423 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 424 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 425 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 426 #define CONFIG_SYS_P4080_ERRATUM_CPU22 427 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 428 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 429 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 430 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 431 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 432 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 433 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 434 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 435 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 436 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 437 #define CONFIG_SYS_FSL_RMU 438 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 439 #define CONFIG_SYS_FSL_ERRATUM_A004510 440 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 441 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 442 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 443 #define CONFIG_SYS_FSL_ERRATUM_A004849 444 #define CONFIG_SYS_FSL_ERRATUM_A004580 445 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 446 #define CONFIG_SYS_FSL_ERRATUM_A005812 447 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 448 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 449 450 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 451 #define CONFIG_SYS_PPC64 /* 64-bit core */ 452 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 453 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 454 #define CONFIG_MAX_CPUS 2 455 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 456 #define CONFIG_SYS_FSL_NUM_LAWS 32 457 #define CONFIG_SYS_FSL_SEC_COMPAT 4 458 #define CONFIG_SYS_NUM_FMAN 1 459 #define CONFIG_SYS_NUM_FM1_DTSEC 5 460 #define CONFIG_SYS_NUM_FM1_10GEC 1 461 #define CONFIG_NUM_DDR_CONTROLLERS 2 462 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 463 #define CONFIG_SYS_FSL_TBCLK_DIV 32 464 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 465 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 466 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 467 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 468 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 469 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 470 #define CONFIG_SYS_FSL_ERRATUM_USB14 471 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 472 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 473 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 474 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 475 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 476 #define CONFIG_SYS_FSL_ERRATUM_A004510 477 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 478 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 479 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 480 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 481 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 482 483 #elif defined(CONFIG_PPC_P5040) 484 #define CONFIG_SYS_PPC64 485 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 486 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 487 #define CONFIG_MAX_CPUS 4 488 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 489 #define CONFIG_SYS_FSL_NUM_LAWS 32 490 #define CONFIG_SYS_FSL_SEC_COMPAT 4 491 #define CONFIG_SYS_NUM_FMAN 2 492 #define CONFIG_SYS_NUM_FM1_DTSEC 5 493 #define CONFIG_SYS_NUM_FM1_10GEC 1 494 #define CONFIG_SYS_NUM_FM2_DTSEC 5 495 #define CONFIG_SYS_NUM_FM2_10GEC 1 496 #define CONFIG_NUM_DDR_CONTROLLERS 2 497 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 498 #define CONFIG_SYS_FSL_TBCLK_DIV 16 499 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 500 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 501 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 502 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 503 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 504 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 505 #define CONFIG_SYS_FSL_ERRATUM_USB14 506 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 507 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 508 #define CONFIG_SYS_FSL_ERRATUM_A004699 509 #define CONFIG_SYS_FSL_ERRATUM_A004510 510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 511 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 512 #define CONFIG_SYS_FSL_ERRATUM_A005812 513 514 #elif defined(CONFIG_BSC9131) 515 #define CONFIG_MAX_CPUS 1 516 #define CONFIG_FSL_SDHC_V2_3 517 #define CONFIG_SYS_FSL_NUM_LAWS 12 518 #define CONFIG_TSECV2 519 #define CONFIG_SYS_FSL_SEC_COMPAT 4 520 #define CONFIG_NUM_DDR_CONTROLLERS 1 521 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 522 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 523 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 524 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 525 #define CONFIG_NAND_FSL_IFC 526 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 527 #define CONFIG_SYS_FSL_ERRATUM_A005125 528 529 #elif defined(CONFIG_BSC9132) 530 #define CONFIG_MAX_CPUS 2 531 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 532 #define CONFIG_FSL_SDHC_V2_3 533 #define CONFIG_SYS_FSL_NUM_LAWS 12 534 #define CONFIG_TSECV2 535 #define CONFIG_SYS_FSL_SEC_COMPAT 4 536 #define CONFIG_NUM_DDR_CONTROLLERS 2 537 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 538 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 539 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 540 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 541 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 542 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 543 #define CONFIG_NAND_FSL_IFC 544 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 545 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 546 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 547 #define CONFIG_SYS_FSL_ERRATUM_A005125 548 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 549 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 550 551 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 552 #define CONFIG_E6500 553 #define CONFIG_SYS_PPC64 /* 64-bit core */ 554 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 555 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 556 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 557 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 558 #ifdef CONFIG_PPC_T4240 559 #define CONFIG_MAX_CPUS 12 560 #define CONFIG_SYS_NUM_FM1_DTSEC 8 561 #define CONFIG_SYS_NUM_FM1_10GEC 2 562 #define CONFIG_SYS_NUM_FM2_DTSEC 8 563 #define CONFIG_SYS_NUM_FM2_10GEC 2 564 #define CONFIG_NUM_DDR_CONTROLLERS 3 565 #else 566 #define CONFIG_MAX_CPUS 8 567 #define CONFIG_SYS_NUM_FM1_DTSEC 7 568 #define CONFIG_SYS_NUM_FM1_10GEC 1 569 #define CONFIG_SYS_NUM_FM2_DTSEC 7 570 #define CONFIG_SYS_NUM_FM2_10GEC 1 571 #define CONFIG_NUM_DDR_CONTROLLERS 2 572 #endif 573 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 574 #define CONFIG_SYS_FSL_NUM_LAWS 32 575 #define CONFIG_SYS_FSL_SRDS_1 576 #define CONFIG_SYS_FSL_SRDS_2 577 #define CONFIG_SYS_FSL_SRDS_3 578 #define CONFIG_SYS_FSL_SRDS_4 579 #define CONFIG_SYS_FSL_SEC_COMPAT 4 580 #define CONFIG_SYS_NUM_FMAN 2 581 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 582 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 583 #define CONFIG_SYS_FMAN_V3 584 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 585 #define CONFIG_SYS_FSL_TBCLK_DIV 16 586 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 587 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 588 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 589 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 590 #define CONFIG_SYS_FSL_SRIO_LIODN 591 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 592 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 593 #define CONFIG_SYS_FSL_ERRATUM_A004468 594 #define CONFIG_SYS_FSL_ERRATUM_A_004934 595 #define CONFIG_SYS_FSL_ERRATUM_A005871 596 #define CONFIG_SYS_FSL_ERRATUM_A006593 597 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 598 #define CONFIG_SYS_FSL_PCI_VER_3_X 599 600 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 601 #define CONFIG_E6500 602 #define CONFIG_SYS_PPC64 /* 64-bit core */ 603 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 604 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 605 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 606 #define CONFIG_SYS_FSL_NUM_LAWS 32 607 #define CONFIG_SYS_FSL_SRDS_1 608 #define CONFIG_SYS_FSL_SRDS_2 609 #define CONFIG_SYS_FSL_SEC_COMPAT 4 610 #define CONFIG_SYS_NUM_FMAN 1 611 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 612 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 613 #define CONFIG_SYS_FMAN_V3 614 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 615 #define CONFIG_SYS_FSL_TBCLK_DIV 16 616 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 617 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 618 #define CONFIG_SYS_FSL_ERRATUM_A_004934 619 #define CONFIG_SYS_FSL_ERRATUM_A005871 620 #define CONFIG_SYS_FSL_ERRATUM_A006593 621 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 622 623 #ifdef CONFIG_PPC_B4860 624 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 625 #define CONFIG_MAX_CPUS 4 626 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 627 #define CONFIG_SYS_NUM_FM1_DTSEC 6 628 #define CONFIG_SYS_NUM_FM1_10GEC 2 629 #define CONFIG_NUM_DDR_CONTROLLERS 2 630 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 631 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 632 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 633 #define CONFIG_SYS_FSL_SRIO_LIODN 634 #else 635 #define CONFIG_MAX_CPUS 2 636 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 637 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 638 #define CONFIG_SYS_NUM_FM1_DTSEC 4 639 #define CONFIG_SYS_NUM_FM1_10GEC 0 640 #define CONFIG_NUM_DDR_CONTROLLERS 1 641 #endif 642 643 #elif defined(CONFIG_PPC_T1040) 644 #define CONFIG_E5500 645 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 646 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 647 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 648 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 649 #define CONFIG_MAX_CPUS 4 650 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 651 #define CONFIG_SYS_FSL_NUM_LAWS 16 652 #define CONFIG_SYS_FSL_SEC_COMPAT 4 653 #define CONFIG_SYS_NUM_FMAN 1 654 #define CONFIG_SYS_NUM_FM1_DTSEC 5 655 #define CONFIG_NUM_DDR_CONTROLLERS 1 656 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 657 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 658 #define CONFIG_SYS_FMAN_V3 659 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 660 #define CONFIG_SYS_FSL_TBCLK_DIV 32 661 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 662 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 663 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 664 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 665 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 666 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 667 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 668 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 669 670 #elif defined(CONFIG_PPC_C29X) 671 #define CONFIG_MAX_CPUS 1 672 #define CONFIG_FSL_SDHC_V2_3 673 #define CONFIG_SYS_FSL_NUM_LAWS 12 674 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 675 #define CONFIG_TSECV2_1 676 #define CONFIG_SYS_FSL_SEC_COMPAT 6 677 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 678 #define CONFIG_NUM_DDR_CONTROLLERS 1 679 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 680 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 681 #define CONFIG_SYS_FSL_ERRATUM_A005125 682 683 #else 684 #error Processor type not defined for this platform 685 #endif 686 687 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 688 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 689 #endif 690 691 #ifdef CONFIG_E6500 692 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 693 #else 694 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 695 #endif 696 697 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 698