1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17  * MA 02111-1307 USA
18  *
19  */
20 
21 #ifndef _ASM_MPC85xx_CONFIG_H_
22 #define _ASM_MPC85xx_CONFIG_H_
23 
24 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25 
26 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28 #endif
29 
30 /*
31  * This macro should be removed when we no longer care about backwards
32  * compatibility with older operating systems.
33  */
34 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
35 
36 #define FSL_DDR_VER_4_7	47
37 
38 /* Number of TLB CAM entries we have on FSL Book-E chips */
39 #if defined(CONFIG_E500MC)
40 #define CONFIG_SYS_NUM_TLBCAMS		64
41 #elif defined(CONFIG_E500)
42 #define CONFIG_SYS_NUM_TLBCAMS		16
43 #endif
44 
45 #if defined(CONFIG_MPC8536)
46 #define CONFIG_MAX_CPUS			1
47 #define CONFIG_SYS_FSL_NUM_LAWS		12
48 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	1
49 #define CONFIG_SYS_FSL_SEC_COMPAT	2
50 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
51 
52 #elif defined(CONFIG_MPC8540)
53 #define CONFIG_MAX_CPUS			1
54 #define CONFIG_SYS_FSL_NUM_LAWS		8
55 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
56 
57 #elif defined(CONFIG_MPC8541)
58 #define CONFIG_MAX_CPUS			1
59 #define CONFIG_SYS_FSL_NUM_LAWS		8
60 #define CONFIG_SYS_FSL_SEC_COMPAT	2
61 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
62 
63 #elif defined(CONFIG_MPC8544)
64 #define CONFIG_MAX_CPUS			1
65 #define CONFIG_SYS_FSL_NUM_LAWS		10
66 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	0
67 #define CONFIG_SYS_FSL_SEC_COMPAT	2
68 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
69 
70 #elif defined(CONFIG_MPC8548)
71 #define CONFIG_MAX_CPUS			1
72 #define CONFIG_SYS_FSL_NUM_LAWS		10
73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	0
74 #define CONFIG_SYS_FSL_SEC_COMPAT	2
75 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
82 #define CONFIG_SYS_FSL_RMU
83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
84 
85 #elif defined(CONFIG_MPC8555)
86 #define CONFIG_MAX_CPUS			1
87 #define CONFIG_SYS_FSL_NUM_LAWS		8
88 #define CONFIG_SYS_FSL_SEC_COMPAT	2
89 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
90 
91 #elif defined(CONFIG_MPC8560)
92 #define CONFIG_MAX_CPUS			1
93 #define CONFIG_SYS_FSL_NUM_LAWS		8
94 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
95 
96 #elif defined(CONFIG_MPC8568)
97 #define CONFIG_MAX_CPUS			1
98 #define CONFIG_SYS_FSL_NUM_LAWS		10
99 #define CONFIG_SYS_FSL_SEC_COMPAT	2
100 #define QE_MURAM_SIZE			0x10000UL
101 #define MAX_QE_RISC			2
102 #define QE_NUM_OF_SNUM			28
103 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
104 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
105 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
106 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
107 #define CONFIG_SYS_FSL_RMU
108 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
109 
110 #elif defined(CONFIG_MPC8569)
111 #define CONFIG_MAX_CPUS			1
112 #define CONFIG_SYS_FSL_NUM_LAWS		10
113 #define CONFIG_SYS_FSL_SEC_COMPAT	2
114 #define QE_MURAM_SIZE			0x20000UL
115 #define MAX_QE_RISC			4
116 #define QE_NUM_OF_SNUM			46
117 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
118 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
119 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
120 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
121 #define CONFIG_SYS_FSL_RMU
122 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
123 
124 #elif defined(CONFIG_MPC8572)
125 #define CONFIG_MAX_CPUS			2
126 #define CONFIG_SYS_FSL_NUM_LAWS		12
127 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
128 #define CONFIG_SYS_FSL_SEC_COMPAT	2
129 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
130 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
131 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
132 
133 #elif defined(CONFIG_P1010)
134 #define CONFIG_MAX_CPUS			1
135 #define CONFIG_FSL_SDHC_V2_3
136 #define CONFIG_SYS_FSL_NUM_LAWS		12
137 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
138 #define CONFIG_TSECV2
139 #define CONFIG_SYS_FSL_SEC_COMPAT	4
140 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
141 #define CONFIG_NUM_DDR_CONTROLLERS	1
142 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
143 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
144 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
145 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
146 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
147 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
148 
149 /* P1011 is single core version of P1020 */
150 #elif defined(CONFIG_P1011)
151 #define CONFIG_MAX_CPUS			1
152 #define CONFIG_SYS_FSL_NUM_LAWS		12
153 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
154 #define CONFIG_TSECV2
155 #define CONFIG_FSL_PCIE_DISABLE_ASPM
156 #define CONFIG_SYS_FSL_SEC_COMPAT	2
157 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
158 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
159 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
160 
161 /* P1012 is single core version of P1021 */
162 #elif defined(CONFIG_P1012)
163 #define CONFIG_MAX_CPUS			1
164 #define CONFIG_SYS_FSL_NUM_LAWS		12
165 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
166 #define CONFIG_TSECV2
167 #define CONFIG_FSL_PCIE_DISABLE_ASPM
168 #define CONFIG_SYS_FSL_SEC_COMPAT	2
169 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
170 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
171 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
172 #define QE_MURAM_SIZE			0x6000UL
173 #define MAX_QE_RISC			1
174 #define QE_NUM_OF_SNUM			28
175 
176 /* P1013 is single core version of P1022 */
177 #elif defined(CONFIG_P1013)
178 #define CONFIG_MAX_CPUS			1
179 #define CONFIG_SYS_FSL_NUM_LAWS		12
180 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
181 #define CONFIG_TSECV2
182 #define CONFIG_SYS_FSL_SEC_COMPAT	2
183 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
184 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
185 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
186 #define CONFIG_FSL_SATA_ERRATUM_A001
187 
188 #elif defined(CONFIG_P1014)
189 #define CONFIG_MAX_CPUS			1
190 #define CONFIG_FSL_SDHC_V2_3
191 #define CONFIG_SYS_FSL_NUM_LAWS		12
192 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	3
193 #define CONFIG_TSECV2
194 #define CONFIG_SYS_FSL_SEC_COMPAT	4
195 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
196 #define CONFIG_NUM_DDR_CONTROLLERS	1
197 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
198 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
199 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
200 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
201 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
202 
203 /* P1017 is single core version of P1023 */
204 #elif defined(CONFIG_P1017)
205 #define CONFIG_MAX_CPUS			1
206 #define CONFIG_SYS_FSL_NUM_LAWS		12
207 #define CONFIG_SYS_FSL_SEC_COMPAT	4
208 #define CONFIG_SYS_NUM_FMAN		1
209 #define CONFIG_SYS_NUM_FM1_DTSEC	2
210 #define CONFIG_NUM_DDR_CONTROLLERS	1
211 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
212 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
213 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
214 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
215 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
216 
217 #elif defined(CONFIG_P1020)
218 #define CONFIG_MAX_CPUS			2
219 #define CONFIG_SYS_FSL_NUM_LAWS		12
220 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
221 #define CONFIG_TSECV2
222 #define CONFIG_FSL_PCIE_DISABLE_ASPM
223 #define CONFIG_SYS_FSL_SEC_COMPAT	2
224 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
225 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
226 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
227 
228 #elif defined(CONFIG_P1021)
229 #define CONFIG_MAX_CPUS			2
230 #define CONFIG_SYS_FSL_NUM_LAWS		12
231 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
232 #define CONFIG_TSECV2
233 #define CONFIG_FSL_PCIE_DISABLE_ASPM
234 #define CONFIG_SYS_FSL_SEC_COMPAT	2
235 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
236 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
237 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
238 #define QE_MURAM_SIZE			0x6000UL
239 #define MAX_QE_RISC			1
240 #define QE_NUM_OF_SNUM			28
241 
242 #elif defined(CONFIG_P1022)
243 #define CONFIG_MAX_CPUS			2
244 #define CONFIG_SYS_FSL_NUM_LAWS		12
245 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
246 #define CONFIG_TSECV2
247 #define CONFIG_SYS_FSL_SEC_COMPAT	2
248 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
249 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
250 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
251 #define CONFIG_FSL_SATA_ERRATUM_A001
252 
253 #elif defined(CONFIG_P1023)
254 #define CONFIG_MAX_CPUS			2
255 #define CONFIG_SYS_FSL_NUM_LAWS		12
256 #define CONFIG_SYS_FSL_SEC_COMPAT	4
257 #define CONFIG_SYS_NUM_FMAN		1
258 #define CONFIG_SYS_NUM_FM1_DTSEC	2
259 #define CONFIG_NUM_DDR_CONTROLLERS	1
260 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
261 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
262 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
263 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
264 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
265 
266 /* P1024 is lower end variant of P1020 */
267 #elif defined(CONFIG_P1024)
268 #define CONFIG_MAX_CPUS			2
269 #define CONFIG_SYS_FSL_NUM_LAWS		12
270 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
271 #define CONFIG_TSECV2
272 #define CONFIG_FSL_PCIE_DISABLE_ASPM
273 #define CONFIG_SYS_FSL_SEC_COMPAT	2
274 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
275 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
276 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
277 
278 /* P1025 is lower end variant of P1021 */
279 #elif defined(CONFIG_P1025)
280 #define CONFIG_MAX_CPUS			2
281 #define CONFIG_SYS_FSL_NUM_LAWS		12
282 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
283 #define CONFIG_TSECV2
284 #define CONFIG_FSL_PCIE_DISABLE_ASPM
285 #define CONFIG_SYS_FSL_SEC_COMPAT	2
286 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
287 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
288 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
289 #define QE_MURAM_SIZE			0x6000UL
290 #define MAX_QE_RISC			1
291 #define QE_NUM_OF_SNUM			28
292 
293 /* P2010 is single core version of P2020 */
294 #elif defined(CONFIG_P2010)
295 #define CONFIG_MAX_CPUS			1
296 #define CONFIG_SYS_FSL_NUM_LAWS		12
297 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
298 #define CONFIG_SYS_FSL_SEC_COMPAT	2
299 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
300 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
301 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
302 
303 #elif defined(CONFIG_P2020)
304 #define CONFIG_MAX_CPUS			2
305 #define CONFIG_SYS_FSL_NUM_LAWS		12
306 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
307 #define CONFIG_SYS_FSL_SEC_COMPAT	2
308 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
309 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
310 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
311 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
312 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
313 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
314 #define CONFIG_SYS_FSL_RMU
315 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
316 
317 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
318 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
319 #define CONFIG_MAX_CPUS			4
320 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
321 #define CONFIG_SYS_FSL_NUM_LAWS		32
322 #define CONFIG_SYS_FSL_SEC_COMPAT	4
323 #define CONFIG_SYS_NUM_FMAN		1
324 #define CONFIG_SYS_NUM_FM1_DTSEC	5
325 #define CONFIG_SYS_NUM_FM1_10GEC	1
326 #define CONFIG_NUM_DDR_CONTROLLERS	1
327 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
328 #define CONFIG_SYS_FSL_TBCLK_DIV	32
329 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
330 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
331 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
332 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
333 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
334 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
335 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
336 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
337 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
338 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
339 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
340 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
341 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
342 #define CONFIG_SYS_FSL_ERRATUM_A004510
343 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
344 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2	0x11
345 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
346 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
347 #define CONFIG_SYS_FSL_ERRATUM_A004849
348 
349 #elif defined(CONFIG_PPC_P3041)
350 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
351 #define CONFIG_MAX_CPUS			4
352 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
353 #define CONFIG_SYS_FSL_NUM_LAWS		32
354 #define CONFIG_SYS_FSL_SEC_COMPAT	4
355 #define CONFIG_SYS_NUM_FMAN		1
356 #define CONFIG_SYS_NUM_FM1_DTSEC	5
357 #define CONFIG_SYS_NUM_FM1_10GEC	1
358 #define CONFIG_NUM_DDR_CONTROLLERS	1
359 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
360 #define CONFIG_SYS_FSL_TBCLK_DIV	32
361 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
362 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
363 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
364 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
365 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
366 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
367 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
368 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
369 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
370 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
371 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
372 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
373 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
374 #define CONFIG_SYS_FSL_ERRATUM_A004510
375 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
376 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2	0x11
377 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
378 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
379 #define CONFIG_SYS_FSL_ERRATUM_A004849
380 
381 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
382 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
383 #define CONFIG_MAX_CPUS			8
384 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
385 #define CONFIG_SYS_FSL_NUM_LAWS		32
386 #define CONFIG_SYS_FSL_SEC_COMPAT	4
387 #define CONFIG_SYS_NUM_FMAN		2
388 #define CONFIG_SYS_NUM_FM1_DTSEC	4
389 #define CONFIG_SYS_NUM_FM2_DTSEC	4
390 #define CONFIG_SYS_NUM_FM1_10GEC	1
391 #define CONFIG_SYS_NUM_FM2_10GEC	1
392 #define CONFIG_NUM_DDR_CONTROLLERS	2
393 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
394 #define CONFIG_SYS_FSL_TBCLK_DIV	16
395 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
396 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
397 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
398 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
399 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
400 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
401 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
402 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
403 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
404 #define CONFIG_SYS_P4080_ERRATUM_CPU22
405 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
406 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
407 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
408 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
409 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
410 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
411 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
412 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
413 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
414 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
415 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
416 #define CONFIG_SYS_FSL_RMU
417 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
418 #define CONFIG_SYS_FSL_ERRATUM_A004510
419 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x20
420 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
421 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
422 #define CONFIG_SYS_FSL_ERRATUM_A004849
423 #define CONFIG_SYS_FSL_ERRATUM_A004580
424 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
425 
426 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
427 #define CONFIG_SYS_PPC64		/* 64-bit core */
428 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
429 #define CONFIG_MAX_CPUS			2
430 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
431 #define CONFIG_SYS_FSL_NUM_LAWS		32
432 #define CONFIG_SYS_FSL_SEC_COMPAT	4
433 #define CONFIG_SYS_NUM_FMAN		1
434 #define CONFIG_SYS_NUM_FM1_DTSEC	5
435 #define CONFIG_SYS_NUM_FM1_10GEC	1
436 #define CONFIG_NUM_DDR_CONTROLLERS	2
437 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
438 #define CONFIG_SYS_FSL_TBCLK_DIV	32
439 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
440 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
441 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
442 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
443 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
444 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
445 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
446 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
447 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
448 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
449 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
450 #define CONFIG_SYS_FSL_ERRATUM_A004510
451 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
452 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
453 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
454 
455 #elif defined(CONFIG_PPC_P5040)
456 #define CONFIG_SYS_PPC64
457 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
458 #define CONFIG_MAX_CPUS			4
459 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
460 #define CONFIG_SYS_FSL_NUM_LAWS		32
461 #define CONFIG_SYS_FSL_SEC_COMPAT	4
462 #define CONFIG_SYS_NUM_FMAN		2
463 #define CONFIG_SYS_NUM_FM1_DTSEC	5
464 #define CONFIG_SYS_NUM_FM1_10GEC	1
465 #define CONFIG_SYS_NUM_FM2_DTSEC	5
466 #define CONFIG_SYS_NUM_FM2_10GEC	1
467 #define CONFIG_NUM_DDR_CONTROLLERS	2
468 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
469 #define CONFIG_SYS_FSL_TBCLK_DIV	16
470 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
471 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
472 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
473 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
474 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
475 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
476 #define CONFIG_SYS_FSL_ERRATUM_USB138
477 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
478 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
479 #define CONFIG_SYS_FSL_ERRATUM_A004699
480 #define CONFIG_SYS_FSL_ERRATUM_A004510
481 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
482 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
483 
484 #elif defined(CONFIG_BSC9131)
485 #define CONFIG_MAX_CPUS			1
486 #define CONFIG_FSL_SDHC_V2_3
487 #define CONFIG_SYS_FSL_NUM_LAWS		12
488 #define CONFIG_TSECV2
489 #define CONFIG_SYS_FSL_SEC_COMPAT	4
490 #define CONFIG_NUM_DDR_CONTROLLERS	1
491 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
492 #define CONFIG_NAND_FSL_IFC
493 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
494 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
495 
496 #elif defined(CONFIG_PPC_T4240)
497 #define CONFIG_SYS_PPC64		/* 64-bit core */
498 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
499 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
500 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
501 #define CONFIG_MAX_CPUS			12
502 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
503 #define CONFIG_SYS_FSL_NUM_LAWS		32
504 #define CONFIG_SYS_FSL_SRDS_3
505 #define CONFIG_SYS_FSL_SRDS_4
506 #define CONFIG_SYS_FSL_SEC_COMPAT	4
507 #define CONFIG_SYS_NUM_FMAN		2
508 #define CONFIG_SYS_NUM_FM1_DTSEC	8
509 #define CONFIG_SYS_NUM_FM1_10GEC	2
510 #define CONFIG_SYS_NUM_FM2_DTSEC	8
511 #define CONFIG_SYS_NUM_FM2_10GEC	2
512 #define CONFIG_NUM_DDR_CONTROLLERS	3
513 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
514 #define CONFIG_SYS_FMAN_V3
515 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
516 #define CONFIG_SYS_FSL_TBCLK_DIV	16
517 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
518 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
519 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
520 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
521 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
522 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
523 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
524 #define CONFIG_SYS_FSL_ERRATUM_A004468
525 #define CONFIG_SYS_FSL_ERRATUM_A_004934
526 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
527 
528 #elif defined(CONFIG_PPC_B4860)
529 #define CONFIG_SYS_PPC64		/* 64-bit core */
530 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
531 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
532 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
533 #define CONFIG_MAX_CPUS			4
534 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
535 #define CONFIG_SYS_FSL_NUM_LAWS		32
536 #define CONFIG_SYS_FSL_SEC_COMPAT	4
537 #define CONFIG_SYS_NUM_FMAN		1
538 #define CONFIG_SYS_NUM_FM1_DTSEC	6
539 #define CONFIG_SYS_NUM_FM1_10GEC	2
540 #define CONFIG_NUM_DDR_CONTROLLERS	1
541 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
542 #define CONFIG_SYS_FMAN_V3
543 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
544 #define CONFIG_SYS_FSL_TBCLK_DIV	16
545 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
546 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
547 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
548 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
549 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
550 #define CONFIG_SYS_FSL_ERRATUM_A_004934
551 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
552 
553 #else
554 #error Processor type not defined for this platform
555 #endif
556 
557 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
558 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
559 #endif
560 
561 #endif /* _ASM_MPC85xx_CONFIG_H_ */
562