1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #include <fsl_ddrc_version.h> 23 #define CONFIG_SYS_FSL_DDR_BE 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 28 /* Number of TLB CAM entries we have on FSL Book-E chips */ 29 #if defined(CONFIG_E500MC) 30 #define CONFIG_SYS_NUM_TLBCAMS 64 31 #elif defined(CONFIG_E500) 32 #define CONFIG_SYS_NUM_TLBCAMS 16 33 #endif 34 35 #if defined(CONFIG_MPC8536) 36 #define CONFIG_MAX_CPUS 1 37 #define CONFIG_SYS_FSL_NUM_LAWS 12 38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 39 #define CONFIG_SYS_FSL_SEC_COMPAT 2 40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 41 #define CONFIG_SYS_FSL_ERRATUM_A004508 42 #define CONFIG_SYS_FSL_ERRATUM_A005125 43 44 #elif defined(CONFIG_MPC8540) 45 #define CONFIG_MAX_CPUS 1 46 #define CONFIG_SYS_FSL_NUM_LAWS 8 47 #define CONFIG_SYS_FSL_DDRC_GEN1 48 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 49 50 #elif defined(CONFIG_MPC8541) 51 #define CONFIG_MAX_CPUS 1 52 #define CONFIG_SYS_FSL_NUM_LAWS 8 53 #define CONFIG_SYS_FSL_DDRC_GEN1 54 #define CONFIG_SYS_FSL_SEC_COMPAT 2 55 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 56 57 #elif defined(CONFIG_MPC8544) 58 #define CONFIG_MAX_CPUS 1 59 #define CONFIG_SYS_FSL_NUM_LAWS 10 60 #define CONFIG_SYS_FSL_DDRC_GEN2 61 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 62 #define CONFIG_SYS_FSL_SEC_COMPAT 2 63 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 64 #define CONFIG_SYS_FSL_ERRATUM_A005125 65 66 #elif defined(CONFIG_MPC8548) 67 #define CONFIG_MAX_CPUS 1 68 #define CONFIG_SYS_FSL_NUM_LAWS 10 69 #define CONFIG_SYS_FSL_DDRC_GEN2 70 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 71 #define CONFIG_SYS_FSL_SEC_COMPAT 2 72 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 73 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 74 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 75 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 76 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 77 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 78 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 79 #define CONFIG_SYS_FSL_RMU 80 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 81 #define CONFIG_SYS_FSL_ERRATUM_A005125 82 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 83 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 84 85 #elif defined(CONFIG_MPC8555) 86 #define CONFIG_MAX_CPUS 1 87 #define CONFIG_SYS_FSL_NUM_LAWS 8 88 #define CONFIG_SYS_FSL_DDRC_GEN1 89 #define CONFIG_SYS_FSL_SEC_COMPAT 2 90 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 91 92 #elif defined(CONFIG_MPC8560) 93 #define CONFIG_MAX_CPUS 1 94 #define CONFIG_SYS_FSL_NUM_LAWS 8 95 #define CONFIG_SYS_FSL_DDRC_GEN1 96 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 97 98 #elif defined(CONFIG_MPC8568) 99 #define CONFIG_MAX_CPUS 1 100 #define CONFIG_SYS_FSL_NUM_LAWS 10 101 #define CONFIG_SYS_FSL_DDRC_GEN2 102 #define CONFIG_SYS_FSL_SEC_COMPAT 2 103 #define QE_MURAM_SIZE 0x10000UL 104 #define MAX_QE_RISC 2 105 #define QE_NUM_OF_SNUM 28 106 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 107 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 108 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 109 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 110 #define CONFIG_SYS_FSL_RMU 111 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 112 113 #elif defined(CONFIG_MPC8569) 114 #define CONFIG_MAX_CPUS 1 115 #define CONFIG_SYS_FSL_NUM_LAWS 10 116 #define CONFIG_SYS_FSL_SEC_COMPAT 2 117 #define QE_MURAM_SIZE 0x20000UL 118 #define MAX_QE_RISC 4 119 #define QE_NUM_OF_SNUM 46 120 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 121 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 122 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 123 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 124 #define CONFIG_SYS_FSL_RMU 125 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 126 #define CONFIG_SYS_FSL_ERRATUM_A004508 127 #define CONFIG_SYS_FSL_ERRATUM_A005125 128 129 #elif defined(CONFIG_MPC8572) 130 #define CONFIG_MAX_CPUS 2 131 #define CONFIG_SYS_FSL_NUM_LAWS 12 132 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 133 #define CONFIG_SYS_FSL_SEC_COMPAT 2 134 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 135 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 136 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 137 #define CONFIG_SYS_FSL_ERRATUM_A004508 138 #define CONFIG_SYS_FSL_ERRATUM_A005125 139 140 #elif defined(CONFIG_P1010) 141 #define CONFIG_MAX_CPUS 1 142 #define CONFIG_FSL_SDHC_V2_3 143 #define CONFIG_SYS_FSL_NUM_LAWS 12 144 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 145 #define CONFIG_TSECV2 146 #define CONFIG_SYS_FSL_SEC_COMPAT 4 147 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 148 #define CONFIG_NUM_DDR_CONTROLLERS 1 149 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 150 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 151 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 152 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 153 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 155 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 156 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 157 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 158 #define CONFIG_SYS_FSL_ERRATUM_A005125 159 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 160 #define CONFIG_SYS_FSL_ERRATUM_A004508 161 #define CONFIG_SYS_FSL_ERRATUM_A007075 162 #define CONFIG_SYS_FSL_ERRATUM_A006261 163 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 164 #define CONFIG_ESDHC_HC_BLK_ADDR 165 166 /* P1011 is single core version of P1020 */ 167 #elif defined(CONFIG_P1011) 168 #define CONFIG_MAX_CPUS 1 169 #define CONFIG_SYS_FSL_NUM_LAWS 12 170 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 171 #define CONFIG_TSECV2 172 #define CONFIG_FSL_PCIE_DISABLE_ASPM 173 #define CONFIG_SYS_FSL_SEC_COMPAT 2 174 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 175 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 176 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 177 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 178 #define CONFIG_SYS_FSL_ERRATUM_A004508 179 #define CONFIG_SYS_FSL_ERRATUM_A005125 180 181 /* P1012 is single core version of P1021 */ 182 #elif defined(CONFIG_P1012) 183 #define CONFIG_MAX_CPUS 1 184 #define CONFIG_SYS_FSL_NUM_LAWS 12 185 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 186 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 187 #define CONFIG_TSECV2 188 #define CONFIG_FSL_PCIE_DISABLE_ASPM 189 #define CONFIG_SYS_FSL_SEC_COMPAT 2 190 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 191 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 192 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 193 #define QE_MURAM_SIZE 0x6000UL 194 #define MAX_QE_RISC 1 195 #define QE_NUM_OF_SNUM 28 196 #define CONFIG_SYS_FSL_ERRATUM_A004508 197 #define CONFIG_SYS_FSL_ERRATUM_A005125 198 199 /* P1013 is single core version of P1022 */ 200 #elif defined(CONFIG_P1013) 201 #define CONFIG_MAX_CPUS 1 202 #define CONFIG_SYS_FSL_NUM_LAWS 12 203 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 204 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 205 #define CONFIG_TSECV2 206 #define CONFIG_SYS_FSL_SEC_COMPAT 2 207 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 208 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 209 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 210 #define CONFIG_FSL_SATA_ERRATUM_A001 211 #define CONFIG_SYS_FSL_ERRATUM_A004508 212 #define CONFIG_SYS_FSL_ERRATUM_A005125 213 214 #elif defined(CONFIG_P1014) 215 #define CONFIG_MAX_CPUS 1 216 #define CONFIG_FSL_SDHC_V2_3 217 #define CONFIG_SYS_FSL_NUM_LAWS 12 218 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 219 #define CONFIG_TSECV2 220 #define CONFIG_SYS_FSL_SEC_COMPAT 4 221 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 222 #define CONFIG_NUM_DDR_CONTROLLERS 1 223 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 224 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 225 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 226 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 227 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 228 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 229 #define CONFIG_SYS_FSL_ERRATUM_A004508 230 231 /* P1017 is single core version of P1023 */ 232 #elif defined(CONFIG_P1017) 233 #define CONFIG_MAX_CPUS 1 234 #define CONFIG_SYS_FSL_NUM_LAWS 12 235 #define CONFIG_SYS_FSL_SEC_COMPAT 4 236 #define CONFIG_SYS_NUM_FMAN 1 237 #define CONFIG_SYS_NUM_FM1_DTSEC 2 238 #define CONFIG_NUM_DDR_CONTROLLERS 1 239 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 240 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 241 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 242 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 243 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 244 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 245 #define CONFIG_SYS_FSL_ERRATUM_A004508 246 #define CONFIG_SYS_FSL_ERRATUM_A005125 247 248 #elif defined(CONFIG_P1020) 249 #define CONFIG_MAX_CPUS 2 250 #define CONFIG_SYS_FSL_NUM_LAWS 12 251 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 252 #define CONFIG_TSECV2 253 #define CONFIG_FSL_PCIE_DISABLE_ASPM 254 #define CONFIG_SYS_FSL_SEC_COMPAT 2 255 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 256 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 257 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 258 #define CONFIG_SYS_FSL_ERRATUM_A004508 259 #define CONFIG_SYS_FSL_ERRATUM_A005125 260 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 261 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 262 #endif 263 264 #elif defined(CONFIG_P1021) 265 #define CONFIG_MAX_CPUS 2 266 #define CONFIG_SYS_FSL_NUM_LAWS 12 267 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 268 #define CONFIG_TSECV2 269 #define CONFIG_FSL_PCIE_DISABLE_ASPM 270 #define CONFIG_SYS_FSL_SEC_COMPAT 2 271 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 272 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 273 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 274 #define QE_MURAM_SIZE 0x6000UL 275 #define MAX_QE_RISC 1 276 #define QE_NUM_OF_SNUM 28 277 #define CONFIG_SYS_FSL_ERRATUM_A004508 278 #define CONFIG_SYS_FSL_ERRATUM_A005125 279 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 280 281 #elif defined(CONFIG_P1022) 282 #define CONFIG_MAX_CPUS 2 283 #define CONFIG_SYS_FSL_NUM_LAWS 12 284 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 285 #define CONFIG_TSECV2 286 #define CONFIG_SYS_FSL_SEC_COMPAT 2 287 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 288 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 289 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 290 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 291 #define CONFIG_FSL_SATA_ERRATUM_A001 292 #define CONFIG_SYS_FSL_ERRATUM_A004508 293 #define CONFIG_SYS_FSL_ERRATUM_A005125 294 295 #elif defined(CONFIG_P1023) 296 #define CONFIG_MAX_CPUS 2 297 #define CONFIG_SYS_FSL_NUM_LAWS 12 298 #define CONFIG_SYS_FSL_SEC_COMPAT 4 299 #define CONFIG_SYS_NUM_FMAN 1 300 #define CONFIG_SYS_NUM_FM1_DTSEC 2 301 #define CONFIG_NUM_DDR_CONTROLLERS 1 302 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 303 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 304 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 305 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 306 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 307 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 308 #define CONFIG_SYS_FSL_ERRATUM_A004508 309 #define CONFIG_SYS_FSL_ERRATUM_A005125 310 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 311 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 312 313 /* P1024 is lower end variant of P1020 */ 314 #elif defined(CONFIG_P1024) 315 #define CONFIG_MAX_CPUS 2 316 #define CONFIG_SYS_FSL_NUM_LAWS 12 317 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 318 #define CONFIG_TSECV2 319 #define CONFIG_FSL_PCIE_DISABLE_ASPM 320 #define CONFIG_SYS_FSL_SEC_COMPAT 2 321 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 322 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 323 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 324 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 325 #define CONFIG_SYS_FSL_ERRATUM_A004508 326 #define CONFIG_SYS_FSL_ERRATUM_A005125 327 328 /* P1025 is lower end variant of P1021 */ 329 #elif defined(CONFIG_P1025) 330 #define CONFIG_MAX_CPUS 2 331 #define CONFIG_SYS_FSL_NUM_LAWS 12 332 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 333 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 334 #define CONFIG_TSECV2 335 #define CONFIG_FSL_PCIE_DISABLE_ASPM 336 #define CONFIG_SYS_FSL_SEC_COMPAT 2 337 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 338 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 339 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 340 #define QE_MURAM_SIZE 0x6000UL 341 #define MAX_QE_RISC 1 342 #define QE_NUM_OF_SNUM 28 343 #define CONFIG_SYS_FSL_ERRATUM_A004508 344 #define CONFIG_SYS_FSL_ERRATUM_A005125 345 346 /* P2010 is single core version of P2020 */ 347 #elif defined(CONFIG_P2010) 348 #define CONFIG_MAX_CPUS 1 349 #define CONFIG_SYS_FSL_NUM_LAWS 12 350 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 351 #define CONFIG_SYS_FSL_SEC_COMPAT 2 352 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 353 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 354 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 355 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 356 #define CONFIG_SYS_FSL_ERRATUM_A004508 357 #define CONFIG_SYS_FSL_ERRATUM_A005125 358 359 #elif defined(CONFIG_P2020) 360 #define CONFIG_MAX_CPUS 2 361 #define CONFIG_SYS_FSL_NUM_LAWS 12 362 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 363 #define CONFIG_SYS_FSL_SEC_COMPAT 2 364 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 365 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 366 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 367 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 368 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 369 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 370 #define CONFIG_SYS_FSL_RMU 371 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 372 #define CONFIG_SYS_FSL_ERRATUM_A004508 373 #define CONFIG_SYS_FSL_ERRATUM_A005125 374 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 375 376 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 377 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 378 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 379 #define CONFIG_MAX_CPUS 4 380 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 381 #define CONFIG_SYS_FSL_NUM_LAWS 32 382 #define CONFIG_SYS_FSL_SEC_COMPAT 4 383 #define CONFIG_SYS_NUM_FMAN 1 384 #define CONFIG_SYS_NUM_FM1_DTSEC 5 385 #define CONFIG_SYS_NUM_FM1_10GEC 1 386 #define CONFIG_NUM_DDR_CONTROLLERS 1 387 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 388 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 389 #define CONFIG_SYS_FSL_TBCLK_DIV 32 390 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 391 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 392 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 393 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 394 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 395 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 396 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 397 #define CONFIG_SYS_FSL_ERRATUM_USB14 398 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 399 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 400 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 401 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 402 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 403 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 404 #define CONFIG_SYS_FSL_ERRATUM_A004510 405 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 406 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 407 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 408 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 409 #define CONFIG_SYS_FSL_ERRATUM_A004849 410 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 411 #define CONFIG_SYS_FSL_ERRATUM_A006261 412 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 413 414 #elif defined(CONFIG_PPC_P3041) 415 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 416 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 417 #define CONFIG_MAX_CPUS 4 418 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 419 #define CONFIG_SYS_FSL_NUM_LAWS 32 420 #define CONFIG_SYS_FSL_SEC_COMPAT 4 421 #define CONFIG_SYS_NUM_FMAN 1 422 #define CONFIG_SYS_NUM_FM1_DTSEC 5 423 #define CONFIG_SYS_NUM_FM1_10GEC 1 424 #define CONFIG_NUM_DDR_CONTROLLERS 1 425 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 426 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 427 #define CONFIG_SYS_FSL_TBCLK_DIV 32 428 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 429 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 430 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 431 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 432 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 433 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 434 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 435 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 436 #define CONFIG_SYS_FSL_ERRATUM_USB14 437 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 438 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 439 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 440 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 441 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 442 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 443 #define CONFIG_SYS_FSL_ERRATUM_A004510 444 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 445 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 446 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 447 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 448 #define CONFIG_SYS_FSL_ERRATUM_A004849 449 #define CONFIG_SYS_FSL_ERRATUM_A005812 450 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 451 #define CONFIG_SYS_FSL_ERRATUM_A006261 452 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 453 454 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 455 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 456 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 457 #define CONFIG_MAX_CPUS 8 458 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 459 #define CONFIG_SYS_FSL_NUM_LAWS 32 460 #define CONFIG_SYS_FSL_SEC_COMPAT 4 461 #define CONFIG_SYS_NUM_FMAN 2 462 #define CONFIG_SYS_NUM_FM1_DTSEC 4 463 #define CONFIG_SYS_NUM_FM2_DTSEC 4 464 #define CONFIG_SYS_NUM_FM1_10GEC 1 465 #define CONFIG_SYS_NUM_FM2_10GEC 1 466 #define CONFIG_NUM_DDR_CONTROLLERS 2 467 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 468 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 469 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 470 #define CONFIG_SYS_FSL_TBCLK_DIV 16 471 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 472 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 473 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 474 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 475 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 476 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 477 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 478 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 479 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 480 #define CONFIG_SYS_P4080_ERRATUM_CPU22 481 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 482 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 483 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 484 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 485 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 486 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 487 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 488 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 489 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 490 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 491 #define CONFIG_SYS_FSL_RMU 492 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 493 #define CONFIG_SYS_FSL_ERRATUM_A004510 494 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 495 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 496 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 497 #define CONFIG_SYS_FSL_ERRATUM_A004849 498 #define CONFIG_SYS_FSL_ERRATUM_A004580 499 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 500 #define CONFIG_SYS_FSL_ERRATUM_A005812 501 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 502 #define CONFIG_SYS_FSL_ERRATUM_A007075 503 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 504 505 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 506 #define CONFIG_SYS_PPC64 /* 64-bit core */ 507 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 508 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 509 #define CONFIG_MAX_CPUS 2 510 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 511 #define CONFIG_SYS_FSL_NUM_LAWS 32 512 #define CONFIG_SYS_FSL_SEC_COMPAT 4 513 #define CONFIG_SYS_NUM_FMAN 1 514 #define CONFIG_SYS_NUM_FM1_DTSEC 5 515 #define CONFIG_SYS_NUM_FM1_10GEC 1 516 #define CONFIG_NUM_DDR_CONTROLLERS 2 517 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 518 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 519 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 520 #define CONFIG_SYS_FSL_TBCLK_DIV 32 521 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 522 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 523 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 524 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 525 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 526 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 527 #define CONFIG_SYS_FSL_ERRATUM_USB14 528 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 529 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 530 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 531 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 532 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 533 #define CONFIG_SYS_FSL_ERRATUM_A004510 534 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 535 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 536 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 537 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 538 #define CONFIG_SYS_FSL_ERRATUM_A006261 539 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 540 541 #elif defined(CONFIG_PPC_P5040) 542 #define CONFIG_SYS_PPC64 543 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 544 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 545 #define CONFIG_MAX_CPUS 4 546 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 547 #define CONFIG_SYS_FSL_NUM_LAWS 32 548 #define CONFIG_SYS_FSL_SEC_COMPAT 4 549 #define CONFIG_SYS_NUM_FMAN 2 550 #define CONFIG_SYS_NUM_FM1_DTSEC 5 551 #define CONFIG_SYS_NUM_FM1_10GEC 1 552 #define CONFIG_SYS_NUM_FM2_DTSEC 5 553 #define CONFIG_SYS_NUM_FM2_10GEC 1 554 #define CONFIG_NUM_DDR_CONTROLLERS 2 555 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 556 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 557 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 558 #define CONFIG_SYS_FSL_TBCLK_DIV 16 559 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 560 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 561 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 562 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 563 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 564 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 565 #define CONFIG_SYS_FSL_ERRATUM_USB14 566 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 567 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 568 #define CONFIG_SYS_FSL_ERRATUM_A004699 569 #define CONFIG_SYS_FSL_ERRATUM_A004510 570 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 571 #define CONFIG_SYS_FSL_ERRATUM_A006261 572 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 573 #define CONFIG_SYS_FSL_ERRATUM_A005812 574 575 #elif defined(CONFIG_BSC9131) 576 #define CONFIG_MAX_CPUS 1 577 #define CONFIG_FSL_SDHC_V2_3 578 #define CONFIG_SYS_FSL_NUM_LAWS 12 579 #define CONFIG_TSECV2 580 #define CONFIG_SYS_FSL_SEC_COMPAT 4 581 #define CONFIG_NUM_DDR_CONTROLLERS 1 582 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 583 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 584 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 585 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 586 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 587 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 588 #define CONFIG_NAND_FSL_IFC 589 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 590 #define CONFIG_SYS_FSL_ERRATUM_A005125 591 #define CONFIG_ESDHC_HC_BLK_ADDR 592 593 #elif defined(CONFIG_BSC9132) 594 #define CONFIG_MAX_CPUS 2 595 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 596 #define CONFIG_FSL_SDHC_V2_3 597 #define CONFIG_SYS_FSL_NUM_LAWS 12 598 #define CONFIG_TSECV2 599 #define CONFIG_SYS_FSL_SEC_COMPAT 4 600 #define CONFIG_NUM_DDR_CONTROLLERS 2 601 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 602 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 603 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 604 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 605 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 606 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 607 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 608 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 609 #define CONFIG_NAND_FSL_IFC 610 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 611 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 612 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 613 #define CONFIG_SYS_FSL_ERRATUM_A005125 614 #define CONFIG_SYS_FSL_ERRATUM_A005434 615 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 616 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 617 #define CONFIG_ESDHC_HC_BLK_ADDR 618 619 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 620 defined(CONFIG_PPC_T4080) 621 #define CONFIG_E6500 622 #define CONFIG_SYS_PPC64 /* 64-bit core */ 623 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 624 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 625 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 626 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 627 #ifdef CONFIG_PPC_T4240 628 #define CONFIG_MAX_CPUS 12 629 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 630 #define CONFIG_SYS_NUM_FM1_DTSEC 8 631 #define CONFIG_SYS_NUM_FM1_10GEC 2 632 #define CONFIG_SYS_NUM_FM2_DTSEC 8 633 #define CONFIG_SYS_NUM_FM2_10GEC 2 634 #define CONFIG_NUM_DDR_CONTROLLERS 3 635 #else 636 #define CONFIG_SYS_NUM_FM1_DTSEC 6 637 #define CONFIG_SYS_NUM_FM1_10GEC 1 638 #define CONFIG_SYS_NUM_FM2_DTSEC 8 639 #define CONFIG_SYS_NUM_FM2_10GEC 1 640 #define CONFIG_NUM_DDR_CONTROLLERS 2 641 #if defined(CONFIG_PPC_T4160) 642 #define CONFIG_MAX_CPUS 8 643 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 644 #elif defined(CONFIG_PPC_T4080) 645 #define CONFIG_MAX_CPUS 4 646 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } 647 #endif 648 #endif 649 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 650 #define CONFIG_SYS_FSL_NUM_LAWS 32 651 #define CONFIG_SYS_FSL_SRDS_1 652 #define CONFIG_SYS_FSL_SRDS_2 653 #define CONFIG_SYS_FSL_SRDS_3 654 #define CONFIG_SYS_FSL_SRDS_4 655 #define CONFIG_SYS_FSL_SEC_COMPAT 4 656 #define CONFIG_SYS_NUM_FMAN 2 657 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 658 #define CONFIG_SYS_PME_CLK 0 659 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 660 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 661 #define CONFIG_SYS_FMAN_V3 662 #define CONFIG_SYS_FM1_CLK 3 663 #define CONFIG_SYS_FM2_CLK 3 664 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 665 #define CONFIG_SYS_FSL_TBCLK_DIV 16 666 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 667 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 668 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 669 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 670 #define CONFIG_SYS_FSL_SRIO_LIODN 671 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 672 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 673 #define CONFIG_SYS_FSL_ERRATUM_A004468 674 #define CONFIG_SYS_FSL_ERRATUM_A_004934 675 #define CONFIG_SYS_FSL_ERRATUM_A005871 676 #define CONFIG_SYS_FSL_ERRATUM_A006261 677 #define CONFIG_SYS_FSL_ERRATUM_A006379 678 #define CONFIG_SYS_FSL_ERRATUM_A007186 679 #define CONFIG_SYS_FSL_ERRATUM_A006593 680 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 681 #define CONFIG_SYS_FSL_SFP_VER_3_0 682 #define CONFIG_SYS_FSL_PCI_VER_3_X 683 684 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 685 #define CONFIG_E6500 686 #define CONFIG_SYS_PPC64 /* 64-bit core */ 687 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 688 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 689 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 690 #define CONFIG_SYS_FSL_NUM_LAWS 32 691 #define CONFIG_SYS_FSL_SRDS_1 692 #define CONFIG_SYS_FSL_SRDS_2 693 #define CONFIG_SYS_FSL_SEC_COMPAT 4 694 #define CONFIG_SYS_NUM_FMAN 1 695 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 696 #define CONFIG_SYS_FM1_CLK 0 697 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 698 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 699 #define CONFIG_SYS_FMAN_V3 700 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 701 #define CONFIG_SYS_FSL_TBCLK_DIV 16 702 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 703 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 704 #define CONFIG_SYS_FSL_ERRATUM_A_004934 705 #define CONFIG_SYS_FSL_ERRATUM_A005871 706 #define CONFIG_SYS_FSL_ERRATUM_A006379 707 #define CONFIG_SYS_FSL_ERRATUM_A007186 708 #define CONFIG_SYS_FSL_ERRATUM_A006593 709 #define CONFIG_SYS_FSL_ERRATUM_A007075 710 #define CONFIG_SYS_FSL_ERRATUM_A006475 711 #define CONFIG_SYS_FSL_ERRATUM_A006384 712 #define CONFIG_SYS_FSL_ERRATUM_A007212 713 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 714 #define CONFIG_SYS_FSL_SFP_VER_3_0 715 716 #ifdef CONFIG_PPC_B4860 717 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 718 #define CONFIG_MAX_CPUS 4 719 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 720 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 721 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 722 #define CONFIG_SYS_NUM_FM1_DTSEC 6 723 #define CONFIG_SYS_NUM_FM1_10GEC 2 724 #define CONFIG_NUM_DDR_CONTROLLERS 2 725 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 726 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 727 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 728 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 729 #define CONFIG_SYS_FSL_SRIO_LIODN 730 #else 731 #define CONFIG_MAX_CPUS 2 732 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 733 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 734 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 735 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 736 #define CONFIG_SYS_NUM_FM1_DTSEC 4 737 #define CONFIG_SYS_NUM_FM1_10GEC 0 738 #define CONFIG_NUM_DDR_CONTROLLERS 1 739 #endif 740 741 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 742 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 743 #define CONFIG_E5500 744 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 745 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 746 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 747 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 748 #ifdef CONFIG_SYS_FSL_DDR4 749 #define CONFIG_SYS_FSL_DDRC_GEN4 750 #endif 751 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 752 #define CONFIG_MAX_CPUS 4 753 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 754 #define CONFIG_MAX_CPUS 2 755 #endif 756 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 757 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 758 #define CONFIG_SYS_SDHC_CLOCK 0 759 #define CONFIG_SYS_FSL_NUM_LAWS 16 760 #define CONFIG_SYS_FSL_SRDS_1 761 #define CONFIG_SYS_FSL_SEC_COMPAT 5 762 #define CONFIG_SYS_NUM_FMAN 1 763 #define CONFIG_SYS_NUM_FM1_DTSEC 5 764 #define CONFIG_NUM_DDR_CONTROLLERS 1 765 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 766 #define CONFIG_PME_PLAT_CLK_DIV 2 767 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 768 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 769 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 770 #define CONFIG_SYS_FMAN_V3 771 #define CONFIG_FM_PLAT_CLK_DIV 1 772 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 773 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 774 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 775 #define CONFIG_SYS_FSL_TBCLK_DIV 16 776 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 777 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 778 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 779 #define CONFIG_SYS_FSL_ERRATUM_A006261 780 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 781 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 782 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 783 #define QE_MURAM_SIZE 0x6000UL 784 #define MAX_QE_RISC 1 785 #define QE_NUM_OF_SNUM 28 786 787 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 788 #define CONFIG_E6500 789 #define CONFIG_SYS_PPC64 /* 64-bit core */ 790 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 791 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 792 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 793 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 794 #define CONFIG_SYS_FSL_QMAN_V3 795 #define CONFIG_MAX_CPUS 4 796 #define CONFIG_SYS_FSL_NUM_LAWS 32 797 #define CONFIG_SYS_FSL_SEC_COMPAT 4 798 #define CONFIG_SYS_NUM_FMAN 1 799 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 800 #define CONFIG_SYS_FSL_SRDS_1 801 #define CONFIG_SYS_FSL_PCI_VER_3_X 802 #if defined(CONFIG_PPC_T2080) 803 #define CONFIG_SYS_NUM_FM1_DTSEC 8 804 #define CONFIG_SYS_NUM_FM1_10GEC 4 805 #define CONFIG_SYS_FSL_SRDS_2 806 #define CONFIG_SYS_FSL_SRIO_LIODN 807 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 808 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 809 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 810 #elif defined(CONFIG_PPC_T2081) 811 #define CONFIG_SYS_NUM_FM1_DTSEC 6 812 #define CONFIG_SYS_NUM_FM1_10GEC 2 813 #endif 814 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 815 #define CONFIG_NUM_DDR_CONTROLLERS 1 816 #define CONFIG_PME_PLAT_CLK_DIV 1 817 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 818 #define CONFIG_SYS_FM1_CLK 0 819 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 820 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 821 #define CONFIG_SYS_FMAN_V3 822 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 823 #define CONFIG_SYS_FSL_TBCLK_DIV 16 824 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 825 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 826 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 827 #define CONFIG_SYS_FSL_ERRATUM_A007212 828 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 829 #define CONFIG_SYS_FSL_SFP_VER_3_0 830 #define CONFIG_SYS_FSL_ISBC_VER 2 831 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 832 #define CONFIG_SYS_FSL_ERRATUM_A006261 833 #define CONFIG_SYS_FSL_ERRATUM_A006593 834 #define CONFIG_SYS_FSL_ERRATUM_A007186 835 #define CONFIG_SYS_FSL_ERRATUM_A006379 836 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 837 #define CONFIG_SYS_FSL_SFP_VER_3_0 838 839 840 #elif defined(CONFIG_PPC_C29X) 841 #define CONFIG_MAX_CPUS 1 842 #define CONFIG_FSL_SDHC_V2_3 843 #define CONFIG_SYS_FSL_NUM_LAWS 12 844 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 845 #define CONFIG_TSECV2_1 846 #define CONFIG_SYS_FSL_SEC_COMPAT 6 847 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 848 #define CONFIG_NUM_DDR_CONTROLLERS 1 849 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 850 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 851 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 852 #define CONFIG_SYS_FSL_ERRATUM_A005125 853 854 #elif defined(CONFIG_QEMU_E500) 855 #define CONFIG_MAX_CPUS 1 856 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 857 858 #else 859 #error Processor type not defined for this platform 860 #endif 861 862 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 863 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 864 #endif 865 866 #ifdef CONFIG_E6500 867 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 868 #else 869 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 870 #endif 871 872 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 873 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 874 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 875 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 876 #define CONFIG_SYS_FSL_DDRC_GEN3 877 #endif 878 879 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 880