1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #include <fsl_ddrc_version.h> 23 #define CONFIG_SYS_FSL_DDR_BE 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 #define CONFIG_SYS_FSL_SEC_BE 28 #define CONFIG_SYS_FSL_SFP_BE 29 #define CONFIG_SYS_FSL_SEC_MON_BE 30 31 /* Number of TLB CAM entries we have on FSL Book-E chips */ 32 #if defined(CONFIG_E500MC) 33 #define CONFIG_SYS_NUM_TLBCAMS 64 34 #elif defined(CONFIG_E500) 35 #define CONFIG_SYS_NUM_TLBCAMS 16 36 #endif 37 38 #if defined(CONFIG_MPC8536) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 12 41 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 42 #define CONFIG_SYS_FSL_SEC_COMPAT 2 43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 44 #define CONFIG_SYS_FSL_ERRATUM_A004508 45 #define CONFIG_SYS_FSL_ERRATUM_A005125 46 47 #elif defined(CONFIG_MPC8540) 48 #define CONFIG_MAX_CPUS 1 49 #define CONFIG_SYS_FSL_NUM_LAWS 8 50 #define CONFIG_SYS_FSL_DDRC_GEN1 51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 52 53 #elif defined(CONFIG_MPC8541) 54 #define CONFIG_MAX_CPUS 1 55 #define CONFIG_SYS_FSL_NUM_LAWS 8 56 #define CONFIG_SYS_FSL_DDRC_GEN1 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8544) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_DDRC_GEN2 64 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 65 #define CONFIG_SYS_FSL_SEC_COMPAT 2 66 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 67 #define CONFIG_SYS_FSL_ERRATUM_A005125 68 69 #elif defined(CONFIG_MPC8548) 70 #define CONFIG_MAX_CPUS 1 71 #define CONFIG_SYS_FSL_NUM_LAWS 10 72 #define CONFIG_SYS_FSL_DDRC_GEN2 73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 74 #define CONFIG_SYS_FSL_SEC_COMPAT 2 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 82 #define CONFIG_SYS_FSL_RMU 83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 84 #define CONFIG_SYS_FSL_ERRATUM_A005125 85 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 86 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 87 88 #elif defined(CONFIG_MPC8555) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 8 91 #define CONFIG_SYS_FSL_DDRC_GEN1 92 #define CONFIG_SYS_FSL_SEC_COMPAT 2 93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 94 95 #elif defined(CONFIG_MPC8560) 96 #define CONFIG_MAX_CPUS 1 97 #define CONFIG_SYS_FSL_NUM_LAWS 8 98 #define CONFIG_SYS_FSL_DDRC_GEN1 99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 100 101 #elif defined(CONFIG_MPC8568) 102 #define CONFIG_MAX_CPUS 1 103 #define CONFIG_SYS_FSL_NUM_LAWS 10 104 #define CONFIG_SYS_FSL_DDRC_GEN2 105 #define CONFIG_SYS_FSL_SEC_COMPAT 2 106 #define QE_MURAM_SIZE 0x10000UL 107 #define MAX_QE_RISC 2 108 #define QE_NUM_OF_SNUM 28 109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 113 #define CONFIG_SYS_FSL_RMU 114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 115 116 #elif defined(CONFIG_MPC8569) 117 #define CONFIG_MAX_CPUS 1 118 #define CONFIG_SYS_FSL_NUM_LAWS 10 119 #define CONFIG_SYS_FSL_SEC_COMPAT 2 120 #define QE_MURAM_SIZE 0x20000UL 121 #define MAX_QE_RISC 4 122 #define QE_NUM_OF_SNUM 46 123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 124 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 125 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 126 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 127 #define CONFIG_SYS_FSL_RMU 128 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 129 #define CONFIG_SYS_FSL_ERRATUM_A004508 130 #define CONFIG_SYS_FSL_ERRATUM_A005125 131 132 #elif defined(CONFIG_MPC8572) 133 #define CONFIG_MAX_CPUS 2 134 #define CONFIG_SYS_FSL_NUM_LAWS 12 135 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 136 #define CONFIG_SYS_FSL_SEC_COMPAT 2 137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 138 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 139 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 140 #define CONFIG_SYS_FSL_ERRATUM_A004508 141 #define CONFIG_SYS_FSL_ERRATUM_A005125 142 143 #elif defined(CONFIG_P1010) 144 #define CONFIG_MAX_CPUS 1 145 #define CONFIG_FSL_SDHC_V2_3 146 #define CONFIG_SYS_FSL_NUM_LAWS 12 147 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 148 #define CONFIG_TSECV2 149 #define CONFIG_SYS_FSL_SEC_COMPAT 4 150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 151 #define CONFIG_NUM_DDR_CONTROLLERS 1 152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 153 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 154 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 155 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 156 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 157 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 158 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 159 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 160 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 161 #define CONFIG_SYS_FSL_ERRATUM_A005125 162 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 163 #define CONFIG_SYS_FSL_ERRATUM_A004508 164 #define CONFIG_SYS_FSL_ERRATUM_A007075 165 #define CONFIG_SYS_FSL_ERRATUM_A006261 166 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 167 #define CONFIG_ESDHC_HC_BLK_ADDR 168 169 /* P1011 is single core version of P1020 */ 170 #elif defined(CONFIG_P1011) 171 #define CONFIG_MAX_CPUS 1 172 #define CONFIG_SYS_FSL_NUM_LAWS 12 173 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 174 #define CONFIG_TSECV2 175 #define CONFIG_FSL_PCIE_DISABLE_ASPM 176 #define CONFIG_SYS_FSL_SEC_COMPAT 2 177 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 178 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 179 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 180 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 181 #define CONFIG_SYS_FSL_ERRATUM_A004508 182 #define CONFIG_SYS_FSL_ERRATUM_A005125 183 184 /* P1012 is single core version of P1021 */ 185 #elif defined(CONFIG_P1012) 186 #define CONFIG_MAX_CPUS 1 187 #define CONFIG_SYS_FSL_NUM_LAWS 12 188 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 189 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 190 #define CONFIG_TSECV2 191 #define CONFIG_FSL_PCIE_DISABLE_ASPM 192 #define CONFIG_SYS_FSL_SEC_COMPAT 2 193 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 194 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 195 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 196 #define QE_MURAM_SIZE 0x6000UL 197 #define MAX_QE_RISC 1 198 #define QE_NUM_OF_SNUM 28 199 #define CONFIG_SYS_FSL_ERRATUM_A004508 200 #define CONFIG_SYS_FSL_ERRATUM_A005125 201 202 /* P1013 is single core version of P1022 */ 203 #elif defined(CONFIG_P1013) 204 #define CONFIG_MAX_CPUS 1 205 #define CONFIG_SYS_FSL_NUM_LAWS 12 206 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 207 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 208 #define CONFIG_TSECV2 209 #define CONFIG_SYS_FSL_SEC_COMPAT 2 210 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 211 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 212 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 213 #define CONFIG_FSL_SATA_ERRATUM_A001 214 #define CONFIG_SYS_FSL_ERRATUM_A004508 215 #define CONFIG_SYS_FSL_ERRATUM_A005125 216 217 #elif defined(CONFIG_P1014) 218 #define CONFIG_MAX_CPUS 1 219 #define CONFIG_FSL_SDHC_V2_3 220 #define CONFIG_SYS_FSL_NUM_LAWS 12 221 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 222 #define CONFIG_TSECV2 223 #define CONFIG_SYS_FSL_SEC_COMPAT 4 224 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 225 #define CONFIG_NUM_DDR_CONTROLLERS 1 226 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 227 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 228 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 229 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 230 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 231 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 232 #define CONFIG_SYS_FSL_ERRATUM_A004508 233 234 /* P1017 is single core version of P1023 */ 235 #elif defined(CONFIG_P1017) 236 #define CONFIG_MAX_CPUS 1 237 #define CONFIG_SYS_FSL_NUM_LAWS 12 238 #define CONFIG_SYS_FSL_SEC_COMPAT 4 239 #define CONFIG_SYS_NUM_FMAN 1 240 #define CONFIG_SYS_NUM_FM1_DTSEC 2 241 #define CONFIG_NUM_DDR_CONTROLLERS 1 242 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 243 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 244 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 245 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 246 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 247 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 248 #define CONFIG_SYS_FSL_ERRATUM_A004508 249 #define CONFIG_SYS_FSL_ERRATUM_A005125 250 251 #elif defined(CONFIG_P1020) 252 #define CONFIG_MAX_CPUS 2 253 #define CONFIG_SYS_FSL_NUM_LAWS 12 254 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 255 #define CONFIG_TSECV2 256 #define CONFIG_FSL_PCIE_DISABLE_ASPM 257 #define CONFIG_SYS_FSL_SEC_COMPAT 2 258 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 259 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 260 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 261 #define CONFIG_SYS_FSL_ERRATUM_A004508 262 #define CONFIG_SYS_FSL_ERRATUM_A005125 263 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 264 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 265 #endif 266 267 #elif defined(CONFIG_P1021) 268 #define CONFIG_MAX_CPUS 2 269 #define CONFIG_SYS_FSL_NUM_LAWS 12 270 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 271 #define CONFIG_TSECV2 272 #define CONFIG_FSL_PCIE_DISABLE_ASPM 273 #define CONFIG_SYS_FSL_SEC_COMPAT 2 274 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 275 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 276 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 277 #define QE_MURAM_SIZE 0x6000UL 278 #define MAX_QE_RISC 1 279 #define QE_NUM_OF_SNUM 28 280 #define CONFIG_SYS_FSL_ERRATUM_A004508 281 #define CONFIG_SYS_FSL_ERRATUM_A005125 282 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 283 284 #elif defined(CONFIG_P1022) 285 #define CONFIG_MAX_CPUS 2 286 #define CONFIG_SYS_FSL_NUM_LAWS 12 287 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 288 #define CONFIG_TSECV2 289 #define CONFIG_SYS_FSL_SEC_COMPAT 2 290 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 291 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 292 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 293 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 294 #define CONFIG_FSL_SATA_ERRATUM_A001 295 #define CONFIG_SYS_FSL_ERRATUM_A004508 296 #define CONFIG_SYS_FSL_ERRATUM_A005125 297 298 #elif defined(CONFIG_P1023) 299 #define CONFIG_MAX_CPUS 2 300 #define CONFIG_SYS_FSL_NUM_LAWS 12 301 #define CONFIG_SYS_FSL_SEC_COMPAT 4 302 #define CONFIG_SYS_NUM_FMAN 1 303 #define CONFIG_SYS_NUM_FM1_DTSEC 2 304 #define CONFIG_NUM_DDR_CONTROLLERS 1 305 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 306 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 307 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 308 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 309 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 310 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 311 #define CONFIG_SYS_FSL_ERRATUM_A004508 312 #define CONFIG_SYS_FSL_ERRATUM_A005125 313 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 314 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 315 316 /* P1024 is lower end variant of P1020 */ 317 #elif defined(CONFIG_P1024) 318 #define CONFIG_MAX_CPUS 2 319 #define CONFIG_SYS_FSL_NUM_LAWS 12 320 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 321 #define CONFIG_TSECV2 322 #define CONFIG_FSL_PCIE_DISABLE_ASPM 323 #define CONFIG_SYS_FSL_SEC_COMPAT 2 324 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 325 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 326 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 327 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 328 #define CONFIG_SYS_FSL_ERRATUM_A004508 329 #define CONFIG_SYS_FSL_ERRATUM_A005125 330 331 /* P1025 is lower end variant of P1021 */ 332 #elif defined(CONFIG_P1025) 333 #define CONFIG_MAX_CPUS 2 334 #define CONFIG_SYS_FSL_NUM_LAWS 12 335 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 336 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 337 #define CONFIG_TSECV2 338 #define CONFIG_FSL_PCIE_DISABLE_ASPM 339 #define CONFIG_SYS_FSL_SEC_COMPAT 2 340 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 341 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 342 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 343 #define QE_MURAM_SIZE 0x6000UL 344 #define MAX_QE_RISC 1 345 #define QE_NUM_OF_SNUM 28 346 #define CONFIG_SYS_FSL_ERRATUM_A004508 347 #define CONFIG_SYS_FSL_ERRATUM_A005125 348 349 /* P2010 is single core version of P2020 */ 350 #elif defined(CONFIG_P2010) 351 #define CONFIG_MAX_CPUS 1 352 #define CONFIG_SYS_FSL_NUM_LAWS 12 353 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 354 #define CONFIG_SYS_FSL_SEC_COMPAT 2 355 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 356 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 357 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 358 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 359 #define CONFIG_SYS_FSL_ERRATUM_A004508 360 #define CONFIG_SYS_FSL_ERRATUM_A005125 361 362 #elif defined(CONFIG_P2020) 363 #define CONFIG_MAX_CPUS 2 364 #define CONFIG_SYS_FSL_NUM_LAWS 12 365 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 366 #define CONFIG_SYS_FSL_SEC_COMPAT 2 367 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 368 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 369 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 370 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 371 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 372 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 373 #define CONFIG_SYS_FSL_RMU 374 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 375 #define CONFIG_SYS_FSL_ERRATUM_A004508 376 #define CONFIG_SYS_FSL_ERRATUM_A005125 377 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 378 379 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 380 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 381 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 382 #define CONFIG_MAX_CPUS 4 383 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 384 #define CONFIG_SYS_FSL_NUM_LAWS 32 385 #define CONFIG_SYS_FSL_SEC_COMPAT 4 386 #define CONFIG_SYS_NUM_FMAN 1 387 #define CONFIG_SYS_NUM_FM1_DTSEC 5 388 #define CONFIG_SYS_NUM_FM1_10GEC 1 389 #define CONFIG_NUM_DDR_CONTROLLERS 1 390 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 391 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 392 #define CONFIG_SYS_FSL_TBCLK_DIV 32 393 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 394 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 395 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 396 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 397 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 398 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 399 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 400 #define CONFIG_SYS_FSL_ERRATUM_USB14 401 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 402 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 403 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 404 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 405 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 406 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 407 #define CONFIG_SYS_FSL_ERRATUM_A004510 408 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 409 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 410 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 411 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 412 #define CONFIG_SYS_FSL_ERRATUM_A004849 413 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 414 #define CONFIG_SYS_FSL_ERRATUM_A006261 415 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 416 417 #elif defined(CONFIG_PPC_P3041) 418 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 419 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 420 #define CONFIG_MAX_CPUS 4 421 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 422 #define CONFIG_SYS_FSL_NUM_LAWS 32 423 #define CONFIG_SYS_FSL_SEC_COMPAT 4 424 #define CONFIG_SYS_NUM_FMAN 1 425 #define CONFIG_SYS_NUM_FM1_DTSEC 5 426 #define CONFIG_SYS_NUM_FM1_10GEC 1 427 #define CONFIG_NUM_DDR_CONTROLLERS 1 428 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 429 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 430 #define CONFIG_SYS_FSL_TBCLK_DIV 32 431 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 432 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 433 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 434 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 435 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 436 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 437 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 438 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 439 #define CONFIG_SYS_FSL_ERRATUM_USB14 440 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 441 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 442 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 443 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 444 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 445 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 446 #define CONFIG_SYS_FSL_ERRATUM_A004510 447 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 448 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 449 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 450 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 451 #define CONFIG_SYS_FSL_ERRATUM_A004849 452 #define CONFIG_SYS_FSL_ERRATUM_A005812 453 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 454 #define CONFIG_SYS_FSL_ERRATUM_A006261 455 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 456 457 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 458 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 459 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 460 #define CONFIG_MAX_CPUS 8 461 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 462 #define CONFIG_SYS_FSL_NUM_LAWS 32 463 #define CONFIG_SYS_FSL_SEC_COMPAT 4 464 #define CONFIG_SYS_NUM_FMAN 2 465 #define CONFIG_SYS_NUM_FM1_DTSEC 4 466 #define CONFIG_SYS_NUM_FM2_DTSEC 4 467 #define CONFIG_SYS_NUM_FM1_10GEC 1 468 #define CONFIG_SYS_NUM_FM2_10GEC 1 469 #define CONFIG_NUM_DDR_CONTROLLERS 2 470 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 471 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 472 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 473 #define CONFIG_SYS_FSL_TBCLK_DIV 16 474 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 475 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 476 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 477 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 478 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 479 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 480 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 481 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 482 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 483 #define CONFIG_SYS_P4080_ERRATUM_CPU22 484 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 485 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 486 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 487 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 488 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 489 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 490 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 491 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 492 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 493 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 494 #define CONFIG_SYS_FSL_RMU 495 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 496 #define CONFIG_SYS_FSL_ERRATUM_A004510 497 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 498 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 499 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 500 #define CONFIG_SYS_FSL_ERRATUM_A004849 501 #define CONFIG_SYS_FSL_ERRATUM_A004580 502 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 503 #define CONFIG_SYS_FSL_ERRATUM_A005812 504 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 505 #define CONFIG_SYS_FSL_ERRATUM_A007075 506 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 507 508 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 509 #define CONFIG_SYS_PPC64 /* 64-bit core */ 510 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 511 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 512 #define CONFIG_MAX_CPUS 2 513 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 514 #define CONFIG_SYS_FSL_NUM_LAWS 32 515 #define CONFIG_SYS_FSL_SEC_COMPAT 4 516 #define CONFIG_SYS_NUM_FMAN 1 517 #define CONFIG_SYS_NUM_FM1_DTSEC 5 518 #define CONFIG_SYS_NUM_FM1_10GEC 1 519 #define CONFIG_NUM_DDR_CONTROLLERS 2 520 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 521 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 522 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 523 #define CONFIG_SYS_FSL_TBCLK_DIV 32 524 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 525 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 526 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 527 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 528 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 529 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 530 #define CONFIG_SYS_FSL_ERRATUM_USB14 531 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 532 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 533 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 534 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 535 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 536 #define CONFIG_SYS_FSL_ERRATUM_A004510 537 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 538 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 539 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 540 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 541 #define CONFIG_SYS_FSL_ERRATUM_A006261 542 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 543 544 #elif defined(CONFIG_PPC_P5040) 545 #define CONFIG_SYS_PPC64 546 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 547 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 548 #define CONFIG_MAX_CPUS 4 549 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 550 #define CONFIG_SYS_FSL_NUM_LAWS 32 551 #define CONFIG_SYS_FSL_SEC_COMPAT 4 552 #define CONFIG_SYS_NUM_FMAN 2 553 #define CONFIG_SYS_NUM_FM1_DTSEC 5 554 #define CONFIG_SYS_NUM_FM1_10GEC 1 555 #define CONFIG_SYS_NUM_FM2_DTSEC 5 556 #define CONFIG_SYS_NUM_FM2_10GEC 1 557 #define CONFIG_NUM_DDR_CONTROLLERS 2 558 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 559 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 560 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 561 #define CONFIG_SYS_FSL_TBCLK_DIV 16 562 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 563 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 564 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 565 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 566 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 567 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 568 #define CONFIG_SYS_FSL_ERRATUM_USB14 569 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 570 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 571 #define CONFIG_SYS_FSL_ERRATUM_A004699 572 #define CONFIG_SYS_FSL_ERRATUM_A004510 573 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 574 #define CONFIG_SYS_FSL_ERRATUM_A006261 575 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 576 #define CONFIG_SYS_FSL_ERRATUM_A005812 577 578 #elif defined(CONFIG_BSC9131) 579 #define CONFIG_MAX_CPUS 1 580 #define CONFIG_FSL_SDHC_V2_3 581 #define CONFIG_SYS_FSL_NUM_LAWS 12 582 #define CONFIG_TSECV2 583 #define CONFIG_SYS_FSL_SEC_COMPAT 4 584 #define CONFIG_NUM_DDR_CONTROLLERS 1 585 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 586 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 587 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 588 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 589 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 590 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 591 #define CONFIG_NAND_FSL_IFC 592 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 593 #define CONFIG_SYS_FSL_ERRATUM_A005125 594 #define CONFIG_ESDHC_HC_BLK_ADDR 595 596 #elif defined(CONFIG_BSC9132) 597 #define CONFIG_MAX_CPUS 2 598 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 599 #define CONFIG_FSL_SDHC_V2_3 600 #define CONFIG_SYS_FSL_NUM_LAWS 12 601 #define CONFIG_TSECV2 602 #define CONFIG_SYS_FSL_SEC_COMPAT 4 603 #define CONFIG_NUM_DDR_CONTROLLERS 2 604 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 605 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 606 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 607 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 608 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 609 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 610 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 611 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 612 #define CONFIG_NAND_FSL_IFC 613 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 614 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 615 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 616 #define CONFIG_SYS_FSL_ERRATUM_A005125 617 #define CONFIG_SYS_FSL_ERRATUM_A005434 618 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 619 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 620 #define CONFIG_ESDHC_HC_BLK_ADDR 621 622 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 623 defined(CONFIG_PPC_T4080) 624 #define CONFIG_E6500 625 #define CONFIG_SYS_PPC64 /* 64-bit core */ 626 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 627 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 628 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 629 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 630 #ifdef CONFIG_PPC_T4240 631 #define CONFIG_MAX_CPUS 12 632 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 633 #define CONFIG_SYS_NUM_FM1_DTSEC 8 634 #define CONFIG_SYS_NUM_FM1_10GEC 2 635 #define CONFIG_SYS_NUM_FM2_DTSEC 8 636 #define CONFIG_SYS_NUM_FM2_10GEC 2 637 #define CONFIG_NUM_DDR_CONTROLLERS 3 638 #else 639 #define CONFIG_SYS_NUM_FM1_DTSEC 6 640 #define CONFIG_SYS_NUM_FM1_10GEC 1 641 #define CONFIG_SYS_NUM_FM2_DTSEC 8 642 #define CONFIG_SYS_NUM_FM2_10GEC 1 643 #define CONFIG_NUM_DDR_CONTROLLERS 2 644 #if defined(CONFIG_PPC_T4160) 645 #define CONFIG_MAX_CPUS 8 646 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 647 #elif defined(CONFIG_PPC_T4080) 648 #define CONFIG_MAX_CPUS 4 649 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } 650 #endif 651 #endif 652 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 653 #define CONFIG_SYS_FSL_NUM_LAWS 32 654 #define CONFIG_SYS_FSL_SRDS_1 655 #define CONFIG_SYS_FSL_SRDS_2 656 #define CONFIG_SYS_FSL_SRDS_3 657 #define CONFIG_SYS_FSL_SRDS_4 658 #define CONFIG_SYS_FSL_SEC_COMPAT 4 659 #define CONFIG_SYS_NUM_FMAN 2 660 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 661 #define CONFIG_SYS_PME_CLK 0 662 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 663 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 664 #define CONFIG_SYS_FMAN_V3 665 #define CONFIG_SYS_FM1_CLK 3 666 #define CONFIG_SYS_FM2_CLK 3 667 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 668 #define CONFIG_SYS_FSL_TBCLK_DIV 16 669 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 670 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 671 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 672 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 673 #define CONFIG_SYS_FSL_SRIO_LIODN 674 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 675 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 676 #define CONFIG_SYS_FSL_ERRATUM_A004468 677 #define CONFIG_SYS_FSL_ERRATUM_A_004934 678 #define CONFIG_SYS_FSL_ERRATUM_A005871 679 #define CONFIG_SYS_FSL_ERRATUM_A006261 680 #define CONFIG_SYS_FSL_ERRATUM_A006379 681 #define CONFIG_SYS_FSL_ERRATUM_A007186 682 #define CONFIG_SYS_FSL_ERRATUM_A006593 683 #define CONFIG_SYS_FSL_ERRATUM_A007798 684 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 685 #define CONFIG_SYS_FSL_SFP_VER_3_0 686 #define CONFIG_SYS_FSL_PCI_VER_3_X 687 688 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 689 #define CONFIG_E6500 690 #define CONFIG_SYS_PPC64 /* 64-bit core */ 691 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 692 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 693 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 694 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 695 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 696 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 697 #define CONFIG_SYS_FSL_NUM_LAWS 32 698 #define CONFIG_SYS_FSL_SRDS_1 699 #define CONFIG_SYS_FSL_SRDS_2 700 #define CONFIG_SYS_MAPLE 701 #define CONFIG_SYS_CPRI 702 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 703 #define CONFIG_SYS_FSL_SEC_COMPAT 4 704 #define CONFIG_SYS_NUM_FMAN 1 705 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 706 #define CONFIG_SYS_FM1_CLK 0 707 #define CONFIG_SYS_CPRI_CLK 3 708 #define CONFIG_SYS_ULB_CLK 4 709 #define CONFIG_SYS_ETVPE_CLK 1 710 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 711 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 712 #define CONFIG_SYS_FMAN_V3 713 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 714 #define CONFIG_SYS_FSL_TBCLK_DIV 16 715 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 716 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 717 #define CONFIG_SYS_FSL_ERRATUM_A_004934 718 #define CONFIG_SYS_FSL_ERRATUM_A005871 719 #define CONFIG_SYS_FSL_ERRATUM_A006379 720 #define CONFIG_SYS_FSL_ERRATUM_A007186 721 #define CONFIG_SYS_FSL_ERRATUM_A006593 722 #define CONFIG_SYS_FSL_ERRATUM_A007075 723 #define CONFIG_SYS_FSL_ERRATUM_A006475 724 #define CONFIG_SYS_FSL_ERRATUM_A006384 725 #define CONFIG_SYS_FSL_ERRATUM_A007212 726 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 727 #define CONFIG_SYS_FSL_SFP_VER_3_0 728 729 #ifdef CONFIG_PPC_B4860 730 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 731 #define CONFIG_MAX_CPUS 4 732 #define CONFIG_MAX_DSP_CPUS 12 733 #define CONFIG_NUM_DSP_CPUS 6 734 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 735 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 736 #define CONFIG_SYS_NUM_FM1_DTSEC 6 737 #define CONFIG_SYS_NUM_FM1_10GEC 2 738 #define CONFIG_NUM_DDR_CONTROLLERS 2 739 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 740 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 741 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 742 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 743 #define CONFIG_SYS_FSL_SRIO_LIODN 744 #else 745 #define CONFIG_MAX_CPUS 2 746 #define CONFIG_MAX_DSP_CPUS 2 747 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 748 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 749 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 750 #define CONFIG_SYS_NUM_FM1_DTSEC 4 751 #define CONFIG_SYS_NUM_FM1_10GEC 0 752 #define CONFIG_NUM_DDR_CONTROLLERS 1 753 #endif 754 755 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 756 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 757 #define CONFIG_E5500 758 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 759 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 760 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 761 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 762 #ifdef CONFIG_SYS_FSL_DDR4 763 #define CONFIG_SYS_FSL_DDRC_GEN4 764 #endif 765 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 766 #define CONFIG_MAX_CPUS 4 767 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 768 #define CONFIG_MAX_CPUS 2 769 #endif 770 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 771 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 772 #define CONFIG_SYS_SDHC_CLOCK 0 773 #define CONFIG_SYS_FSL_NUM_LAWS 16 774 #define CONFIG_SYS_FSL_SRDS_1 775 #define CONFIG_SYS_FSL_SEC_COMPAT 5 776 #define CONFIG_SYS_NUM_FMAN 1 777 #define CONFIG_SYS_NUM_FM1_DTSEC 5 778 #define CONFIG_NUM_DDR_CONTROLLERS 1 779 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 780 #define CONFIG_PME_PLAT_CLK_DIV 2 781 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 782 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 783 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 784 #define CONFIG_SYS_FSL_ERRATUM_A008044 785 #define CONFIG_SYS_FMAN_V3 786 #define CONFIG_FM_PLAT_CLK_DIV 1 787 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 788 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 789 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 790 #define CONFIG_SYS_FSL_TBCLK_DIV 16 791 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 792 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 793 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 794 #define CONFIG_SYS_FSL_ERRATUM_A006261 795 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 796 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 797 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 798 #define QE_MURAM_SIZE 0x6000UL 799 #define MAX_QE_RISC 1 800 #define QE_NUM_OF_SNUM 28 801 802 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ 803 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 804 #define CONFIG_E5500 805 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 806 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 807 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 808 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 809 #define CONFIG_SYS_FMAN_V3 810 #ifdef CONFIG_SYS_FSL_DDR4 811 #define CONFIG_SYS_FSL_DDRC_GEN4 812 #endif 813 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) 814 #define CONFIG_MAX_CPUS 2 815 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 816 #define CONFIG_MAX_CPUS 1 817 #endif 818 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 819 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 820 #define CONFIG_SYS_SDHC_CLOCK 0 821 #define CONFIG_SYS_FSL_NUM_LAWS 16 822 #define CONFIG_SYS_FSL_SRDS_1 823 #define CONFIG_SYS_FSL_SEC_COMPAT 5 824 #define CONFIG_SYS_NUM_FMAN 1 825 #define CONFIG_SYS_NUM_FM1_DTSEC 4 826 #define CONFIG_SYS_NUM_FM1_10GEC 1 827 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 828 #define CONFIG_NUM_DDR_CONTROLLERS 1 829 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 830 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 831 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 832 #define CONFIG_SYS_FM1_CLK 0 833 #define CONFIG_QBMAN_CLK_DIV 1 834 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 835 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 836 #define CONFIG_SYS_FSL_TBCLK_DIV 16 837 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 838 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 839 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 840 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 841 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 842 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 843 #define QE_MURAM_SIZE 0x6000UL 844 #define MAX_QE_RISC 1 845 #define QE_NUM_OF_SNUM 28 846 #define CONFIG_SYS_FSL_SFP_VER_3_0 847 848 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 849 #define CONFIG_E6500 850 #define CONFIG_SYS_PPC64 /* 64-bit core */ 851 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 852 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 853 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 854 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 855 #define CONFIG_SYS_FSL_QMAN_V3 856 #define CONFIG_MAX_CPUS 4 857 #define CONFIG_SYS_FSL_NUM_LAWS 32 858 #define CONFIG_SYS_FSL_SEC_COMPAT 4 859 #define CONFIG_SYS_NUM_FMAN 1 860 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 861 #define CONFIG_SYS_FSL_SRDS_1 862 #define CONFIG_SYS_FSL_PCI_VER_3_X 863 #if defined(CONFIG_PPC_T2080) 864 #define CONFIG_SYS_NUM_FM1_DTSEC 8 865 #define CONFIG_SYS_NUM_FM1_10GEC 4 866 #define CONFIG_SYS_FSL_SRDS_2 867 #define CONFIG_SYS_FSL_SRIO_LIODN 868 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 869 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 870 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 871 #elif defined(CONFIG_PPC_T2081) 872 #define CONFIG_SYS_NUM_FM1_DTSEC 6 873 #define CONFIG_SYS_NUM_FM1_10GEC 2 874 #endif 875 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 876 #define CONFIG_NUM_DDR_CONTROLLERS 1 877 #define CONFIG_PME_PLAT_CLK_DIV 1 878 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 879 #define CONFIG_SYS_FM1_CLK 0 880 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 881 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 882 #define CONFIG_SYS_FMAN_V3 883 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 884 #define CONFIG_SYS_FSL_TBCLK_DIV 16 885 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 886 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 887 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 888 #define CONFIG_SYS_FSL_ERRATUM_A007212 889 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 890 #define CONFIG_SYS_FSL_SFP_VER_3_0 891 #define CONFIG_SYS_FSL_ISBC_VER 2 892 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 893 #define CONFIG_SYS_FSL_ERRATUM_A006261 894 #define CONFIG_SYS_FSL_ERRATUM_A006593 895 #define CONFIG_SYS_FSL_ERRATUM_A007186 896 #define CONFIG_SYS_FSL_ERRATUM_A006379 897 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 898 #define CONFIG_SYS_FSL_SFP_VER_3_0 899 900 901 #elif defined(CONFIG_PPC_C29X) 902 #define CONFIG_MAX_CPUS 1 903 #define CONFIG_FSL_SDHC_V2_3 904 #define CONFIG_SYS_FSL_NUM_LAWS 12 905 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 906 #define CONFIG_TSECV2_1 907 #define CONFIG_SYS_FSL_SEC_COMPAT 6 908 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 909 #define CONFIG_NUM_DDR_CONTROLLERS 1 910 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 911 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 912 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 913 #define CONFIG_SYS_FSL_ERRATUM_A005125 914 915 #elif defined(CONFIG_QEMU_E500) 916 #define CONFIG_MAX_CPUS 1 917 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 918 919 #else 920 #error Processor type not defined for this platform 921 #endif 922 923 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 924 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 925 #endif 926 927 #ifdef CONFIG_E6500 928 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 929 #else 930 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 931 #endif 932 933 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 934 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 935 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 936 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 937 #define CONFIG_SYS_FSL_DDRC_GEN3 938 #endif 939 940 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 941