1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #include <fsl_ddrc_version.h> 23 #define CONFIG_SYS_FSL_DDR_BE 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 #define CONFIG_SYS_FSL_SEC_BE 28 #define CONFIG_SYS_FSL_SFP_BE 29 #define CONFIG_SYS_FSL_SEC_MON_BE 30 31 /* Number of TLB CAM entries we have on FSL Book-E chips */ 32 #if defined(CONFIG_E500MC) 33 #define CONFIG_SYS_NUM_TLBCAMS 64 34 #elif defined(CONFIG_E500) 35 #define CONFIG_SYS_NUM_TLBCAMS 16 36 #endif 37 38 #if defined(CONFIG_MPC8536) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 12 41 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 42 #define CONFIG_SYS_FSL_SEC_COMPAT 2 43 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 44 #define CONFIG_SYS_FSL_ERRATUM_A004508 45 #define CONFIG_SYS_FSL_ERRATUM_A005125 46 47 #elif defined(CONFIG_MPC8540) 48 #define CONFIG_MAX_CPUS 1 49 #define CONFIG_SYS_FSL_NUM_LAWS 8 50 #define CONFIG_SYS_FSL_DDRC_GEN1 51 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 52 53 #elif defined(CONFIG_MPC8541) 54 #define CONFIG_MAX_CPUS 1 55 #define CONFIG_SYS_FSL_NUM_LAWS 8 56 #define CONFIG_SYS_FSL_DDRC_GEN1 57 #define CONFIG_SYS_FSL_SEC_COMPAT 2 58 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 59 60 #elif defined(CONFIG_MPC8544) 61 #define CONFIG_MAX_CPUS 1 62 #define CONFIG_SYS_FSL_NUM_LAWS 10 63 #define CONFIG_SYS_FSL_DDRC_GEN2 64 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 65 #define CONFIG_SYS_FSL_SEC_COMPAT 2 66 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 67 #define CONFIG_SYS_FSL_ERRATUM_A005125 68 69 #elif defined(CONFIG_MPC8548) 70 #define CONFIG_MAX_CPUS 1 71 #define CONFIG_SYS_FSL_NUM_LAWS 10 72 #define CONFIG_SYS_FSL_DDRC_GEN2 73 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 74 #define CONFIG_SYS_FSL_SEC_COMPAT 2 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 76 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 77 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 78 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 79 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 80 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 81 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 82 #define CONFIG_SYS_FSL_RMU 83 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 84 #define CONFIG_SYS_FSL_ERRATUM_A005125 85 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 86 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 87 88 #elif defined(CONFIG_MPC8555) 89 #define CONFIG_MAX_CPUS 1 90 #define CONFIG_SYS_FSL_NUM_LAWS 8 91 #define CONFIG_SYS_FSL_DDRC_GEN1 92 #define CONFIG_SYS_FSL_SEC_COMPAT 2 93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 94 95 #elif defined(CONFIG_MPC8560) 96 #define CONFIG_MAX_CPUS 1 97 #define CONFIG_SYS_FSL_NUM_LAWS 8 98 #define CONFIG_SYS_FSL_DDRC_GEN1 99 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 100 101 #elif defined(CONFIG_MPC8568) 102 #define CONFIG_MAX_CPUS 1 103 #define CONFIG_SYS_FSL_NUM_LAWS 10 104 #define CONFIG_SYS_FSL_DDRC_GEN2 105 #define CONFIG_SYS_FSL_SEC_COMPAT 2 106 #define QE_MURAM_SIZE 0x10000UL 107 #define MAX_QE_RISC 2 108 #define QE_NUM_OF_SNUM 28 109 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 110 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 111 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 112 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 113 #define CONFIG_SYS_FSL_RMU 114 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 115 116 #elif defined(CONFIG_MPC8569) 117 #define CONFIG_MAX_CPUS 1 118 #define CONFIG_SYS_FSL_NUM_LAWS 10 119 #define CONFIG_SYS_FSL_SEC_COMPAT 2 120 #define QE_MURAM_SIZE 0x20000UL 121 #define MAX_QE_RISC 4 122 #define QE_NUM_OF_SNUM 46 123 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 124 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 125 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 126 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 127 #define CONFIG_SYS_FSL_RMU 128 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 129 #define CONFIG_SYS_FSL_ERRATUM_A004508 130 #define CONFIG_SYS_FSL_ERRATUM_A005125 131 132 #elif defined(CONFIG_MPC8572) 133 #define CONFIG_MAX_CPUS 2 134 #define CONFIG_SYS_FSL_NUM_LAWS 12 135 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 136 #define CONFIG_SYS_FSL_SEC_COMPAT 2 137 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 138 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 139 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 140 #define CONFIG_SYS_FSL_ERRATUM_A004508 141 #define CONFIG_SYS_FSL_ERRATUM_A005125 142 143 #elif defined(CONFIG_P1010) 144 #define CONFIG_MAX_CPUS 1 145 #define CONFIG_FSL_SDHC_V2_3 146 #define CONFIG_SYS_FSL_NUM_LAWS 12 147 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 148 #define CONFIG_TSECV2 149 #define CONFIG_SYS_FSL_SEC_COMPAT 4 150 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 151 #define CONFIG_NUM_DDR_CONTROLLERS 1 152 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 153 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 154 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 155 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 156 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 157 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 158 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 159 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 160 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 161 #define CONFIG_SYS_FSL_ERRATUM_A005125 162 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 163 #define CONFIG_SYS_FSL_ERRATUM_A004508 164 #define CONFIG_SYS_FSL_ERRATUM_A007075 165 #define CONFIG_SYS_FSL_ERRATUM_A006261 166 #define CONFIG_SYS_FSL_ERRATUM_A004477 167 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 168 #define CONFIG_ESDHC_HC_BLK_ADDR 169 170 /* P1011 is single core version of P1020 */ 171 #elif defined(CONFIG_P1011) 172 #define CONFIG_MAX_CPUS 1 173 #define CONFIG_SYS_FSL_NUM_LAWS 12 174 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 175 #define CONFIG_TSECV2 176 #define CONFIG_FSL_PCIE_DISABLE_ASPM 177 #define CONFIG_SYS_FSL_SEC_COMPAT 2 178 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 179 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 180 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 181 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 182 #define CONFIG_SYS_FSL_ERRATUM_A004508 183 #define CONFIG_SYS_FSL_ERRATUM_A005125 184 185 /* P1012 is single core version of P1021 */ 186 #elif defined(CONFIG_P1012) 187 #define CONFIG_MAX_CPUS 1 188 #define CONFIG_SYS_FSL_NUM_LAWS 12 189 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 190 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 191 #define CONFIG_TSECV2 192 #define CONFIG_FSL_PCIE_DISABLE_ASPM 193 #define CONFIG_SYS_FSL_SEC_COMPAT 2 194 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 195 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 196 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 197 #define QE_MURAM_SIZE 0x6000UL 198 #define MAX_QE_RISC 1 199 #define QE_NUM_OF_SNUM 28 200 #define CONFIG_SYS_FSL_ERRATUM_A004508 201 #define CONFIG_SYS_FSL_ERRATUM_A005125 202 203 /* P1013 is single core version of P1022 */ 204 #elif defined(CONFIG_P1013) 205 #define CONFIG_MAX_CPUS 1 206 #define CONFIG_SYS_FSL_NUM_LAWS 12 207 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 208 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 209 #define CONFIG_TSECV2 210 #define CONFIG_SYS_FSL_SEC_COMPAT 2 211 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 212 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 213 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 214 #define CONFIG_FSL_SATA_ERRATUM_A001 215 #define CONFIG_SYS_FSL_ERRATUM_A004508 216 #define CONFIG_SYS_FSL_ERRATUM_A005125 217 218 #elif defined(CONFIG_P1014) 219 #define CONFIG_MAX_CPUS 1 220 #define CONFIG_FSL_SDHC_V2_3 221 #define CONFIG_SYS_FSL_NUM_LAWS 12 222 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 223 #define CONFIG_TSECV2 224 #define CONFIG_SYS_FSL_SEC_COMPAT 4 225 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 226 #define CONFIG_NUM_DDR_CONTROLLERS 1 227 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 228 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 229 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 230 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 231 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 232 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 233 #define CONFIG_SYS_FSL_ERRATUM_A004508 234 235 /* P1017 is single core version of P1023 */ 236 #elif defined(CONFIG_P1017) 237 #define CONFIG_MAX_CPUS 1 238 #define CONFIG_SYS_FSL_NUM_LAWS 12 239 #define CONFIG_SYS_FSL_SEC_COMPAT 4 240 #define CONFIG_SYS_NUM_FMAN 1 241 #define CONFIG_SYS_NUM_FM1_DTSEC 2 242 #define CONFIG_NUM_DDR_CONTROLLERS 1 243 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 244 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 245 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 246 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 247 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 248 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 249 #define CONFIG_SYS_FSL_ERRATUM_A004508 250 #define CONFIG_SYS_FSL_ERRATUM_A005125 251 252 #elif defined(CONFIG_P1020) 253 #define CONFIG_MAX_CPUS 2 254 #define CONFIG_SYS_FSL_NUM_LAWS 12 255 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 256 #define CONFIG_TSECV2 257 #define CONFIG_FSL_PCIE_DISABLE_ASPM 258 #define CONFIG_SYS_FSL_SEC_COMPAT 2 259 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 260 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 261 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 262 #define CONFIG_SYS_FSL_ERRATUM_A004508 263 #define CONFIG_SYS_FSL_ERRATUM_A005125 264 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 265 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 266 #endif 267 268 #elif defined(CONFIG_P1021) 269 #define CONFIG_MAX_CPUS 2 270 #define CONFIG_SYS_FSL_NUM_LAWS 12 271 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 272 #define CONFIG_TSECV2 273 #define CONFIG_FSL_PCIE_DISABLE_ASPM 274 #define CONFIG_SYS_FSL_SEC_COMPAT 2 275 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 276 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 277 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 278 #define QE_MURAM_SIZE 0x6000UL 279 #define MAX_QE_RISC 1 280 #define QE_NUM_OF_SNUM 28 281 #define CONFIG_SYS_FSL_ERRATUM_A004508 282 #define CONFIG_SYS_FSL_ERRATUM_A005125 283 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 284 285 #elif defined(CONFIG_P1022) 286 #define CONFIG_MAX_CPUS 2 287 #define CONFIG_SYS_FSL_NUM_LAWS 12 288 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 289 #define CONFIG_TSECV2 290 #define CONFIG_SYS_FSL_SEC_COMPAT 2 291 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 292 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 293 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 294 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 295 #define CONFIG_FSL_SATA_ERRATUM_A001 296 #define CONFIG_SYS_FSL_ERRATUM_A004508 297 #define CONFIG_SYS_FSL_ERRATUM_A005125 298 #define CONFIG_SYS_FSL_ERRATUM_A004477 299 300 #elif defined(CONFIG_P1023) 301 #define CONFIG_MAX_CPUS 2 302 #define CONFIG_SYS_FSL_NUM_LAWS 12 303 #define CONFIG_SYS_FSL_SEC_COMPAT 4 304 #define CONFIG_SYS_NUM_FMAN 1 305 #define CONFIG_SYS_NUM_FM1_DTSEC 2 306 #define CONFIG_NUM_DDR_CONTROLLERS 1 307 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 308 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 309 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 310 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 311 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 312 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 313 #define CONFIG_SYS_FSL_ERRATUM_A004508 314 #define CONFIG_SYS_FSL_ERRATUM_A005125 315 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 316 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 317 318 /* P1024 is lower end variant of P1020 */ 319 #elif defined(CONFIG_P1024) 320 #define CONFIG_MAX_CPUS 2 321 #define CONFIG_SYS_FSL_NUM_LAWS 12 322 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 323 #define CONFIG_TSECV2 324 #define CONFIG_FSL_PCIE_DISABLE_ASPM 325 #define CONFIG_SYS_FSL_SEC_COMPAT 2 326 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 327 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 328 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 329 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 330 #define CONFIG_SYS_FSL_ERRATUM_A004508 331 #define CONFIG_SYS_FSL_ERRATUM_A005125 332 333 /* P1025 is lower end variant of P1021 */ 334 #elif defined(CONFIG_P1025) 335 #define CONFIG_MAX_CPUS 2 336 #define CONFIG_SYS_FSL_NUM_LAWS 12 337 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 338 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 339 #define CONFIG_TSECV2 340 #define CONFIG_FSL_PCIE_DISABLE_ASPM 341 #define CONFIG_SYS_FSL_SEC_COMPAT 2 342 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 343 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 344 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 345 #define QE_MURAM_SIZE 0x6000UL 346 #define MAX_QE_RISC 1 347 #define QE_NUM_OF_SNUM 28 348 #define CONFIG_SYS_FSL_ERRATUM_A004508 349 #define CONFIG_SYS_FSL_ERRATUM_A005125 350 351 /* P2010 is single core version of P2020 */ 352 #elif defined(CONFIG_P2010) 353 #define CONFIG_MAX_CPUS 1 354 #define CONFIG_SYS_FSL_NUM_LAWS 12 355 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 356 #define CONFIG_SYS_FSL_SEC_COMPAT 2 357 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 358 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 359 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 360 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 361 #define CONFIG_SYS_FSL_ERRATUM_A004508 362 #define CONFIG_SYS_FSL_ERRATUM_A005125 363 364 #elif defined(CONFIG_P2020) 365 #define CONFIG_MAX_CPUS 2 366 #define CONFIG_SYS_FSL_NUM_LAWS 12 367 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 368 #define CONFIG_SYS_FSL_SEC_COMPAT 2 369 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 370 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 371 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 372 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 373 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 374 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 375 #define CONFIG_SYS_FSL_RMU 376 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 377 #define CONFIG_SYS_FSL_ERRATUM_A004508 378 #define CONFIG_SYS_FSL_ERRATUM_A005125 379 #define CONFIG_SYS_FSL_ERRATUM_A004477 380 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 381 382 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 383 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 384 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 385 #define CONFIG_MAX_CPUS 4 386 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 387 #define CONFIG_SYS_FSL_NUM_LAWS 32 388 #define CONFIG_SYS_FSL_SEC_COMPAT 4 389 #define CONFIG_SYS_NUM_FMAN 1 390 #define CONFIG_SYS_NUM_FM1_DTSEC 5 391 #define CONFIG_SYS_NUM_FM1_10GEC 1 392 #define CONFIG_NUM_DDR_CONTROLLERS 1 393 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 394 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 395 #define CONFIG_SYS_FSL_TBCLK_DIV 32 396 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 397 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 398 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 399 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 400 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 401 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 402 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 403 #define CONFIG_SYS_FSL_ERRATUM_USB14 404 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 405 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 406 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 407 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 408 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 409 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 410 #define CONFIG_SYS_FSL_ERRATUM_A004510 411 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 412 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 413 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 414 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 415 #define CONFIG_SYS_FSL_ERRATUM_A004849 416 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 417 #define CONFIG_SYS_FSL_ERRATUM_A006261 418 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 419 420 #elif defined(CONFIG_PPC_P3041) 421 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 422 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 423 #define CONFIG_MAX_CPUS 4 424 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 425 #define CONFIG_SYS_FSL_NUM_LAWS 32 426 #define CONFIG_SYS_FSL_SEC_COMPAT 4 427 #define CONFIG_SYS_NUM_FMAN 1 428 #define CONFIG_SYS_NUM_FM1_DTSEC 5 429 #define CONFIG_SYS_NUM_FM1_10GEC 1 430 #define CONFIG_NUM_DDR_CONTROLLERS 1 431 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 432 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 433 #define CONFIG_SYS_FSL_TBCLK_DIV 32 434 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 435 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 436 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 437 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 438 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 439 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 440 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 441 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 442 #define CONFIG_SYS_FSL_ERRATUM_USB14 443 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 444 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 445 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 446 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 447 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 448 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 449 #define CONFIG_SYS_FSL_ERRATUM_A004510 450 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 451 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 452 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 453 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 454 #define CONFIG_SYS_FSL_ERRATUM_A004849 455 #define CONFIG_SYS_FSL_ERRATUM_A005812 456 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 457 #define CONFIG_SYS_FSL_ERRATUM_A006261 458 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 459 460 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 461 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 462 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 463 #define CONFIG_MAX_CPUS 8 464 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 465 #define CONFIG_SYS_FSL_NUM_LAWS 32 466 #define CONFIG_SYS_FSL_SEC_COMPAT 4 467 #define CONFIG_SYS_NUM_FMAN 2 468 #define CONFIG_SYS_NUM_FM1_DTSEC 4 469 #define CONFIG_SYS_NUM_FM2_DTSEC 4 470 #define CONFIG_SYS_NUM_FM1_10GEC 1 471 #define CONFIG_SYS_NUM_FM2_10GEC 1 472 #define CONFIG_NUM_DDR_CONTROLLERS 2 473 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 474 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 475 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 476 #define CONFIG_SYS_FSL_TBCLK_DIV 16 477 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 478 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 479 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 480 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 481 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 482 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 483 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 484 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 485 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 486 #define CONFIG_SYS_P4080_ERRATUM_CPU22 487 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 488 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 489 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 490 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 491 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 492 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 493 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 494 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 495 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 496 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 497 #define CONFIG_SYS_FSL_RMU 498 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 499 #define CONFIG_SYS_FSL_ERRATUM_A004510 500 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 501 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 502 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 503 #define CONFIG_SYS_FSL_ERRATUM_A004849 504 #define CONFIG_SYS_FSL_ERRATUM_A004580 505 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 506 #define CONFIG_SYS_FSL_ERRATUM_A005812 507 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 508 #define CONFIG_SYS_FSL_ERRATUM_A007075 509 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 510 511 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 512 #define CONFIG_SYS_PPC64 /* 64-bit core */ 513 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 514 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 515 #define CONFIG_MAX_CPUS 2 516 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 517 #define CONFIG_SYS_FSL_NUM_LAWS 32 518 #define CONFIG_SYS_FSL_SEC_COMPAT 4 519 #define CONFIG_SYS_NUM_FMAN 1 520 #define CONFIG_SYS_NUM_FM1_DTSEC 5 521 #define CONFIG_SYS_NUM_FM1_10GEC 1 522 #define CONFIG_NUM_DDR_CONTROLLERS 2 523 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 524 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 525 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 526 #define CONFIG_SYS_FSL_TBCLK_DIV 32 527 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 528 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 529 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 530 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 531 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 532 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 533 #define CONFIG_SYS_FSL_ERRATUM_USB14 534 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 535 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 536 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 537 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 538 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 539 #define CONFIG_SYS_FSL_ERRATUM_A004510 540 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 541 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 542 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 543 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 544 #define CONFIG_SYS_FSL_ERRATUM_A006261 545 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 546 547 #elif defined(CONFIG_PPC_P5040) 548 #define CONFIG_SYS_PPC64 549 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 550 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 551 #define CONFIG_MAX_CPUS 4 552 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 553 #define CONFIG_SYS_FSL_NUM_LAWS 32 554 #define CONFIG_SYS_FSL_SEC_COMPAT 4 555 #define CONFIG_SYS_NUM_FMAN 2 556 #define CONFIG_SYS_NUM_FM1_DTSEC 5 557 #define CONFIG_SYS_NUM_FM1_10GEC 1 558 #define CONFIG_SYS_NUM_FM2_DTSEC 5 559 #define CONFIG_SYS_NUM_FM2_10GEC 1 560 #define CONFIG_NUM_DDR_CONTROLLERS 2 561 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 562 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 563 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 564 #define CONFIG_SYS_FSL_TBCLK_DIV 16 565 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 566 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 567 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 568 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 569 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 570 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 571 #define CONFIG_SYS_FSL_ERRATUM_USB14 572 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 573 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 574 #define CONFIG_SYS_FSL_ERRATUM_A004699 575 #define CONFIG_SYS_FSL_ERRATUM_A004510 576 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 577 #define CONFIG_SYS_FSL_ERRATUM_A006261 578 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 579 #define CONFIG_SYS_FSL_ERRATUM_A005812 580 581 #elif defined(CONFIG_BSC9131) 582 #define CONFIG_MAX_CPUS 1 583 #define CONFIG_FSL_SDHC_V2_3 584 #define CONFIG_SYS_FSL_NUM_LAWS 12 585 #define CONFIG_TSECV2 586 #define CONFIG_SYS_FSL_SEC_COMPAT 4 587 #define CONFIG_NUM_DDR_CONTROLLERS 1 588 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 589 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 590 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 591 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 592 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 593 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 594 #define CONFIG_NAND_FSL_IFC 595 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 596 #define CONFIG_SYS_FSL_ERRATUM_A005125 597 #define CONFIG_SYS_FSL_ERRATUM_A004477 598 #define CONFIG_ESDHC_HC_BLK_ADDR 599 600 #elif defined(CONFIG_BSC9132) 601 #define CONFIG_MAX_CPUS 2 602 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 603 #define CONFIG_FSL_SDHC_V2_3 604 #define CONFIG_SYS_FSL_NUM_LAWS 12 605 #define CONFIG_TSECV2 606 #define CONFIG_SYS_FSL_SEC_COMPAT 4 607 #define CONFIG_NUM_DDR_CONTROLLERS 2 608 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 609 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 610 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 611 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 612 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 613 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 614 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 615 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 616 #define CONFIG_NAND_FSL_IFC 617 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 618 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 619 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 620 #define CONFIG_SYS_FSL_ERRATUM_A005125 621 #define CONFIG_SYS_FSL_ERRATUM_A005434 622 #define CONFIG_SYS_FSL_ERRATUM_A004477 623 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 624 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 625 #define CONFIG_ESDHC_HC_BLK_ADDR 626 627 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 628 defined(CONFIG_PPC_T4080) 629 #define CONFIG_E6500 630 #define CONFIG_SYS_PPC64 /* 64-bit core */ 631 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 632 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 633 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 634 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 635 #ifdef CONFIG_PPC_T4240 636 #define CONFIG_MAX_CPUS 12 637 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 638 #define CONFIG_SYS_NUM_FM1_DTSEC 8 639 #define CONFIG_SYS_NUM_FM1_10GEC 2 640 #define CONFIG_SYS_NUM_FM2_DTSEC 8 641 #define CONFIG_SYS_NUM_FM2_10GEC 2 642 #define CONFIG_NUM_DDR_CONTROLLERS 3 643 #else 644 #define CONFIG_SYS_NUM_FM1_DTSEC 6 645 #define CONFIG_SYS_NUM_FM1_10GEC 1 646 #define CONFIG_SYS_NUM_FM2_DTSEC 8 647 #define CONFIG_SYS_NUM_FM2_10GEC 1 648 #define CONFIG_NUM_DDR_CONTROLLERS 2 649 #if defined(CONFIG_PPC_T4160) 650 #define CONFIG_MAX_CPUS 8 651 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 652 #elif defined(CONFIG_PPC_T4080) 653 #define CONFIG_MAX_CPUS 4 654 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } 655 #endif 656 #endif 657 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 658 #define CONFIG_SYS_FSL_NUM_LAWS 32 659 #define CONFIG_SYS_FSL_SRDS_1 660 #define CONFIG_SYS_FSL_SRDS_2 661 #define CONFIG_SYS_FSL_SRDS_3 662 #define CONFIG_SYS_FSL_SRDS_4 663 #define CONFIG_SYS_FSL_SEC_COMPAT 4 664 #define CONFIG_SYS_NUM_FMAN 2 665 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 666 #define CONFIG_SYS_PME_CLK 0 667 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 668 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 669 #define CONFIG_SYS_FMAN_V3 670 #define CONFIG_SYS_FM1_CLK 3 671 #define CONFIG_SYS_FM2_CLK 3 672 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 673 #define CONFIG_SYS_FSL_TBCLK_DIV 16 674 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 675 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 676 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 677 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 678 #define CONFIG_SYS_FSL_SRIO_LIODN 679 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 680 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 681 #define CONFIG_SYS_FSL_ERRATUM_A004468 682 #define CONFIG_SYS_FSL_ERRATUM_A_004934 683 #define CONFIG_SYS_FSL_ERRATUM_A005871 684 #define CONFIG_SYS_FSL_ERRATUM_A006261 685 #define CONFIG_SYS_FSL_ERRATUM_A006379 686 #define CONFIG_SYS_FSL_ERRATUM_A007186 687 #define CONFIG_SYS_FSL_ERRATUM_A006593 688 #define CONFIG_SYS_FSL_ERRATUM_A007798 689 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 690 #define CONFIG_SYS_FSL_SFP_VER_3_0 691 #define CONFIG_SYS_FSL_PCI_VER_3_X 692 693 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 694 #define CONFIG_E6500 695 #define CONFIG_SYS_PPC64 /* 64-bit core */ 696 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 697 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 698 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 699 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 700 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 701 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 702 #define CONFIG_SYS_FSL_NUM_LAWS 32 703 #define CONFIG_SYS_FSL_SRDS_1 704 #define CONFIG_SYS_FSL_SRDS_2 705 #define CONFIG_SYS_MAPLE 706 #define CONFIG_SYS_CPRI 707 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 708 #define CONFIG_SYS_FSL_SEC_COMPAT 4 709 #define CONFIG_SYS_NUM_FMAN 1 710 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 711 #define CONFIG_SYS_FM1_CLK 0 712 #define CONFIG_SYS_CPRI_CLK 3 713 #define CONFIG_SYS_ULB_CLK 4 714 #define CONFIG_SYS_ETVPE_CLK 1 715 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 716 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 717 #define CONFIG_SYS_FMAN_V3 718 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 719 #define CONFIG_SYS_FSL_TBCLK_DIV 16 720 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 721 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 722 #define CONFIG_SYS_FSL_ERRATUM_A_004934 723 #define CONFIG_SYS_FSL_ERRATUM_A005871 724 #define CONFIG_SYS_FSL_ERRATUM_A006379 725 #define CONFIG_SYS_FSL_ERRATUM_A007186 726 #define CONFIG_SYS_FSL_ERRATUM_A006593 727 #define CONFIG_SYS_FSL_ERRATUM_A007075 728 #define CONFIG_SYS_FSL_ERRATUM_A006475 729 #define CONFIG_SYS_FSL_ERRATUM_A006384 730 #define CONFIG_SYS_FSL_ERRATUM_A007212 731 #define CONFIG_SYS_FSL_ERRATUM_A004477 732 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 733 #define CONFIG_SYS_FSL_SFP_VER_3_0 734 735 #ifdef CONFIG_PPC_B4860 736 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 737 #define CONFIG_MAX_CPUS 4 738 #define CONFIG_MAX_DSP_CPUS 12 739 #define CONFIG_NUM_DSP_CPUS 6 740 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 741 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 742 #define CONFIG_SYS_NUM_FM1_DTSEC 6 743 #define CONFIG_SYS_NUM_FM1_10GEC 2 744 #define CONFIG_NUM_DDR_CONTROLLERS 2 745 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 746 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 747 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 748 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 749 #define CONFIG_SYS_FSL_SRIO_LIODN 750 #else 751 #define CONFIG_MAX_CPUS 2 752 #define CONFIG_MAX_DSP_CPUS 2 753 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 754 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 755 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 756 #define CONFIG_SYS_NUM_FM1_DTSEC 4 757 #define CONFIG_SYS_NUM_FM1_10GEC 0 758 #define CONFIG_NUM_DDR_CONTROLLERS 1 759 #endif 760 761 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 762 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 763 #define CONFIG_E5500 764 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 765 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 766 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 767 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 768 #ifdef CONFIG_SYS_FSL_DDR4 769 #define CONFIG_SYS_FSL_DDRC_GEN4 770 #endif 771 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 772 #define CONFIG_MAX_CPUS 4 773 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 774 #define CONFIG_MAX_CPUS 2 775 #endif 776 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 777 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 778 #define CONFIG_SYS_FSL_NUM_LAWS 16 779 #define CONFIG_SYS_FSL_SRDS_1 780 #define CONFIG_SYS_FSL_SEC_COMPAT 5 781 #define CONFIG_SYS_NUM_FMAN 1 782 #define CONFIG_SYS_NUM_FM1_DTSEC 5 783 #define CONFIG_NUM_DDR_CONTROLLERS 1 784 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 785 #define CONFIG_PME_PLAT_CLK_DIV 2 786 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 787 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 788 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 789 #define CONFIG_SYS_FSL_ERRATUM_A008044 790 #define CONFIG_SYS_FMAN_V3 791 #define CONFIG_FM_PLAT_CLK_DIV 1 792 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 793 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 794 per rcw field value */ 795 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 796 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 797 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 798 #define CONFIG_SYS_FSL_TBCLK_DIV 16 799 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 800 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 801 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 802 #define CONFIG_SYS_FSL_ERRATUM_A006261 803 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 804 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 805 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 806 #define QE_MURAM_SIZE 0x6000UL 807 #define MAX_QE_RISC 1 808 #define QE_NUM_OF_SNUM 28 809 810 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ 811 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 812 #define CONFIG_E5500 813 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 814 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 815 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 816 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 817 #define CONFIG_SYS_FMAN_V3 818 #ifdef CONFIG_SYS_FSL_DDR4 819 #define CONFIG_SYS_FSL_DDRC_GEN4 820 #endif 821 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) 822 #define CONFIG_MAX_CPUS 2 823 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 824 #define CONFIG_MAX_CPUS 1 825 #endif 826 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 827 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 828 #define CONFIG_SYS_FSL_NUM_LAWS 16 829 #define CONFIG_SYS_FSL_SRDS_1 830 #define CONFIG_SYS_FSL_SEC_COMPAT 5 831 #define CONFIG_SYS_NUM_FMAN 1 832 #define CONFIG_SYS_NUM_FM1_DTSEC 4 833 #define CONFIG_SYS_NUM_FM1_10GEC 1 834 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 835 #define CONFIG_NUM_DDR_CONTROLLERS 1 836 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 837 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 838 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 839 #define CONFIG_SYS_FM1_CLK 0 840 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 841 per rcw field value */ 842 #define CONFIG_QBMAN_CLK_DIV 1 843 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 844 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 845 #define CONFIG_SYS_FSL_TBCLK_DIV 16 846 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 847 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 848 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 849 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 850 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 851 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 852 #define QE_MURAM_SIZE 0x6000UL 853 #define MAX_QE_RISC 1 854 #define QE_NUM_OF_SNUM 28 855 #define CONFIG_SYS_FSL_SFP_VER_3_0 856 857 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 858 #define CONFIG_E6500 859 #define CONFIG_SYS_PPC64 /* 64-bit core */ 860 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 861 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 862 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 863 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 864 #define CONFIG_SYS_FSL_QMAN_V3 865 #define CONFIG_MAX_CPUS 4 866 #define CONFIG_SYS_FSL_NUM_LAWS 32 867 #define CONFIG_SYS_FSL_SEC_COMPAT 4 868 #define CONFIG_SYS_NUM_FMAN 1 869 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 870 #define CONFIG_SYS_FSL_SRDS_1 871 #define CONFIG_SYS_FSL_PCI_VER_3_X 872 #if defined(CONFIG_PPC_T2080) 873 #define CONFIG_SYS_NUM_FM1_DTSEC 8 874 #define CONFIG_SYS_NUM_FM1_10GEC 4 875 #define CONFIG_SYS_FSL_SRDS_2 876 #define CONFIG_SYS_FSL_SRIO_LIODN 877 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 878 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 879 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 880 #elif defined(CONFIG_PPC_T2081) 881 #define CONFIG_SYS_NUM_FM1_DTSEC 6 882 #define CONFIG_SYS_NUM_FM1_10GEC 2 883 #endif 884 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 885 #define CONFIG_NUM_DDR_CONTROLLERS 1 886 #define CONFIG_PME_PLAT_CLK_DIV 1 887 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 888 #define CONFIG_SYS_FM1_CLK 0 889 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 890 per rcw field value */ 891 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 892 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 893 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 894 #define CONFIG_SYS_FMAN_V3 895 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 896 #define CONFIG_SYS_FSL_TBCLK_DIV 16 897 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 898 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 899 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 900 #define CONFIG_SYS_FSL_ERRATUM_A007212 901 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 902 #define CONFIG_SYS_FSL_SFP_VER_3_0 903 #define CONFIG_SYS_FSL_ISBC_VER 2 904 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 905 #define CONFIG_SYS_FSL_ERRATUM_A006261 906 #define CONFIG_SYS_FSL_ERRATUM_A006593 907 #define CONFIG_SYS_FSL_ERRATUM_A007186 908 #define CONFIG_SYS_FSL_ERRATUM_A006379 909 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 910 #define CONFIG_SYS_FSL_SFP_VER_3_0 911 912 913 #elif defined(CONFIG_PPC_C29X) 914 #define CONFIG_MAX_CPUS 1 915 #define CONFIG_FSL_SDHC_V2_3 916 #define CONFIG_SYS_FSL_NUM_LAWS 12 917 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 918 #define CONFIG_TSECV2_1 919 #define CONFIG_SYS_FSL_SEC_COMPAT 6 920 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 921 #define CONFIG_NUM_DDR_CONTROLLERS 1 922 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 923 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 924 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 925 #define CONFIG_SYS_FSL_ERRATUM_A005125 926 927 #elif defined(CONFIG_QEMU_E500) 928 #define CONFIG_MAX_CPUS 1 929 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 930 931 #else 932 #error Processor type not defined for this platform 933 #endif 934 935 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 936 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 937 #endif 938 939 #ifdef CONFIG_E6500 940 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 941 #else 942 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 943 #endif 944 945 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 946 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 947 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 948 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 949 #define CONFIG_SYS_FSL_DDRC_GEN3 950 #endif 951 952 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 953