1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #define FSL_DDR_VER_4_7 47 23 #define FSL_DDR_VER_5_0 50 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 28 /* Number of TLB CAM entries we have on FSL Book-E chips */ 29 #if defined(CONFIG_E500MC) 30 #define CONFIG_SYS_NUM_TLBCAMS 64 31 #elif defined(CONFIG_E500) 32 #define CONFIG_SYS_NUM_TLBCAMS 16 33 #endif 34 35 #if defined(CONFIG_MPC8536) 36 #define CONFIG_MAX_CPUS 1 37 #define CONFIG_SYS_FSL_NUM_LAWS 12 38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 39 #define CONFIG_SYS_FSL_SEC_COMPAT 2 40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 41 #define CONFIG_SYS_FSL_ERRATUM_A005125 42 43 #elif defined(CONFIG_MPC8540) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_FSL_DDRC_GEN1 47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 48 49 #elif defined(CONFIG_MPC8541) 50 #define CONFIG_MAX_CPUS 1 51 #define CONFIG_SYS_FSL_NUM_LAWS 8 52 #define CONFIG_SYS_FSL_DDRC_GEN1 53 #define CONFIG_SYS_FSL_SEC_COMPAT 2 54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 55 56 #elif defined(CONFIG_MPC8544) 57 #define CONFIG_MAX_CPUS 1 58 #define CONFIG_SYS_FSL_NUM_LAWS 10 59 #define CONFIG_SYS_FSL_DDRC_GEN2 60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 61 #define CONFIG_SYS_FSL_SEC_COMPAT 2 62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 63 #define CONFIG_SYS_FSL_ERRATUM_A005125 64 65 #elif defined(CONFIG_MPC8548) 66 #define CONFIG_MAX_CPUS 1 67 #define CONFIG_SYS_FSL_NUM_LAWS 10 68 #define CONFIG_SYS_FSL_DDRC_GEN2 69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 70 #define CONFIG_SYS_FSL_SEC_COMPAT 2 71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 78 #define CONFIG_SYS_FSL_RMU 79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 80 #define CONFIG_SYS_FSL_ERRATUM_A005125 81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 83 84 #elif defined(CONFIG_MPC8555) 85 #define CONFIG_MAX_CPUS 1 86 #define CONFIG_SYS_FSL_NUM_LAWS 8 87 #define CONFIG_SYS_FSL_DDRC_GEN1 88 #define CONFIG_SYS_FSL_SEC_COMPAT 2 89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 90 91 #elif defined(CONFIG_MPC8560) 92 #define CONFIG_MAX_CPUS 1 93 #define CONFIG_SYS_FSL_NUM_LAWS 8 94 #define CONFIG_SYS_FSL_DDRC_GEN1 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 96 97 #elif defined(CONFIG_MPC8568) 98 #define CONFIG_MAX_CPUS 1 99 #define CONFIG_SYS_FSL_NUM_LAWS 10 100 #define CONFIG_SYS_FSL_DDRC_GEN2 101 #define CONFIG_SYS_FSL_SEC_COMPAT 2 102 #define QE_MURAM_SIZE 0x10000UL 103 #define MAX_QE_RISC 2 104 #define QE_NUM_OF_SNUM 28 105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 109 #define CONFIG_SYS_FSL_RMU 110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 111 112 #elif defined(CONFIG_MPC8569) 113 #define CONFIG_MAX_CPUS 1 114 #define CONFIG_SYS_FSL_NUM_LAWS 10 115 #define CONFIG_SYS_FSL_SEC_COMPAT 2 116 #define QE_MURAM_SIZE 0x20000UL 117 #define MAX_QE_RISC 4 118 #define QE_NUM_OF_SNUM 46 119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 123 #define CONFIG_SYS_FSL_RMU 124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 125 #define CONFIG_SYS_FSL_ERRATUM_A005125 126 127 #elif defined(CONFIG_MPC8572) 128 #define CONFIG_MAX_CPUS 2 129 #define CONFIG_SYS_FSL_NUM_LAWS 12 130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 131 #define CONFIG_SYS_FSL_SEC_COMPAT 2 132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 135 #define CONFIG_SYS_FSL_ERRATUM_A005125 136 137 #elif defined(CONFIG_P1010) 138 #define CONFIG_MAX_CPUS 1 139 #define CONFIG_FSL_SDHC_V2_3 140 #define CONFIG_SYS_FSL_NUM_LAWS 12 141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 142 #define CONFIG_TSECV2 143 #define CONFIG_SYS_FSL_SEC_COMPAT 4 144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 145 #define CONFIG_NUM_DDR_CONTROLLERS 1 146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 155 #define CONFIG_SYS_FSL_ERRATUM_A005125 156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 157 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 158 #define CONFIG_ESDHC_HC_BLK_ADDR 159 160 /* P1011 is single core version of P1020 */ 161 #elif defined(CONFIG_P1011) 162 #define CONFIG_MAX_CPUS 1 163 #define CONFIG_SYS_FSL_NUM_LAWS 12 164 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 165 #define CONFIG_TSECV2 166 #define CONFIG_FSL_PCIE_DISABLE_ASPM 167 #define CONFIG_SYS_FSL_SEC_COMPAT 2 168 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 169 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 170 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 171 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 172 #define CONFIG_SYS_FSL_ERRATUM_A005125 173 174 /* P1012 is single core version of P1021 */ 175 #elif defined(CONFIG_P1012) 176 #define CONFIG_MAX_CPUS 1 177 #define CONFIG_SYS_FSL_NUM_LAWS 12 178 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 179 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 180 #define CONFIG_TSECV2 181 #define CONFIG_FSL_PCIE_DISABLE_ASPM 182 #define CONFIG_SYS_FSL_SEC_COMPAT 2 183 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 184 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 185 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 186 #define QE_MURAM_SIZE 0x6000UL 187 #define MAX_QE_RISC 1 188 #define QE_NUM_OF_SNUM 28 189 #define CONFIG_SYS_FSL_ERRATUM_A005125 190 191 /* P1013 is single core version of P1022 */ 192 #elif defined(CONFIG_P1013) 193 #define CONFIG_MAX_CPUS 1 194 #define CONFIG_SYS_FSL_NUM_LAWS 12 195 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 196 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 197 #define CONFIG_TSECV2 198 #define CONFIG_SYS_FSL_SEC_COMPAT 2 199 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 200 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 201 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 202 #define CONFIG_FSL_SATA_ERRATUM_A001 203 #define CONFIG_SYS_FSL_ERRATUM_A005125 204 205 #elif defined(CONFIG_P1014) 206 #define CONFIG_MAX_CPUS 1 207 #define CONFIG_FSL_SDHC_V2_3 208 #define CONFIG_SYS_FSL_NUM_LAWS 12 209 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 210 #define CONFIG_TSECV2 211 #define CONFIG_SYS_FSL_SEC_COMPAT 4 212 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 213 #define CONFIG_NUM_DDR_CONTROLLERS 1 214 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 215 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 216 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 217 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 218 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 219 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 220 221 /* P1017 is single core version of P1023 */ 222 #elif defined(CONFIG_P1017) 223 #define CONFIG_MAX_CPUS 1 224 #define CONFIG_SYS_FSL_NUM_LAWS 12 225 #define CONFIG_SYS_FSL_SEC_COMPAT 4 226 #define CONFIG_SYS_NUM_FMAN 1 227 #define CONFIG_SYS_NUM_FM1_DTSEC 2 228 #define CONFIG_NUM_DDR_CONTROLLERS 1 229 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 230 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 231 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 232 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 233 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 234 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 235 #define CONFIG_SYS_FSL_ERRATUM_A005125 236 237 #elif defined(CONFIG_P1020) 238 #define CONFIG_MAX_CPUS 2 239 #define CONFIG_SYS_FSL_NUM_LAWS 12 240 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 241 #define CONFIG_TSECV2 242 #define CONFIG_FSL_PCIE_DISABLE_ASPM 243 #define CONFIG_SYS_FSL_SEC_COMPAT 2 244 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 245 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 246 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 247 #define CONFIG_SYS_FSL_ERRATUM_A005125 248 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 249 250 #elif defined(CONFIG_P1021) 251 #define CONFIG_MAX_CPUS 2 252 #define CONFIG_SYS_FSL_NUM_LAWS 12 253 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 254 #define CONFIG_TSECV2 255 #define CONFIG_FSL_PCIE_DISABLE_ASPM 256 #define CONFIG_SYS_FSL_SEC_COMPAT 2 257 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 258 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 259 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 260 #define QE_MURAM_SIZE 0x6000UL 261 #define MAX_QE_RISC 1 262 #define QE_NUM_OF_SNUM 28 263 #define CONFIG_SYS_FSL_ERRATUM_A005125 264 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 265 266 #elif defined(CONFIG_P1022) 267 #define CONFIG_MAX_CPUS 2 268 #define CONFIG_SYS_FSL_NUM_LAWS 12 269 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 270 #define CONFIG_TSECV2 271 #define CONFIG_SYS_FSL_SEC_COMPAT 2 272 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 273 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 274 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 275 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 276 #define CONFIG_FSL_SATA_ERRATUM_A001 277 #define CONFIG_SYS_FSL_ERRATUM_A005125 278 279 #elif defined(CONFIG_P1023) 280 #define CONFIG_MAX_CPUS 2 281 #define CONFIG_SYS_FSL_NUM_LAWS 12 282 #define CONFIG_SYS_FSL_SEC_COMPAT 4 283 #define CONFIG_SYS_NUM_FMAN 1 284 #define CONFIG_SYS_NUM_FM1_DTSEC 2 285 #define CONFIG_NUM_DDR_CONTROLLERS 1 286 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 287 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 288 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 289 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 290 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 291 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 292 #define CONFIG_SYS_FSL_ERRATUM_A005125 293 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 294 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 295 296 /* P1024 is lower end variant of P1020 */ 297 #elif defined(CONFIG_P1024) 298 #define CONFIG_MAX_CPUS 2 299 #define CONFIG_SYS_FSL_NUM_LAWS 12 300 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 301 #define CONFIG_TSECV2 302 #define CONFIG_FSL_PCIE_DISABLE_ASPM 303 #define CONFIG_SYS_FSL_SEC_COMPAT 2 304 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 305 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 306 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 307 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 308 #define CONFIG_SYS_FSL_ERRATUM_A005125 309 310 /* P1025 is lower end variant of P1021 */ 311 #elif defined(CONFIG_P1025) 312 #define CONFIG_MAX_CPUS 2 313 #define CONFIG_SYS_FSL_NUM_LAWS 12 314 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 315 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 316 #define CONFIG_TSECV2 317 #define CONFIG_FSL_PCIE_DISABLE_ASPM 318 #define CONFIG_SYS_FSL_SEC_COMPAT 2 319 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 320 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 321 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 322 #define QE_MURAM_SIZE 0x6000UL 323 #define MAX_QE_RISC 1 324 #define QE_NUM_OF_SNUM 28 325 #define CONFIG_SYS_FSL_ERRATUM_A005125 326 327 /* P2010 is single core version of P2020 */ 328 #elif defined(CONFIG_P2010) 329 #define CONFIG_MAX_CPUS 1 330 #define CONFIG_SYS_FSL_NUM_LAWS 12 331 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 332 #define CONFIG_SYS_FSL_SEC_COMPAT 2 333 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 334 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 335 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 336 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 337 #define CONFIG_SYS_FSL_ERRATUM_A005125 338 339 #elif defined(CONFIG_P2020) 340 #define CONFIG_MAX_CPUS 2 341 #define CONFIG_SYS_FSL_NUM_LAWS 12 342 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 343 #define CONFIG_SYS_FSL_SEC_COMPAT 2 344 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 345 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 346 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 347 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 348 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 349 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 350 #define CONFIG_SYS_FSL_RMU 351 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 352 #define CONFIG_SYS_FSL_ERRATUM_A005125 353 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 354 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 355 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 356 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 357 #define CONFIG_MAX_CPUS 4 358 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 359 #define CONFIG_SYS_FSL_NUM_LAWS 32 360 #define CONFIG_SYS_FSL_SEC_COMPAT 4 361 #define CONFIG_SYS_NUM_FMAN 1 362 #define CONFIG_SYS_NUM_FM1_DTSEC 5 363 #define CONFIG_SYS_NUM_FM1_10GEC 1 364 #define CONFIG_NUM_DDR_CONTROLLERS 1 365 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 366 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 367 #define CONFIG_SYS_FSL_TBCLK_DIV 32 368 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 369 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 370 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 371 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 372 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 373 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 374 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 375 #define CONFIG_SYS_FSL_ERRATUM_USB14 376 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 377 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 378 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 379 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 380 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 381 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 382 #define CONFIG_SYS_FSL_ERRATUM_A004510 383 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 384 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 385 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 386 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 387 #define CONFIG_SYS_FSL_ERRATUM_A004849 388 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 389 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 390 391 #elif defined(CONFIG_PPC_P3041) 392 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 393 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 394 #define CONFIG_MAX_CPUS 4 395 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 396 #define CONFIG_SYS_FSL_NUM_LAWS 32 397 #define CONFIG_SYS_FSL_SEC_COMPAT 4 398 #define CONFIG_SYS_NUM_FMAN 1 399 #define CONFIG_SYS_NUM_FM1_DTSEC 5 400 #define CONFIG_SYS_NUM_FM1_10GEC 1 401 #define CONFIG_NUM_DDR_CONTROLLERS 1 402 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 403 #define CONFIG_SYS_FSL_TBCLK_DIV 32 404 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 405 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 406 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 407 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 408 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 409 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 410 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 411 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 412 #define CONFIG_SYS_FSL_ERRATUM_USB14 413 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 414 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 415 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 416 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 417 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 418 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 419 #define CONFIG_SYS_FSL_ERRATUM_A004510 420 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 421 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 422 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 423 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 424 #define CONFIG_SYS_FSL_ERRATUM_A004849 425 #define CONFIG_SYS_FSL_ERRATUM_A005812 426 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 427 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 428 429 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 430 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 431 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 432 #define CONFIG_MAX_CPUS 8 433 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 434 #define CONFIG_SYS_FSL_NUM_LAWS 32 435 #define CONFIG_SYS_FSL_SEC_COMPAT 4 436 #define CONFIG_SYS_NUM_FMAN 2 437 #define CONFIG_SYS_NUM_FM1_DTSEC 4 438 #define CONFIG_SYS_NUM_FM2_DTSEC 4 439 #define CONFIG_SYS_NUM_FM1_10GEC 1 440 #define CONFIG_SYS_NUM_FM2_10GEC 1 441 #define CONFIG_NUM_DDR_CONTROLLERS 2 442 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 443 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 444 #define CONFIG_SYS_FSL_TBCLK_DIV 16 445 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 446 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 447 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 448 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 449 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 450 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 451 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 452 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 453 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 454 #define CONFIG_SYS_P4080_ERRATUM_CPU22 455 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 456 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 457 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 458 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 459 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 460 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 461 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 462 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 463 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 464 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 465 #define CONFIG_SYS_FSL_RMU 466 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 467 #define CONFIG_SYS_FSL_ERRATUM_A004510 468 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 469 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 470 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 471 #define CONFIG_SYS_FSL_ERRATUM_A004849 472 #define CONFIG_SYS_FSL_ERRATUM_A004580 473 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 474 #define CONFIG_SYS_FSL_ERRATUM_A005812 475 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 476 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 477 478 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 479 #define CONFIG_SYS_PPC64 /* 64-bit core */ 480 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 481 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 482 #define CONFIG_MAX_CPUS 2 483 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 484 #define CONFIG_SYS_FSL_NUM_LAWS 32 485 #define CONFIG_SYS_FSL_SEC_COMPAT 4 486 #define CONFIG_SYS_NUM_FMAN 1 487 #define CONFIG_SYS_NUM_FM1_DTSEC 5 488 #define CONFIG_SYS_NUM_FM1_10GEC 1 489 #define CONFIG_NUM_DDR_CONTROLLERS 2 490 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 491 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 492 #define CONFIG_SYS_FSL_TBCLK_DIV 32 493 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 494 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 495 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 496 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 497 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 498 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 499 #define CONFIG_SYS_FSL_ERRATUM_USB14 500 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 501 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 502 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 503 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 504 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 505 #define CONFIG_SYS_FSL_ERRATUM_A004510 506 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 507 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 508 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 509 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 510 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 511 512 #elif defined(CONFIG_PPC_P5040) 513 #define CONFIG_SYS_PPC64 514 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 515 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 516 #define CONFIG_MAX_CPUS 4 517 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 518 #define CONFIG_SYS_FSL_NUM_LAWS 32 519 #define CONFIG_SYS_FSL_SEC_COMPAT 4 520 #define CONFIG_SYS_NUM_FMAN 2 521 #define CONFIG_SYS_NUM_FM1_DTSEC 5 522 #define CONFIG_SYS_NUM_FM1_10GEC 1 523 #define CONFIG_SYS_NUM_FM2_DTSEC 5 524 #define CONFIG_SYS_NUM_FM2_10GEC 1 525 #define CONFIG_NUM_DDR_CONTROLLERS 2 526 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 527 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 528 #define CONFIG_SYS_FSL_TBCLK_DIV 16 529 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 530 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 531 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 532 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 533 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 534 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 535 #define CONFIG_SYS_FSL_ERRATUM_USB14 536 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 537 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 538 #define CONFIG_SYS_FSL_ERRATUM_A004699 539 #define CONFIG_SYS_FSL_ERRATUM_A004510 540 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 541 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 542 #define CONFIG_SYS_FSL_ERRATUM_A005812 543 544 #elif defined(CONFIG_BSC9131) 545 #define CONFIG_MAX_CPUS 1 546 #define CONFIG_FSL_SDHC_V2_3 547 #define CONFIG_SYS_FSL_NUM_LAWS 12 548 #define CONFIG_TSECV2 549 #define CONFIG_SYS_FSL_SEC_COMPAT 4 550 #define CONFIG_NUM_DDR_CONTROLLERS 1 551 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 552 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 553 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 554 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 555 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 556 #define CONFIG_NAND_FSL_IFC 557 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 558 #define CONFIG_SYS_FSL_ERRATUM_A005125 559 #define CONFIG_ESDHC_HC_BLK_ADDR 560 561 #elif defined(CONFIG_BSC9132) 562 #define CONFIG_MAX_CPUS 2 563 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 564 #define CONFIG_FSL_SDHC_V2_3 565 #define CONFIG_SYS_FSL_NUM_LAWS 12 566 #define CONFIG_TSECV2 567 #define CONFIG_SYS_FSL_SEC_COMPAT 4 568 #define CONFIG_NUM_DDR_CONTROLLERS 2 569 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 570 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 571 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 572 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 573 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 574 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 575 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 576 #define CONFIG_NAND_FSL_IFC 577 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 578 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 579 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 580 #define CONFIG_SYS_FSL_ERRATUM_A005125 581 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 582 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 583 #define CONFIG_ESDHC_HC_BLK_ADDR 584 585 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 586 #define CONFIG_E6500 587 #define CONFIG_SYS_PPC64 /* 64-bit core */ 588 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 589 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 590 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 591 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 592 #ifdef CONFIG_PPC_T4240 593 #define CONFIG_MAX_CPUS 12 594 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 595 #define CONFIG_SYS_NUM_FM1_DTSEC 8 596 #define CONFIG_SYS_NUM_FM1_10GEC 2 597 #define CONFIG_SYS_NUM_FM2_DTSEC 8 598 #define CONFIG_SYS_NUM_FM2_10GEC 2 599 #define CONFIG_NUM_DDR_CONTROLLERS 3 600 #else 601 #define CONFIG_MAX_CPUS 8 602 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 603 #define CONFIG_SYS_NUM_FM1_DTSEC 7 604 #define CONFIG_SYS_NUM_FM1_10GEC 1 605 #define CONFIG_SYS_NUM_FM2_DTSEC 7 606 #define CONFIG_SYS_NUM_FM2_10GEC 1 607 #define CONFIG_NUM_DDR_CONTROLLERS 2 608 #endif 609 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 610 #define CONFIG_SYS_FSL_NUM_LAWS 32 611 #define CONFIG_SYS_FSL_SRDS_1 612 #define CONFIG_SYS_FSL_SRDS_2 613 #define CONFIG_SYS_FSL_SRDS_3 614 #define CONFIG_SYS_FSL_SRDS_4 615 #define CONFIG_SYS_FSL_SEC_COMPAT 4 616 #define CONFIG_SYS_NUM_FMAN 2 617 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 618 #define CONFIG_SYS_PME_CLK 0 619 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 620 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 621 #define CONFIG_SYS_FMAN_V3 622 #define CONFIG_SYS_FM1_CLK 3 623 #define CONFIG_SYS_FM2_CLK 3 624 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 625 #define CONFIG_SYS_FSL_TBCLK_DIV 16 626 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 627 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 628 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 629 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 630 #define CONFIG_SYS_FSL_SRIO_LIODN 631 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 632 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 633 #define CONFIG_SYS_FSL_ERRATUM_A004468 634 #define CONFIG_SYS_FSL_ERRATUM_A_004934 635 #define CONFIG_SYS_FSL_ERRATUM_A005871 636 #define CONFIG_SYS_FSL_ERRATUM_A006379 637 #define CONFIG_SYS_FSL_ERRATUM_A006593 638 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 639 #define CONFIG_SYS_FSL_PCI_VER_3_X 640 641 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 642 #define CONFIG_E6500 643 #define CONFIG_SYS_PPC64 /* 64-bit core */ 644 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 645 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 646 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 647 #define CONFIG_SYS_FSL_NUM_LAWS 32 648 #define CONFIG_SYS_FSL_SRDS_1 649 #define CONFIG_SYS_FSL_SRDS_2 650 #define CONFIG_SYS_FSL_SEC_COMPAT 4 651 #define CONFIG_SYS_NUM_FMAN 1 652 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 653 #define CONFIG_SYS_FM1_CLK 0 654 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 655 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 656 #define CONFIG_SYS_FMAN_V3 657 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 658 #define CONFIG_SYS_FSL_TBCLK_DIV 16 659 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 660 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 661 #define CONFIG_SYS_FSL_ERRATUM_A_004934 662 #define CONFIG_SYS_FSL_ERRATUM_A005871 663 #define CONFIG_SYS_FSL_ERRATUM_A006379 664 #define CONFIG_SYS_FSL_ERRATUM_A006593 665 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 666 667 #ifdef CONFIG_PPC_B4860 668 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 669 #define CONFIG_MAX_CPUS 4 670 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 671 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 672 #define CONFIG_SYS_NUM_FM1_DTSEC 6 673 #define CONFIG_SYS_NUM_FM1_10GEC 2 674 #define CONFIG_NUM_DDR_CONTROLLERS 2 675 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 676 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 677 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 678 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 679 #define CONFIG_SYS_FSL_SRIO_LIODN 680 #else 681 #define CONFIG_MAX_CPUS 2 682 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 683 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 684 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 685 #define CONFIG_SYS_NUM_FM1_DTSEC 4 686 #define CONFIG_SYS_NUM_FM1_10GEC 0 687 #define CONFIG_NUM_DDR_CONTROLLERS 1 688 #endif 689 690 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 691 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 692 #define CONFIG_E5500 693 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 694 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 695 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 696 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 697 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 698 #define CONFIG_MAX_CPUS 4 699 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 700 #define CONFIG_MAX_CPUS 2 701 #endif 702 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 703 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 704 #define CONFIG_SYS_SDHC_CLOCK 0 705 #define CONFIG_SYS_FSL_NUM_LAWS 16 706 #define CONFIG_SYS_FSL_SRDS_1 707 #define CONFIG_SYS_FSL_SEC_COMPAT 5 708 #define CONFIG_SYS_NUM_FMAN 1 709 #define CONFIG_SYS_NUM_FM1_DTSEC 5 710 #define CONFIG_NUM_DDR_CONTROLLERS 1 711 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 712 #define CONFIG_PME_PLAT_CLK_DIV 2 713 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 714 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 715 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 716 #define CONFIG_SYS_FMAN_V3 717 #define CONFIG_FM_PLAT_CLK_DIV 1 718 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 719 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 720 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 721 #define CONFIG_SYS_FSL_TBCLK_DIV 16 722 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 723 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 724 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 725 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 726 727 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 728 #define CONFIG_E6500 729 #define CONFIG_SYS_PPC64 /* 64-bit core */ 730 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 731 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 732 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 733 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 734 #define CONFIG_SYS_FSL_QMAN_V3 735 #define CONFIG_MAX_CPUS 4 736 #define CONFIG_SYS_FSL_NUM_LAWS 32 737 #define CONFIG_SYS_FSL_SEC_COMPAT 4 738 #define CONFIG_SYS_NUM_FMAN 1 739 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 740 #define CONFIG_SYS_FSL_SRDS_1 741 #define CONFIG_SYS_FSL_PCI_VER_3_X 742 #if defined(CONFIG_PPC_T2080) 743 #define CONFIG_SYS_NUM_FM1_DTSEC 8 744 #define CONFIG_SYS_NUM_FM1_10GEC 4 745 #define CONFIG_SYS_FSL_SRDS_2 746 #define CONFIG_SYS_FSL_SRIO_LIODN 747 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 748 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 749 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 750 #elif defined(CONFIG_PPC_T2081) 751 #define CONFIG_SYS_NUM_FM1_DTSEC 6 752 #define CONFIG_SYS_NUM_FM1_10GEC 2 753 #endif 754 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 755 #define CONFIG_NUM_DDR_CONTROLLERS 1 756 #define CONFIG_PME_PLAT_CLK_DIV 1 757 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 758 #define CONFIG_SYS_FM1_CLK 0 759 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 760 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 761 #define CONFIG_SYS_FMAN_V3 762 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 763 #define CONFIG_SYS_FSL_TBCLK_DIV 16 764 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 765 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 766 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 767 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 768 #define CONFIG_SYS_FSL_SFP_VER_3_0 769 #define CONFIG_SYS_FSL_ISBC_VER 2 770 771 #elif defined(CONFIG_PPC_C29X) 772 #define CONFIG_MAX_CPUS 1 773 #define CONFIG_FSL_SDHC_V2_3 774 #define CONFIG_SYS_FSL_NUM_LAWS 12 775 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 776 #define CONFIG_TSECV2_1 777 #define CONFIG_SYS_FSL_SEC_COMPAT 6 778 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 779 #define CONFIG_NUM_DDR_CONTROLLERS 1 780 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 781 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 782 #define CONFIG_SYS_FSL_ERRATUM_A005125 783 784 #else 785 #error Processor type not defined for this platform 786 #endif 787 788 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 789 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 790 #endif 791 792 #ifdef CONFIG_E6500 793 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 794 #else 795 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 796 #endif 797 798 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 799 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 800 !defined(CONFIG_SYS_FSL_DDRC_GEN3) 801 #define CONFIG_SYS_FSL_DDRC_GEN3 802 #endif 803 804 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 805