1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #define FSL_DDR_VER_4_7 47 23 24 /* Number of TLB CAM entries we have on FSL Book-E chips */ 25 #if defined(CONFIG_E500MC) 26 #define CONFIG_SYS_NUM_TLBCAMS 64 27 #elif defined(CONFIG_E500) 28 #define CONFIG_SYS_NUM_TLBCAMS 16 29 #endif 30 31 #if defined(CONFIG_MPC8536) 32 #define CONFIG_MAX_CPUS 1 33 #define CONFIG_SYS_FSL_NUM_LAWS 12 34 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 35 #define CONFIG_SYS_FSL_SEC_COMPAT 2 36 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 37 38 #elif defined(CONFIG_MPC8540) 39 #define CONFIG_MAX_CPUS 1 40 #define CONFIG_SYS_FSL_NUM_LAWS 8 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 43 #elif defined(CONFIG_MPC8541) 44 #define CONFIG_MAX_CPUS 1 45 #define CONFIG_SYS_FSL_NUM_LAWS 8 46 #define CONFIG_SYS_FSL_SEC_COMPAT 2 47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 48 49 #elif defined(CONFIG_MPC8544) 50 #define CONFIG_MAX_CPUS 1 51 #define CONFIG_SYS_FSL_NUM_LAWS 10 52 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 53 #define CONFIG_SYS_FSL_SEC_COMPAT 2 54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 55 56 #elif defined(CONFIG_MPC8548) 57 #define CONFIG_MAX_CPUS 1 58 #define CONFIG_SYS_FSL_NUM_LAWS 10 59 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 60 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 62 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 63 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 64 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 65 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 66 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 67 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 68 #define CONFIG_SYS_FSL_RMU 69 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 70 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 71 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 72 73 #elif defined(CONFIG_MPC8555) 74 #define CONFIG_MAX_CPUS 1 75 #define CONFIG_SYS_FSL_NUM_LAWS 8 76 #define CONFIG_SYS_FSL_SEC_COMPAT 2 77 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 78 79 #elif defined(CONFIG_MPC8560) 80 #define CONFIG_MAX_CPUS 1 81 #define CONFIG_SYS_FSL_NUM_LAWS 8 82 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 83 84 #elif defined(CONFIG_MPC8568) 85 #define CONFIG_MAX_CPUS 1 86 #define CONFIG_SYS_FSL_NUM_LAWS 10 87 #define CONFIG_SYS_FSL_SEC_COMPAT 2 88 #define QE_MURAM_SIZE 0x10000UL 89 #define MAX_QE_RISC 2 90 #define QE_NUM_OF_SNUM 28 91 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 92 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 93 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 94 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 95 #define CONFIG_SYS_FSL_RMU 96 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 97 98 #elif defined(CONFIG_MPC8569) 99 #define CONFIG_MAX_CPUS 1 100 #define CONFIG_SYS_FSL_NUM_LAWS 10 101 #define CONFIG_SYS_FSL_SEC_COMPAT 2 102 #define QE_MURAM_SIZE 0x20000UL 103 #define MAX_QE_RISC 4 104 #define QE_NUM_OF_SNUM 46 105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 109 #define CONFIG_SYS_FSL_RMU 110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 111 112 #elif defined(CONFIG_MPC8572) 113 #define CONFIG_MAX_CPUS 2 114 #define CONFIG_SYS_FSL_NUM_LAWS 12 115 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 116 #define CONFIG_SYS_FSL_SEC_COMPAT 2 117 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 118 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 119 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 120 121 #elif defined(CONFIG_P1010) 122 #define CONFIG_MAX_CPUS 1 123 #define CONFIG_FSL_SDHC_V2_3 124 #define CONFIG_SYS_FSL_NUM_LAWS 12 125 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 126 #define CONFIG_TSECV2 127 #define CONFIG_SYS_FSL_SEC_COMPAT 4 128 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 129 #define CONFIG_NUM_DDR_CONTROLLERS 1 130 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 131 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 132 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 133 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 134 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 135 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 136 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 137 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 138 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 139 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 140 141 /* P1011 is single core version of P1020 */ 142 #elif defined(CONFIG_P1011) 143 #define CONFIG_MAX_CPUS 1 144 #define CONFIG_SYS_FSL_NUM_LAWS 12 145 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 146 #define CONFIG_TSECV2 147 #define CONFIG_FSL_PCIE_DISABLE_ASPM 148 #define CONFIG_SYS_FSL_SEC_COMPAT 2 149 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 150 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 151 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 152 153 /* P1012 is single core version of P1021 */ 154 #elif defined(CONFIG_P1012) 155 #define CONFIG_MAX_CPUS 1 156 #define CONFIG_SYS_FSL_NUM_LAWS 12 157 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 158 #define CONFIG_TSECV2 159 #define CONFIG_FSL_PCIE_DISABLE_ASPM 160 #define CONFIG_SYS_FSL_SEC_COMPAT 2 161 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 162 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 163 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 164 #define QE_MURAM_SIZE 0x6000UL 165 #define MAX_QE_RISC 1 166 #define QE_NUM_OF_SNUM 28 167 168 /* P1013 is single core version of P1022 */ 169 #elif defined(CONFIG_P1013) 170 #define CONFIG_MAX_CPUS 1 171 #define CONFIG_SYS_FSL_NUM_LAWS 12 172 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 173 #define CONFIG_TSECV2 174 #define CONFIG_SYS_FSL_SEC_COMPAT 2 175 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 176 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 177 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 178 #define CONFIG_FSL_SATA_ERRATUM_A001 179 180 #elif defined(CONFIG_P1014) 181 #define CONFIG_MAX_CPUS 1 182 #define CONFIG_FSL_SDHC_V2_3 183 #define CONFIG_SYS_FSL_NUM_LAWS 12 184 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 185 #define CONFIG_TSECV2 186 #define CONFIG_SYS_FSL_SEC_COMPAT 4 187 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 188 #define CONFIG_NUM_DDR_CONTROLLERS 1 189 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 190 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 191 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 192 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 193 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 194 195 /* P1017 is single core version of P1023 */ 196 #elif defined(CONFIG_P1017) 197 #define CONFIG_MAX_CPUS 1 198 #define CONFIG_SYS_FSL_NUM_LAWS 12 199 #define CONFIG_SYS_FSL_SEC_COMPAT 4 200 #define CONFIG_SYS_NUM_FMAN 1 201 #define CONFIG_SYS_NUM_FM1_DTSEC 2 202 #define CONFIG_NUM_DDR_CONTROLLERS 1 203 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 204 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 205 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 206 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 207 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 208 209 #elif defined(CONFIG_P1020) 210 #define CONFIG_MAX_CPUS 2 211 #define CONFIG_SYS_FSL_NUM_LAWS 12 212 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 213 #define CONFIG_TSECV2 214 #define CONFIG_FSL_PCIE_DISABLE_ASPM 215 #define CONFIG_SYS_FSL_SEC_COMPAT 2 216 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 217 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 218 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 219 220 #elif defined(CONFIG_P1021) 221 #define CONFIG_MAX_CPUS 2 222 #define CONFIG_SYS_FSL_NUM_LAWS 12 223 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 224 #define CONFIG_TSECV2 225 #define CONFIG_FSL_PCIE_DISABLE_ASPM 226 #define CONFIG_SYS_FSL_SEC_COMPAT 2 227 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 228 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 229 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 230 #define QE_MURAM_SIZE 0x6000UL 231 #define MAX_QE_RISC 1 232 #define QE_NUM_OF_SNUM 28 233 234 #elif defined(CONFIG_P1022) 235 #define CONFIG_MAX_CPUS 2 236 #define CONFIG_SYS_FSL_NUM_LAWS 12 237 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 238 #define CONFIG_TSECV2 239 #define CONFIG_SYS_FSL_SEC_COMPAT 2 240 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 241 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 242 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 243 #define CONFIG_FSL_SATA_ERRATUM_A001 244 245 #elif defined(CONFIG_P1023) 246 #define CONFIG_MAX_CPUS 2 247 #define CONFIG_SYS_FSL_NUM_LAWS 12 248 #define CONFIG_SYS_FSL_SEC_COMPAT 4 249 #define CONFIG_SYS_NUM_FMAN 1 250 #define CONFIG_SYS_NUM_FM1_DTSEC 2 251 #define CONFIG_NUM_DDR_CONTROLLERS 1 252 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 253 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 254 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 255 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 256 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 257 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 258 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 259 260 /* P1024 is lower end variant of P1020 */ 261 #elif defined(CONFIG_P1024) 262 #define CONFIG_MAX_CPUS 2 263 #define CONFIG_SYS_FSL_NUM_LAWS 12 264 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 265 #define CONFIG_TSECV2 266 #define CONFIG_FSL_PCIE_DISABLE_ASPM 267 #define CONFIG_SYS_FSL_SEC_COMPAT 2 268 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 269 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 270 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 271 272 /* P1025 is lower end variant of P1021 */ 273 #elif defined(CONFIG_P1025) 274 #define CONFIG_MAX_CPUS 2 275 #define CONFIG_SYS_FSL_NUM_LAWS 12 276 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 277 #define CONFIG_TSECV2 278 #define CONFIG_FSL_PCIE_DISABLE_ASPM 279 #define CONFIG_SYS_FSL_SEC_COMPAT 2 280 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 281 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 282 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 283 #define QE_MURAM_SIZE 0x6000UL 284 #define MAX_QE_RISC 1 285 #define QE_NUM_OF_SNUM 28 286 287 /* P2010 is single core version of P2020 */ 288 #elif defined(CONFIG_P2010) 289 #define CONFIG_MAX_CPUS 1 290 #define CONFIG_SYS_FSL_NUM_LAWS 12 291 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 292 #define CONFIG_SYS_FSL_SEC_COMPAT 2 293 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 294 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 295 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 296 297 #elif defined(CONFIG_P2020) 298 #define CONFIG_MAX_CPUS 2 299 #define CONFIG_SYS_FSL_NUM_LAWS 12 300 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 301 #define CONFIG_SYS_FSL_SEC_COMPAT 2 302 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 303 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 304 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 305 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 306 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 307 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 308 #define CONFIG_SYS_FSL_RMU 309 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 310 311 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 312 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 313 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 314 #define CONFIG_MAX_CPUS 4 315 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 316 #define CONFIG_SYS_FSL_NUM_LAWS 32 317 #define CONFIG_SYS_FSL_SEC_COMPAT 4 318 #define CONFIG_SYS_NUM_FMAN 1 319 #define CONFIG_SYS_NUM_FM1_DTSEC 5 320 #define CONFIG_SYS_NUM_FM1_10GEC 1 321 #define CONFIG_NUM_DDR_CONTROLLERS 1 322 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 323 #define CONFIG_SYS_FSL_TBCLK_DIV 32 324 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 325 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 326 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 327 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 328 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 329 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 330 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 331 #define CONFIG_SYS_FSL_ERRATUM_USB14 332 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 333 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 334 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 335 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 336 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 337 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 338 #define CONFIG_SYS_FSL_ERRATUM_A004510 339 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 340 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 341 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 342 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 343 #define CONFIG_SYS_FSL_ERRATUM_A004849 344 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 345 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 346 347 #elif defined(CONFIG_PPC_P3041) 348 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 349 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 350 #define CONFIG_MAX_CPUS 4 351 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 352 #define CONFIG_SYS_FSL_NUM_LAWS 32 353 #define CONFIG_SYS_FSL_SEC_COMPAT 4 354 #define CONFIG_SYS_NUM_FMAN 1 355 #define CONFIG_SYS_NUM_FM1_DTSEC 5 356 #define CONFIG_SYS_NUM_FM1_10GEC 1 357 #define CONFIG_NUM_DDR_CONTROLLERS 1 358 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 359 #define CONFIG_SYS_FSL_TBCLK_DIV 32 360 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 361 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 362 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 363 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 364 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 365 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 366 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 367 #define CONFIG_SYS_FSL_ERRATUM_USB14 368 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 369 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 370 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 371 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 372 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 373 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 374 #define CONFIG_SYS_FSL_ERRATUM_A004510 375 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 376 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 377 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 378 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 379 #define CONFIG_SYS_FSL_ERRATUM_A004849 380 #define CONFIG_SYS_FSL_ERRATUM_A005812 381 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 382 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 383 384 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 385 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 386 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 387 #define CONFIG_MAX_CPUS 8 388 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 389 #define CONFIG_SYS_FSL_NUM_LAWS 32 390 #define CONFIG_SYS_FSL_SEC_COMPAT 4 391 #define CONFIG_SYS_NUM_FMAN 2 392 #define CONFIG_SYS_NUM_FM1_DTSEC 4 393 #define CONFIG_SYS_NUM_FM2_DTSEC 4 394 #define CONFIG_SYS_NUM_FM1_10GEC 1 395 #define CONFIG_SYS_NUM_FM2_10GEC 1 396 #define CONFIG_NUM_DDR_CONTROLLERS 2 397 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 398 #define CONFIG_SYS_FSL_TBCLK_DIV 16 399 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 400 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 401 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 402 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 403 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 404 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 405 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 406 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 407 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 408 #define CONFIG_SYS_P4080_ERRATUM_CPU22 409 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 410 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 411 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 412 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 413 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 414 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 415 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 416 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 417 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 418 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 419 #define CONFIG_SYS_FSL_RMU 420 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 421 #define CONFIG_SYS_FSL_ERRATUM_A004510 422 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 423 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 424 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 425 #define CONFIG_SYS_FSL_ERRATUM_A004849 426 #define CONFIG_SYS_FSL_ERRATUM_A004580 427 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 428 #define CONFIG_SYS_FSL_ERRATUM_A005812 429 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 430 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 431 432 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 433 #define CONFIG_SYS_PPC64 /* 64-bit core */ 434 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 435 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 436 #define CONFIG_MAX_CPUS 2 437 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 438 #define CONFIG_SYS_FSL_NUM_LAWS 32 439 #define CONFIG_SYS_FSL_SEC_COMPAT 4 440 #define CONFIG_SYS_NUM_FMAN 1 441 #define CONFIG_SYS_NUM_FM1_DTSEC 5 442 #define CONFIG_SYS_NUM_FM1_10GEC 1 443 #define CONFIG_NUM_DDR_CONTROLLERS 2 444 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 445 #define CONFIG_SYS_FSL_TBCLK_DIV 32 446 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 447 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 448 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 449 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 450 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 451 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 452 #define CONFIG_SYS_FSL_ERRATUM_USB14 453 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 454 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 455 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 456 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 457 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 458 #define CONFIG_SYS_FSL_ERRATUM_A004510 459 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 460 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 461 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 462 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 463 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 464 465 #elif defined(CONFIG_PPC_P5040) 466 #define CONFIG_SYS_PPC64 467 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 468 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 469 #define CONFIG_MAX_CPUS 4 470 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 471 #define CONFIG_SYS_FSL_NUM_LAWS 32 472 #define CONFIG_SYS_FSL_SEC_COMPAT 4 473 #define CONFIG_SYS_NUM_FMAN 2 474 #define CONFIG_SYS_NUM_FM1_DTSEC 5 475 #define CONFIG_SYS_NUM_FM1_10GEC 1 476 #define CONFIG_SYS_NUM_FM2_DTSEC 5 477 #define CONFIG_SYS_NUM_FM2_10GEC 1 478 #define CONFIG_NUM_DDR_CONTROLLERS 2 479 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 480 #define CONFIG_SYS_FSL_TBCLK_DIV 16 481 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 482 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 483 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 484 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 485 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 486 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 487 #define CONFIG_SYS_FSL_ERRATUM_USB14 488 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 489 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 490 #define CONFIG_SYS_FSL_ERRATUM_A004699 491 #define CONFIG_SYS_FSL_ERRATUM_A004510 492 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 493 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 494 #define CONFIG_SYS_FSL_ERRATUM_A005812 495 496 #elif defined(CONFIG_BSC9131) 497 #define CONFIG_MAX_CPUS 1 498 #define CONFIG_FSL_SDHC_V2_3 499 #define CONFIG_SYS_FSL_NUM_LAWS 12 500 #define CONFIG_TSECV2 501 #define CONFIG_SYS_FSL_SEC_COMPAT 4 502 #define CONFIG_NUM_DDR_CONTROLLERS 1 503 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 504 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 505 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 506 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 507 #define CONFIG_NAND_FSL_IFC 508 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 509 510 #elif defined(CONFIG_BSC9132) 511 #define CONFIG_MAX_CPUS 2 512 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 513 #define CONFIG_FSL_SDHC_V2_3 514 #define CONFIG_SYS_FSL_NUM_LAWS 12 515 #define CONFIG_TSECV2 516 #define CONFIG_SYS_FSL_SEC_COMPAT 4 517 #define CONFIG_NUM_DDR_CONTROLLERS 2 518 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 519 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 520 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 521 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 522 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 523 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 524 #define CONFIG_NAND_FSL_IFC 525 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 526 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 527 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 528 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 529 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 530 531 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 532 #define CONFIG_E6500 533 #define CONFIG_SYS_PPC64 /* 64-bit core */ 534 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 535 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 536 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 537 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 538 #ifdef CONFIG_PPC_T4240 539 #define CONFIG_MAX_CPUS 12 540 #define CONFIG_SYS_NUM_FM1_DTSEC 8 541 #define CONFIG_SYS_NUM_FM1_10GEC 2 542 #define CONFIG_SYS_NUM_FM2_DTSEC 8 543 #define CONFIG_SYS_NUM_FM2_10GEC 2 544 #define CONFIG_NUM_DDR_CONTROLLERS 3 545 #else 546 #define CONFIG_MAX_CPUS 8 547 #define CONFIG_SYS_NUM_FM1_DTSEC 7 548 #define CONFIG_SYS_NUM_FM1_10GEC 1 549 #define CONFIG_SYS_NUM_FM2_DTSEC 7 550 #define CONFIG_SYS_NUM_FM2_10GEC 1 551 #define CONFIG_NUM_DDR_CONTROLLERS 2 552 #endif 553 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 554 #define CONFIG_SYS_FSL_NUM_LAWS 32 555 #define CONFIG_SYS_FSL_SRDS_1 556 #define CONFIG_SYS_FSL_SRDS_2 557 #define CONFIG_SYS_FSL_SRDS_3 558 #define CONFIG_SYS_FSL_SRDS_4 559 #define CONFIG_SYS_FSL_SEC_COMPAT 4 560 #define CONFIG_SYS_NUM_FMAN 2 561 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 562 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 563 #define CONFIG_SYS_FMAN_V3 564 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 565 #define CONFIG_SYS_FSL_TBCLK_DIV 16 566 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 567 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 568 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 569 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 570 #define CONFIG_SYS_FSL_SRIO_LIODN 571 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 572 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 573 #define CONFIG_SYS_FSL_ERRATUM_A004468 574 #define CONFIG_SYS_FSL_ERRATUM_A_004934 575 #define CONFIG_SYS_FSL_ERRATUM_A005871 576 #define CONFIG_SYS_FSL_ERRATUM_A006593 577 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 578 #define CONFIG_SYS_FSL_PCI_VER_3_X 579 580 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 581 #define CONFIG_E6500 582 #define CONFIG_SYS_PPC64 /* 64-bit core */ 583 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 584 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 585 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 586 #define CONFIG_SYS_FSL_NUM_LAWS 32 587 #define CONFIG_SYS_FSL_SRDS_1 588 #define CONFIG_SYS_FSL_SRDS_2 589 #define CONFIG_SYS_FSL_SEC_COMPAT 4 590 #define CONFIG_SYS_NUM_FMAN 1 591 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 592 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 593 #define CONFIG_SYS_FMAN_V3 594 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 595 #define CONFIG_SYS_FSL_TBCLK_DIV 16 596 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 597 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 598 #define CONFIG_SYS_FSL_ERRATUM_A_004934 599 #define CONFIG_SYS_FSL_ERRATUM_A005871 600 #define CONFIG_SYS_FSL_ERRATUM_A006593 601 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 602 603 #ifdef CONFIG_PPC_B4860 604 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 605 #define CONFIG_MAX_CPUS 4 606 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 607 #define CONFIG_SYS_NUM_FM1_DTSEC 6 608 #define CONFIG_SYS_NUM_FM1_10GEC 2 609 #define CONFIG_NUM_DDR_CONTROLLERS 2 610 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 611 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 612 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 613 #define CONFIG_SYS_FSL_SRIO_LIODN 614 #else 615 #define CONFIG_MAX_CPUS 2 616 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 617 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 618 #define CONFIG_SYS_NUM_FM1_DTSEC 4 619 #define CONFIG_SYS_NUM_FM1_10GEC 0 620 #define CONFIG_NUM_DDR_CONTROLLERS 1 621 #endif 622 623 #elif defined(CONFIG_PPC_T1040) 624 #define CONFIG_E5500 625 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 626 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 627 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 628 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 629 #define CONFIG_MAX_CPUS 4 630 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 631 #define CONFIG_SYS_FSL_NUM_LAWS 16 632 #define CONFIG_SYS_FSL_SEC_COMPAT 4 633 #define CONFIG_SYS_NUM_FMAN 1 634 #define CONFIG_SYS_NUM_FM1_DTSEC 5 635 #define CONFIG_NUM_DDR_CONTROLLERS 1 636 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 637 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 638 #define CONFIG_SYS_FMAN_V3 639 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 640 #define CONFIG_SYS_FSL_TBCLK_DIV 32 641 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 642 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 643 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 644 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 645 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 646 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 647 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 648 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 649 650 #elif defined(CONFIG_PPC_C29X) 651 #define CONFIG_MAX_CPUS 1 652 #define CONFIG_FSL_SDHC_V2_3 653 #define CONFIG_SYS_FSL_NUM_LAWS 12 654 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 655 #define CONFIG_TSECV2_1 656 #define CONFIG_SYS_FSL_SEC_COMPAT 6 657 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 658 #define CONFIG_NUM_DDR_CONTROLLERS 1 659 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 660 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 661 662 #else 663 #error Processor type not defined for this platform 664 #endif 665 666 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 667 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 668 #endif 669 670 #ifdef CONFIG_E6500 671 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 672 #else 673 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 674 #endif 675 676 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 677