1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 /* 13 * This macro should be removed when we no longer care about backwards 14 * compatibility with older operating systems. 15 */ 16 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 17 18 #include <fsl_ddrc_version.h> 19 #define CONFIG_SYS_FSL_DDR_BE 20 21 /* IP endianness */ 22 #define CONFIG_SYS_FSL_IFC_BE 23 #define CONFIG_SYS_FSL_SEC_BE 24 #define CONFIG_SYS_FSL_SFP_BE 25 #define CONFIG_SYS_FSL_SEC_MON_BE 26 27 /* Number of TLB CAM entries we have on FSL Book-E chips */ 28 #if defined(CONFIG_E500MC) 29 #define CONFIG_SYS_NUM_TLBCAMS 64 30 #elif defined(CONFIG_E500) 31 #define CONFIG_SYS_NUM_TLBCAMS 16 32 #endif 33 34 #if defined(CONFIG_ARCH_MPC8536) 35 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 36 #define CONFIG_SYS_FSL_SEC_COMPAT 2 37 #define CONFIG_SYS_FSL_ERRATUM_A004508 38 #define CONFIG_SYS_FSL_ERRATUM_A005125 39 40 #elif defined(CONFIG_ARCH_MPC8540) 41 #define CONFIG_SYS_FSL_DDRC_GEN1 42 43 #elif defined(CONFIG_ARCH_MPC8541) 44 #define CONFIG_SYS_FSL_DDRC_GEN1 45 #define CONFIG_SYS_FSL_SEC_COMPAT 2 46 47 #elif defined(CONFIG_ARCH_MPC8544) 48 #define CONFIG_SYS_FSL_DDRC_GEN2 49 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 50 #define CONFIG_SYS_FSL_SEC_COMPAT 2 51 #define CONFIG_SYS_FSL_ERRATUM_A005125 52 53 #elif defined(CONFIG_ARCH_MPC8548) 54 #define CONFIG_SYS_FSL_DDRC_GEN2 55 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 56 #define CONFIG_SYS_FSL_SEC_COMPAT 2 57 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 58 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 59 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 60 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 61 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 62 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 63 #define CONFIG_SYS_FSL_RMU 64 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 65 #define CONFIG_SYS_FSL_ERRATUM_A005125 66 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 67 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 68 69 #elif defined(CONFIG_ARCH_MPC8555) 70 #define CONFIG_SYS_FSL_DDRC_GEN1 71 #define CONFIG_SYS_FSL_SEC_COMPAT 2 72 73 #elif defined(CONFIG_ARCH_MPC8560) 74 #define CONFIG_SYS_FSL_DDRC_GEN1 75 76 #elif defined(CONFIG_ARCH_MPC8568) 77 #define CONFIG_SYS_FSL_DDRC_GEN2 78 #define CONFIG_SYS_FSL_SEC_COMPAT 2 79 #define QE_MURAM_SIZE 0x10000UL 80 #define MAX_QE_RISC 2 81 #define QE_NUM_OF_SNUM 28 82 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 83 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 84 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 85 #define CONFIG_SYS_FSL_RMU 86 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 87 88 #elif defined(CONFIG_ARCH_MPC8569) 89 #define CONFIG_SYS_FSL_SEC_COMPAT 2 90 #define QE_MURAM_SIZE 0x20000UL 91 #define MAX_QE_RISC 4 92 #define QE_NUM_OF_SNUM 46 93 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 94 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 95 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 96 #define CONFIG_SYS_FSL_RMU 97 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 98 #define CONFIG_SYS_FSL_ERRATUM_A004508 99 #define CONFIG_SYS_FSL_ERRATUM_A005125 100 101 #elif defined(CONFIG_ARCH_MPC8572) 102 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 103 #define CONFIG_SYS_FSL_SEC_COMPAT 2 104 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 105 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 106 #define CONFIG_SYS_FSL_ERRATUM_A004508 107 #define CONFIG_SYS_FSL_ERRATUM_A005125 108 109 #elif defined(CONFIG_ARCH_P1010) 110 #define CONFIG_FSL_SDHC_V2_3 111 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 112 #define CONFIG_TSECV2 113 #define CONFIG_SYS_FSL_SEC_COMPAT 4 114 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 115 #define CONFIG_NUM_DDR_CONTROLLERS 1 116 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 117 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 118 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 119 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 120 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 121 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 122 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 123 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 124 #define CONFIG_SYS_FSL_ERRATUM_A005125 125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 126 #define CONFIG_SYS_FSL_ERRATUM_A004508 127 #define CONFIG_SYS_FSL_ERRATUM_A007075 128 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 129 #define CONFIG_SYS_FSL_ERRATUM_A006261 130 #define CONFIG_SYS_FSL_ERRATUM_A004477 131 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 132 #define CONFIG_ESDHC_HC_BLK_ADDR 133 134 /* P1011 is single core version of P1020 */ 135 #elif defined(CONFIG_ARCH_P1011) 136 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 137 #define CONFIG_TSECV2 138 #define CONFIG_FSL_PCIE_DISABLE_ASPM 139 #define CONFIG_SYS_FSL_SEC_COMPAT 2 140 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 141 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 142 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 143 #define CONFIG_SYS_FSL_ERRATUM_A004508 144 #define CONFIG_SYS_FSL_ERRATUM_A005125 145 146 #elif defined(CONFIG_ARCH_P1020) 147 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 148 #define CONFIG_TSECV2 149 #define CONFIG_FSL_PCIE_DISABLE_ASPM 150 #define CONFIG_SYS_FSL_SEC_COMPAT 2 151 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 152 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 153 #define CONFIG_SYS_FSL_ERRATUM_A004508 154 #define CONFIG_SYS_FSL_ERRATUM_A005125 155 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 156 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 157 #endif 158 159 #elif defined(CONFIG_ARCH_P1021) 160 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 161 #define CONFIG_TSECV2 162 #define CONFIG_FSL_PCIE_DISABLE_ASPM 163 #define CONFIG_SYS_FSL_SEC_COMPAT 2 164 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 165 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 166 #define QE_MURAM_SIZE 0x6000UL 167 #define MAX_QE_RISC 1 168 #define QE_NUM_OF_SNUM 28 169 #define CONFIG_SYS_FSL_ERRATUM_A004508 170 #define CONFIG_SYS_FSL_ERRATUM_A005125 171 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 172 173 #elif defined(CONFIG_ARCH_P1022) 174 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 175 #define CONFIG_TSECV2 176 #define CONFIG_SYS_FSL_SEC_COMPAT 2 177 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 178 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 179 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 180 #define CONFIG_FSL_SATA_ERRATUM_A001 181 #define CONFIG_SYS_FSL_ERRATUM_A004508 182 #define CONFIG_SYS_FSL_ERRATUM_A005125 183 #define CONFIG_SYS_FSL_ERRATUM_A004477 184 185 #elif defined(CONFIG_ARCH_P1023) 186 #define CONFIG_SYS_FSL_SEC_COMPAT 4 187 #define CONFIG_SYS_NUM_FMAN 1 188 #define CONFIG_SYS_NUM_FM1_DTSEC 2 189 #define CONFIG_NUM_DDR_CONTROLLERS 1 190 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 191 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 192 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 193 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 194 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 195 #define CONFIG_SYS_FSL_ERRATUM_A004508 196 #define CONFIG_SYS_FSL_ERRATUM_A005125 197 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 198 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 199 200 /* P1024 is lower end variant of P1020 */ 201 #elif defined(CONFIG_ARCH_P1024) 202 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 203 #define CONFIG_TSECV2 204 #define CONFIG_FSL_PCIE_DISABLE_ASPM 205 #define CONFIG_SYS_FSL_SEC_COMPAT 2 206 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 207 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 208 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 209 #define CONFIG_SYS_FSL_ERRATUM_A004508 210 #define CONFIG_SYS_FSL_ERRATUM_A005125 211 212 /* P1025 is lower end variant of P1021 */ 213 #elif defined(CONFIG_ARCH_P1025) 214 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 215 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 216 #define CONFIG_TSECV2 217 #define CONFIG_FSL_PCIE_DISABLE_ASPM 218 #define CONFIG_SYS_FSL_SEC_COMPAT 2 219 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 220 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 221 #define QE_MURAM_SIZE 0x6000UL 222 #define MAX_QE_RISC 1 223 #define QE_NUM_OF_SNUM 28 224 #define CONFIG_SYS_FSL_ERRATUM_A004508 225 #define CONFIG_SYS_FSL_ERRATUM_A005125 226 227 #elif defined(CONFIG_ARCH_P2020) 228 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 229 #define CONFIG_SYS_FSL_SEC_COMPAT 2 230 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 231 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 232 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 233 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 234 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 235 #define CONFIG_SYS_FSL_RMU 236 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 237 #define CONFIG_SYS_FSL_ERRATUM_A004508 238 #define CONFIG_SYS_FSL_ERRATUM_A005125 239 #define CONFIG_SYS_FSL_ERRATUM_A004477 240 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 241 242 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ 243 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 244 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 245 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 246 #define CONFIG_SYS_FSL_SEC_COMPAT 4 247 #define CONFIG_SYS_NUM_FMAN 1 248 #define CONFIG_SYS_NUM_FM1_DTSEC 5 249 #define CONFIG_SYS_NUM_FM1_10GEC 1 250 #define CONFIG_NUM_DDR_CONTROLLERS 1 251 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 252 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 253 #define CONFIG_SYS_FSL_TBCLK_DIV 32 254 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 255 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 256 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 257 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 258 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 259 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 260 #define CONFIG_SYS_FSL_ERRATUM_USB14 261 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 262 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 263 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 264 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 265 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 266 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 267 #define CONFIG_SYS_FSL_ERRATUM_A004510 268 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 269 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 270 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 271 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 272 #define CONFIG_SYS_FSL_ERRATUM_A004849 273 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 274 #define CONFIG_SYS_FSL_ERRATUM_A006261 275 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 276 277 #elif defined(CONFIG_ARCH_P3041) 278 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 279 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 280 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 281 #define CONFIG_SYS_FSL_SEC_COMPAT 4 282 #define CONFIG_SYS_NUM_FMAN 1 283 #define CONFIG_SYS_NUM_FM1_DTSEC 5 284 #define CONFIG_SYS_NUM_FM1_10GEC 1 285 #define CONFIG_NUM_DDR_CONTROLLERS 1 286 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 287 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 288 #define CONFIG_SYS_FSL_TBCLK_DIV 32 289 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 290 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 291 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 292 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 293 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 294 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 295 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 296 #define CONFIG_SYS_FSL_ERRATUM_USB14 297 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 298 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 299 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 300 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 301 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 302 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 303 #define CONFIG_SYS_FSL_ERRATUM_A004510 304 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 305 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 306 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 307 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 308 #define CONFIG_SYS_FSL_ERRATUM_A004849 309 #define CONFIG_SYS_FSL_ERRATUM_A005812 310 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 311 #define CONFIG_SYS_FSL_ERRATUM_A006261 312 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 313 314 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ 315 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 316 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 317 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 318 #define CONFIG_SYS_FSL_SEC_COMPAT 4 319 #define CONFIG_SYS_NUM_FMAN 2 320 #define CONFIG_SYS_NUM_FM1_DTSEC 4 321 #define CONFIG_SYS_NUM_FM2_DTSEC 4 322 #define CONFIG_SYS_NUM_FM1_10GEC 1 323 #define CONFIG_SYS_NUM_FM2_10GEC 1 324 #define CONFIG_NUM_DDR_CONTROLLERS 2 325 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 326 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 327 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 328 #define CONFIG_SYS_FSL_TBCLK_DIV 16 329 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 330 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 331 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 332 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 333 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 334 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 335 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 336 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 337 #define CONFIG_SYS_P4080_ERRATUM_CPU22 338 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 339 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 340 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 341 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 342 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 343 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 344 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 345 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 346 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 347 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 348 #define CONFIG_SYS_FSL_RMU 349 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 350 #define CONFIG_SYS_FSL_ERRATUM_A004510 351 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 352 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 353 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 354 #define CONFIG_SYS_FSL_ERRATUM_A004849 355 #define CONFIG_SYS_FSL_ERRATUM_A004580 356 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 357 #define CONFIG_SYS_FSL_ERRATUM_A005812 358 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 359 #define CONFIG_SYS_FSL_ERRATUM_A007075 360 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 361 362 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ 363 #define CONFIG_SYS_PPC64 /* 64-bit core */ 364 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 365 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 366 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 367 #define CONFIG_SYS_FSL_SEC_COMPAT 4 368 #define CONFIG_SYS_NUM_FMAN 1 369 #define CONFIG_SYS_NUM_FM1_DTSEC 5 370 #define CONFIG_SYS_NUM_FM1_10GEC 1 371 #define CONFIG_NUM_DDR_CONTROLLERS 2 372 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 373 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 374 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 375 #define CONFIG_SYS_FSL_TBCLK_DIV 32 376 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 377 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 378 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 379 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 380 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 381 #define CONFIG_SYS_FSL_ERRATUM_USB14 382 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 383 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 384 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 385 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 386 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 387 #define CONFIG_SYS_FSL_ERRATUM_A004510 388 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 389 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 390 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 391 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 392 #define CONFIG_SYS_FSL_ERRATUM_A006261 393 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 394 395 #elif defined(CONFIG_ARCH_P5040) 396 #define CONFIG_SYS_PPC64 397 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 398 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 399 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 400 #define CONFIG_SYS_FSL_SEC_COMPAT 4 401 #define CONFIG_SYS_NUM_FMAN 2 402 #define CONFIG_SYS_NUM_FM1_DTSEC 5 403 #define CONFIG_SYS_NUM_FM1_10GEC 1 404 #define CONFIG_SYS_NUM_FM2_DTSEC 5 405 #define CONFIG_SYS_NUM_FM2_10GEC 1 406 #define CONFIG_NUM_DDR_CONTROLLERS 2 407 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 408 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 409 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 410 #define CONFIG_SYS_FSL_TBCLK_DIV 16 411 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 412 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 413 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 414 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 415 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 416 #define CONFIG_SYS_FSL_ERRATUM_USB14 417 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 418 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 419 #define CONFIG_SYS_FSL_ERRATUM_A004699 420 #define CONFIG_SYS_FSL_ERRATUM_A004510 421 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 422 #define CONFIG_SYS_FSL_ERRATUM_A006261 423 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 424 #define CONFIG_SYS_FSL_ERRATUM_A005812 425 426 #elif defined(CONFIG_ARCH_BSC9131) 427 #define CONFIG_FSL_SDHC_V2_3 428 #define CONFIG_TSECV2 429 #define CONFIG_SYS_FSL_SEC_COMPAT 4 430 #define CONFIG_NUM_DDR_CONTROLLERS 1 431 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 432 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 433 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 434 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 435 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 436 #define CONFIG_NAND_FSL_IFC 437 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 438 #define CONFIG_SYS_FSL_ERRATUM_A005125 439 #define CONFIG_SYS_FSL_ERRATUM_A004477 440 #define CONFIG_ESDHC_HC_BLK_ADDR 441 442 #elif defined(CONFIG_ARCH_BSC9132) 443 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 444 #define CONFIG_FSL_SDHC_V2_3 445 #define CONFIG_TSECV2 446 #define CONFIG_SYS_FSL_SEC_COMPAT 4 447 #define CONFIG_NUM_DDR_CONTROLLERS 2 448 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 449 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 450 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 451 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 452 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 453 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 454 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 455 #define CONFIG_NAND_FSL_IFC 456 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 457 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 458 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 459 #define CONFIG_SYS_FSL_ERRATUM_A005125 460 #define CONFIG_SYS_FSL_ERRATUM_A005434 461 #define CONFIG_SYS_FSL_ERRATUM_A004477 462 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 463 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 464 #define CONFIG_ESDHC_HC_BLK_ADDR 465 466 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) 467 #define CONFIG_E6500 468 #define CONFIG_SYS_PPC64 /* 64-bit core */ 469 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 470 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 471 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 472 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 473 #ifdef CONFIG_ARCH_T4240 474 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 475 #define CONFIG_SYS_NUM_FM1_DTSEC 8 476 #define CONFIG_SYS_NUM_FM1_10GEC 2 477 #define CONFIG_SYS_NUM_FM2_DTSEC 8 478 #define CONFIG_SYS_NUM_FM2_10GEC 2 479 #define CONFIG_NUM_DDR_CONTROLLERS 3 480 #define CONFIG_SYS_FSL_ERRATUM_A006261 481 #else 482 #define CONFIG_SYS_NUM_FM1_DTSEC 6 483 #define CONFIG_SYS_NUM_FM1_10GEC 1 484 #define CONFIG_SYS_NUM_FM2_DTSEC 8 485 #define CONFIG_SYS_NUM_FM2_10GEC 1 486 #define CONFIG_NUM_DDR_CONTROLLERS 2 487 #if defined(CONFIG_ARCH_T4160) 488 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 489 #endif 490 #endif 491 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 492 #define CONFIG_SYS_FSL_SRDS_1 493 #define CONFIG_SYS_FSL_SRDS_2 494 #define CONFIG_SYS_FSL_SRDS_3 495 #define CONFIG_SYS_FSL_SRDS_4 496 #define CONFIG_SYS_FSL_SEC_COMPAT 4 497 #define CONFIG_SYS_NUM_FMAN 2 498 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 499 #define CONFIG_SYS_PME_CLK 0 500 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 501 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 502 #define CONFIG_SYS_FMAN_V3 503 #define CONFIG_SYS_FM1_CLK 3 504 #define CONFIG_SYS_FM2_CLK 3 505 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 506 #define CONFIG_SYS_FSL_TBCLK_DIV 16 507 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 508 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 509 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 510 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 511 #define CONFIG_SYS_FSL_SRIO_LIODN 512 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 513 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 514 #define CONFIG_SYS_FSL_ERRATUM_A004468 515 #define CONFIG_SYS_FSL_ERRATUM_A005871 516 #define CONFIG_SYS_FSL_ERRATUM_A006379 517 #define CONFIG_SYS_FSL_ERRATUM_A007186 518 #define CONFIG_SYS_FSL_ERRATUM_A006593 519 #define CONFIG_SYS_FSL_ERRATUM_A007798 520 #define CONFIG_SYS_FSL_ERRATUM_A009942 521 #define CONFIG_SYS_FSL_SFP_VER_3_0 522 #define CONFIG_SYS_FSL_PCI_VER_3_X 523 524 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) 525 #define CONFIG_E6500 526 #define CONFIG_SYS_PPC64 /* 64-bit core */ 527 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 528 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 529 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 530 #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ 531 #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ 532 #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ 533 #define CONFIG_SYS_FSL_SRDS_1 534 #define CONFIG_SYS_FSL_SRDS_2 535 #define CONFIG_SYS_MAPLE 536 #define CONFIG_SYS_CPRI 537 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 538 #define CONFIG_SYS_FSL_SEC_COMPAT 4 539 #define CONFIG_SYS_NUM_FMAN 1 540 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 541 #define CONFIG_SYS_FM1_CLK 0 542 #define CONFIG_SYS_CPRI_CLK 3 543 #define CONFIG_SYS_ULB_CLK 4 544 #define CONFIG_SYS_ETVPE_CLK 1 545 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 546 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 547 #define CONFIG_SYS_FMAN_V3 548 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 549 #define CONFIG_SYS_FSL_TBCLK_DIV 16 550 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 551 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 552 #define CONFIG_SYS_FSL_ERRATUM_A005871 553 #define CONFIG_SYS_FSL_ERRATUM_A006379 554 #define CONFIG_SYS_FSL_ERRATUM_A007186 555 #define CONFIG_SYS_FSL_ERRATUM_A006593 556 #define CONFIG_SYS_FSL_ERRATUM_A007075 557 #define CONFIG_SYS_FSL_ERRATUM_A006475 558 #define CONFIG_SYS_FSL_ERRATUM_A006384 559 #define CONFIG_SYS_FSL_ERRATUM_A007212 560 #define CONFIG_SYS_FSL_ERRATUM_A004477 561 #define CONFIG_SYS_FSL_ERRATUM_A009942 562 #define CONFIG_SYS_FSL_SFP_VER_3_0 563 564 #ifdef CONFIG_ARCH_B4860 565 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 566 #define CONFIG_MAX_DSP_CPUS 12 567 #define CONFIG_NUM_DSP_CPUS 6 568 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 569 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 570 #define CONFIG_SYS_NUM_FM1_DTSEC 6 571 #define CONFIG_SYS_NUM_FM1_10GEC 2 572 #define CONFIG_NUM_DDR_CONTROLLERS 2 573 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 574 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 575 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 576 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 577 #define CONFIG_SYS_FSL_SRIO_LIODN 578 #else 579 #define CONFIG_MAX_DSP_CPUS 2 580 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 581 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 582 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 583 #define CONFIG_SYS_NUM_FM1_DTSEC 4 584 #define CONFIG_SYS_NUM_FM1_10GEC 0 585 #define CONFIG_NUM_DDR_CONTROLLERS 1 586 #endif 587 588 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\ 589 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 590 #define CONFIG_E5500 591 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 592 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 593 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 594 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 595 #ifdef CONFIG_SYS_FSL_DDR4 596 #define CONFIG_SYS_FSL_DDRC_GEN4 597 #endif 598 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 599 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 600 #define CONFIG_SYS_FSL_SRDS_1 601 #define CONFIG_SYS_FSL_SEC_COMPAT 5 602 #define CONFIG_SYS_NUM_FMAN 1 603 #define CONFIG_SYS_NUM_FM1_DTSEC 5 604 #define CONFIG_NUM_DDR_CONTROLLERS 1 605 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 606 #define CONFIG_PME_PLAT_CLK_DIV 2 607 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 608 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 609 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 610 #define CONFIG_SYS_FSL_ERRATUM_A008044 611 #define CONFIG_SYS_FMAN_V3 612 #define CONFIG_FM_PLAT_CLK_DIV 1 613 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 614 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 615 per rcw field value */ 616 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 617 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 618 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 619 #define CONFIG_SYS_FSL_TBCLK_DIV 16 620 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 621 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 622 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 623 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 624 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 625 #define QE_MURAM_SIZE 0x6000UL 626 #define MAX_QE_RISC 1 627 #define QE_NUM_OF_SNUM 28 628 #define CONFIG_SYS_FSL_SFP_VER_3_0 629 #define CONFIG_SYS_FSL_ERRATUM_A008378 630 #define CONFIG_SYS_FSL_ERRATUM_A009663 631 #define CONFIG_SYS_FSL_ERRATUM_A009942 632 633 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\ 634 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) 635 #define CONFIG_E5500 636 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 637 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 638 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 639 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 640 #define CONFIG_SYS_FMAN_V3 641 #ifdef CONFIG_SYS_FSL_DDR4 642 #define CONFIG_SYS_FSL_DDRC_GEN4 643 #endif 644 #define CONFIG_SYS_FSL_NUM_CC_PLL 2 645 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 646 #define CONFIG_SYS_FSL_SRDS_1 647 #define CONFIG_SYS_FSL_SEC_COMPAT 5 648 #define CONFIG_SYS_NUM_FMAN 1 649 #define CONFIG_SYS_NUM_FM1_DTSEC 4 650 #define CONFIG_SYS_NUM_FM1_10GEC 1 651 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 652 #define CONFIG_NUM_DDR_CONTROLLERS 1 653 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 654 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 655 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 656 #define CONFIG_SYS_FM1_CLK 0 657 #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1 658 per rcw field value */ 659 #define CONFIG_QBMAN_CLK_DIV 1 660 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 661 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 662 #define CONFIG_SYS_FSL_TBCLK_DIV 16 663 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 664 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 665 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 666 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 667 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 668 #define QE_MURAM_SIZE 0x6000UL 669 #define MAX_QE_RISC 1 670 #define QE_NUM_OF_SNUM 28 671 #define CONFIG_SYS_FSL_SFP_VER_3_0 672 #define CONFIG_SYS_FSL_ERRATUM_A008378 673 #define CONFIG_SYS_FSL_ERRATUM_A009663 674 #define CONFIG_SYS_FSL_ERRATUM_A009942 675 676 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) 677 #define CONFIG_E6500 678 #define CONFIG_SYS_PPC64 /* 64-bit core */ 679 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 680 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 681 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 682 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 683 #define CONFIG_SYS_FSL_QMAN_V3 684 #define CONFIG_SYS_FSL_SEC_COMPAT 4 685 #define CONFIG_SYS_NUM_FMAN 1 686 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 687 #define CONFIG_SYS_FSL_SRDS_1 688 #define CONFIG_SYS_FSL_PCI_VER_3_X 689 #if defined(CONFIG_ARCH_T2080) 690 #define CONFIG_SYS_NUM_FM1_DTSEC 8 691 #define CONFIG_SYS_NUM_FM1_10GEC 4 692 #define CONFIG_SYS_FSL_SRDS_2 693 #define CONFIG_SYS_FSL_SRIO_LIODN 694 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 695 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 696 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 697 #elif defined(CONFIG_ARCH_T2081) 698 #define CONFIG_SYS_NUM_FM1_DTSEC 6 699 #define CONFIG_SYS_NUM_FM1_10GEC 2 700 #endif 701 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 702 #define CONFIG_NUM_DDR_CONTROLLERS 1 703 #define CONFIG_PME_PLAT_CLK_DIV 1 704 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 705 #define CONFIG_SYS_FM1_CLK 0 706 #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2 707 per rcw field value */ 708 #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */ 709 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 710 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 711 #define CONFIG_SYS_FMAN_V3 712 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 713 #define CONFIG_SYS_FSL_TBCLK_DIV 16 714 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 715 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 716 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 717 #define CONFIG_SYS_FSL_ERRATUM_A007212 718 #define CONFIG_SYS_FSL_SFP_VER_3_0 719 #define CONFIG_SYS_FSL_ISBC_VER 2 720 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 721 #define CONFIG_SYS_FSL_ERRATUM_A006593 722 #define CONFIG_SYS_FSL_ERRATUM_A007186 723 #define CONFIG_SYS_FSL_ERRATUM_A006379 724 #define CONFIG_SYS_FSL_ERRATUM_A009942 725 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 726 #define CONFIG_SYS_FSL_SFP_VER_3_0 727 728 729 #elif defined(CONFIG_ARCH_C29X) 730 #define CONFIG_FSL_SDHC_V2_3 731 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 732 #define CONFIG_TSECV2_1 733 #define CONFIG_SYS_FSL_SEC_COMPAT 6 734 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 735 #define CONFIG_NUM_DDR_CONTROLLERS 1 736 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 737 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 738 #define CONFIG_SYS_FSL_ERRATUM_A005125 739 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 740 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 741 742 #elif defined(CONFIG_ARCH_QEMU_E500) 743 744 #else 745 #error Processor type not defined for this platform 746 #endif 747 748 #ifdef CONFIG_E6500 749 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 750 #else 751 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 752 #endif 753 754 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 755 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 756 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 757 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 758 #define CONFIG_SYS_FSL_DDRC_GEN3 759 #endif 760 761 #if !defined(CONFIG_ARCH_C29X) 762 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 763 #endif 764 765 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 766