1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_ 9 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 11 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 14 #endif 15 16 /* 17 * This macro should be removed when we no longer care about backwards 18 * compatibility with older operating systems. 19 */ 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 21 22 #include <fsl_ddrc_version.h> 23 #define CONFIG_SYS_FSL_DDR_BE 24 25 /* IP endianness */ 26 #define CONFIG_SYS_FSL_IFC_BE 27 #define CONFIG_SYS_FSL_SEC_BE 28 29 /* Number of TLB CAM entries we have on FSL Book-E chips */ 30 #if defined(CONFIG_E500MC) 31 #define CONFIG_SYS_NUM_TLBCAMS 64 32 #elif defined(CONFIG_E500) 33 #define CONFIG_SYS_NUM_TLBCAMS 16 34 #endif 35 36 #if defined(CONFIG_MPC8536) 37 #define CONFIG_MAX_CPUS 1 38 #define CONFIG_SYS_FSL_NUM_LAWS 12 39 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 40 #define CONFIG_SYS_FSL_SEC_COMPAT 2 41 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 42 #define CONFIG_SYS_FSL_ERRATUM_A004508 43 #define CONFIG_SYS_FSL_ERRATUM_A005125 44 45 #elif defined(CONFIG_MPC8540) 46 #define CONFIG_MAX_CPUS 1 47 #define CONFIG_SYS_FSL_NUM_LAWS 8 48 #define CONFIG_SYS_FSL_DDRC_GEN1 49 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 50 51 #elif defined(CONFIG_MPC8541) 52 #define CONFIG_MAX_CPUS 1 53 #define CONFIG_SYS_FSL_NUM_LAWS 8 54 #define CONFIG_SYS_FSL_DDRC_GEN1 55 #define CONFIG_SYS_FSL_SEC_COMPAT 2 56 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 57 58 #elif defined(CONFIG_MPC8544) 59 #define CONFIG_MAX_CPUS 1 60 #define CONFIG_SYS_FSL_NUM_LAWS 10 61 #define CONFIG_SYS_FSL_DDRC_GEN2 62 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 63 #define CONFIG_SYS_FSL_SEC_COMPAT 2 64 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 65 #define CONFIG_SYS_FSL_ERRATUM_A005125 66 67 #elif defined(CONFIG_MPC8548) 68 #define CONFIG_MAX_CPUS 1 69 #define CONFIG_SYS_FSL_NUM_LAWS 10 70 #define CONFIG_SYS_FSL_DDRC_GEN2 71 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 72 #define CONFIG_SYS_FSL_SEC_COMPAT 2 73 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 74 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 75 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 76 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 77 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 78 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 79 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 80 #define CONFIG_SYS_FSL_RMU 81 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 82 #define CONFIG_SYS_FSL_ERRATUM_A005125 83 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 84 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 85 86 #elif defined(CONFIG_MPC8555) 87 #define CONFIG_MAX_CPUS 1 88 #define CONFIG_SYS_FSL_NUM_LAWS 8 89 #define CONFIG_SYS_FSL_DDRC_GEN1 90 #define CONFIG_SYS_FSL_SEC_COMPAT 2 91 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 92 93 #elif defined(CONFIG_MPC8560) 94 #define CONFIG_MAX_CPUS 1 95 #define CONFIG_SYS_FSL_NUM_LAWS 8 96 #define CONFIG_SYS_FSL_DDRC_GEN1 97 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 98 99 #elif defined(CONFIG_MPC8568) 100 #define CONFIG_MAX_CPUS 1 101 #define CONFIG_SYS_FSL_NUM_LAWS 10 102 #define CONFIG_SYS_FSL_DDRC_GEN2 103 #define CONFIG_SYS_FSL_SEC_COMPAT 2 104 #define QE_MURAM_SIZE 0x10000UL 105 #define MAX_QE_RISC 2 106 #define QE_NUM_OF_SNUM 28 107 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 108 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 109 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 110 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 111 #define CONFIG_SYS_FSL_RMU 112 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 113 114 #elif defined(CONFIG_MPC8569) 115 #define CONFIG_MAX_CPUS 1 116 #define CONFIG_SYS_FSL_NUM_LAWS 10 117 #define CONFIG_SYS_FSL_SEC_COMPAT 2 118 #define QE_MURAM_SIZE 0x20000UL 119 #define MAX_QE_RISC 4 120 #define QE_NUM_OF_SNUM 46 121 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 122 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 123 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 124 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 125 #define CONFIG_SYS_FSL_RMU 126 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 127 #define CONFIG_SYS_FSL_ERRATUM_A004508 128 #define CONFIG_SYS_FSL_ERRATUM_A005125 129 130 #elif defined(CONFIG_MPC8572) 131 #define CONFIG_MAX_CPUS 2 132 #define CONFIG_SYS_FSL_NUM_LAWS 12 133 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 134 #define CONFIG_SYS_FSL_SEC_COMPAT 2 135 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 136 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 137 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 138 #define CONFIG_SYS_FSL_ERRATUM_A004508 139 #define CONFIG_SYS_FSL_ERRATUM_A005125 140 141 #elif defined(CONFIG_P1010) 142 #define CONFIG_MAX_CPUS 1 143 #define CONFIG_FSL_SDHC_V2_3 144 #define CONFIG_SYS_FSL_NUM_LAWS 12 145 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 146 #define CONFIG_TSECV2 147 #define CONFIG_SYS_FSL_SEC_COMPAT 4 148 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 149 #define CONFIG_NUM_DDR_CONTROLLERS 1 150 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 151 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 152 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 153 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 154 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 155 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 156 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 157 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 158 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 159 #define CONFIG_SYS_FSL_ERRATUM_A005125 160 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 161 #define CONFIG_SYS_FSL_ERRATUM_A004508 162 #define CONFIG_SYS_FSL_ERRATUM_A007075 163 #define CONFIG_SYS_FSL_ERRATUM_A006261 164 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 165 #define CONFIG_ESDHC_HC_BLK_ADDR 166 167 /* P1011 is single core version of P1020 */ 168 #elif defined(CONFIG_P1011) 169 #define CONFIG_MAX_CPUS 1 170 #define CONFIG_SYS_FSL_NUM_LAWS 12 171 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 172 #define CONFIG_TSECV2 173 #define CONFIG_FSL_PCIE_DISABLE_ASPM 174 #define CONFIG_SYS_FSL_SEC_COMPAT 2 175 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 176 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 177 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 178 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 179 #define CONFIG_SYS_FSL_ERRATUM_A004508 180 #define CONFIG_SYS_FSL_ERRATUM_A005125 181 182 /* P1012 is single core version of P1021 */ 183 #elif defined(CONFIG_P1012) 184 #define CONFIG_MAX_CPUS 1 185 #define CONFIG_SYS_FSL_NUM_LAWS 12 186 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 187 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 188 #define CONFIG_TSECV2 189 #define CONFIG_FSL_PCIE_DISABLE_ASPM 190 #define CONFIG_SYS_FSL_SEC_COMPAT 2 191 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 192 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 193 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 194 #define QE_MURAM_SIZE 0x6000UL 195 #define MAX_QE_RISC 1 196 #define QE_NUM_OF_SNUM 28 197 #define CONFIG_SYS_FSL_ERRATUM_A004508 198 #define CONFIG_SYS_FSL_ERRATUM_A005125 199 200 /* P1013 is single core version of P1022 */ 201 #elif defined(CONFIG_P1013) 202 #define CONFIG_MAX_CPUS 1 203 #define CONFIG_SYS_FSL_NUM_LAWS 12 204 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 205 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 206 #define CONFIG_TSECV2 207 #define CONFIG_SYS_FSL_SEC_COMPAT 2 208 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 209 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 210 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 211 #define CONFIG_FSL_SATA_ERRATUM_A001 212 #define CONFIG_SYS_FSL_ERRATUM_A004508 213 #define CONFIG_SYS_FSL_ERRATUM_A005125 214 215 #elif defined(CONFIG_P1014) 216 #define CONFIG_MAX_CPUS 1 217 #define CONFIG_FSL_SDHC_V2_3 218 #define CONFIG_SYS_FSL_NUM_LAWS 12 219 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 220 #define CONFIG_TSECV2 221 #define CONFIG_SYS_FSL_SEC_COMPAT 4 222 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 223 #define CONFIG_NUM_DDR_CONTROLLERS 1 224 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 225 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 226 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 227 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 228 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 229 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 230 #define CONFIG_SYS_FSL_ERRATUM_A004508 231 232 /* P1017 is single core version of P1023 */ 233 #elif defined(CONFIG_P1017) 234 #define CONFIG_MAX_CPUS 1 235 #define CONFIG_SYS_FSL_NUM_LAWS 12 236 #define CONFIG_SYS_FSL_SEC_COMPAT 4 237 #define CONFIG_SYS_NUM_FMAN 1 238 #define CONFIG_SYS_NUM_FM1_DTSEC 2 239 #define CONFIG_NUM_DDR_CONTROLLERS 1 240 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 241 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 242 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 243 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 244 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 245 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 246 #define CONFIG_SYS_FSL_ERRATUM_A004508 247 #define CONFIG_SYS_FSL_ERRATUM_A005125 248 249 #elif defined(CONFIG_P1020) 250 #define CONFIG_MAX_CPUS 2 251 #define CONFIG_SYS_FSL_NUM_LAWS 12 252 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 253 #define CONFIG_TSECV2 254 #define CONFIG_FSL_PCIE_DISABLE_ASPM 255 #define CONFIG_SYS_FSL_SEC_COMPAT 2 256 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 257 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 258 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 259 #define CONFIG_SYS_FSL_ERRATUM_A004508 260 #define CONFIG_SYS_FSL_ERRATUM_A005125 261 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 262 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 263 #endif 264 265 #elif defined(CONFIG_P1021) 266 #define CONFIG_MAX_CPUS 2 267 #define CONFIG_SYS_FSL_NUM_LAWS 12 268 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 269 #define CONFIG_TSECV2 270 #define CONFIG_FSL_PCIE_DISABLE_ASPM 271 #define CONFIG_SYS_FSL_SEC_COMPAT 2 272 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 273 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 274 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 275 #define QE_MURAM_SIZE 0x6000UL 276 #define MAX_QE_RISC 1 277 #define QE_NUM_OF_SNUM 28 278 #define CONFIG_SYS_FSL_ERRATUM_A004508 279 #define CONFIG_SYS_FSL_ERRATUM_A005125 280 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 281 282 #elif defined(CONFIG_P1022) 283 #define CONFIG_MAX_CPUS 2 284 #define CONFIG_SYS_FSL_NUM_LAWS 12 285 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 286 #define CONFIG_TSECV2 287 #define CONFIG_SYS_FSL_SEC_COMPAT 2 288 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 289 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 290 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 291 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 292 #define CONFIG_FSL_SATA_ERRATUM_A001 293 #define CONFIG_SYS_FSL_ERRATUM_A004508 294 #define CONFIG_SYS_FSL_ERRATUM_A005125 295 296 #elif defined(CONFIG_P1023) 297 #define CONFIG_MAX_CPUS 2 298 #define CONFIG_SYS_FSL_NUM_LAWS 12 299 #define CONFIG_SYS_FSL_SEC_COMPAT 4 300 #define CONFIG_SYS_NUM_FMAN 1 301 #define CONFIG_SYS_NUM_FM1_DTSEC 2 302 #define CONFIG_NUM_DDR_CONTROLLERS 1 303 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 304 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 305 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 306 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 307 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 308 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 309 #define CONFIG_SYS_FSL_ERRATUM_A004508 310 #define CONFIG_SYS_FSL_ERRATUM_A005125 311 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 312 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 313 314 /* P1024 is lower end variant of P1020 */ 315 #elif defined(CONFIG_P1024) 316 #define CONFIG_MAX_CPUS 2 317 #define CONFIG_SYS_FSL_NUM_LAWS 12 318 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 319 #define CONFIG_TSECV2 320 #define CONFIG_FSL_PCIE_DISABLE_ASPM 321 #define CONFIG_SYS_FSL_SEC_COMPAT 2 322 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 323 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 324 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 325 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 326 #define CONFIG_SYS_FSL_ERRATUM_A004508 327 #define CONFIG_SYS_FSL_ERRATUM_A005125 328 329 /* P1025 is lower end variant of P1021 */ 330 #elif defined(CONFIG_P1025) 331 #define CONFIG_MAX_CPUS 2 332 #define CONFIG_SYS_FSL_NUM_LAWS 12 333 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 334 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 335 #define CONFIG_TSECV2 336 #define CONFIG_FSL_PCIE_DISABLE_ASPM 337 #define CONFIG_SYS_FSL_SEC_COMPAT 2 338 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 339 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 340 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 341 #define QE_MURAM_SIZE 0x6000UL 342 #define MAX_QE_RISC 1 343 #define QE_NUM_OF_SNUM 28 344 #define CONFIG_SYS_FSL_ERRATUM_A004508 345 #define CONFIG_SYS_FSL_ERRATUM_A005125 346 347 /* P2010 is single core version of P2020 */ 348 #elif defined(CONFIG_P2010) 349 #define CONFIG_MAX_CPUS 1 350 #define CONFIG_SYS_FSL_NUM_LAWS 12 351 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 352 #define CONFIG_SYS_FSL_SEC_COMPAT 2 353 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 354 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 355 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 356 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 357 #define CONFIG_SYS_FSL_ERRATUM_A004508 358 #define CONFIG_SYS_FSL_ERRATUM_A005125 359 360 #elif defined(CONFIG_P2020) 361 #define CONFIG_MAX_CPUS 2 362 #define CONFIG_SYS_FSL_NUM_LAWS 12 363 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 364 #define CONFIG_SYS_FSL_SEC_COMPAT 2 365 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 366 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 367 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 368 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 369 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 370 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 371 #define CONFIG_SYS_FSL_RMU 372 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 373 #define CONFIG_SYS_FSL_ERRATUM_A004508 374 #define CONFIG_SYS_FSL_ERRATUM_A005125 375 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 376 377 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 378 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 379 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 380 #define CONFIG_MAX_CPUS 4 381 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 382 #define CONFIG_SYS_FSL_NUM_LAWS 32 383 #define CONFIG_SYS_FSL_SEC_COMPAT 4 384 #define CONFIG_SYS_NUM_FMAN 1 385 #define CONFIG_SYS_NUM_FM1_DTSEC 5 386 #define CONFIG_SYS_NUM_FM1_10GEC 1 387 #define CONFIG_NUM_DDR_CONTROLLERS 1 388 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 389 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 390 #define CONFIG_SYS_FSL_TBCLK_DIV 32 391 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 392 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 393 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 394 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 395 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 396 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 397 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 398 #define CONFIG_SYS_FSL_ERRATUM_USB14 399 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 400 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 401 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 402 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 403 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 404 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 405 #define CONFIG_SYS_FSL_ERRATUM_A004510 406 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 407 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 408 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 409 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 410 #define CONFIG_SYS_FSL_ERRATUM_A004849 411 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 412 #define CONFIG_SYS_FSL_ERRATUM_A006261 413 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 414 415 #elif defined(CONFIG_PPC_P3041) 416 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 417 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 418 #define CONFIG_MAX_CPUS 4 419 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 420 #define CONFIG_SYS_FSL_NUM_LAWS 32 421 #define CONFIG_SYS_FSL_SEC_COMPAT 4 422 #define CONFIG_SYS_NUM_FMAN 1 423 #define CONFIG_SYS_NUM_FM1_DTSEC 5 424 #define CONFIG_SYS_NUM_FM1_10GEC 1 425 #define CONFIG_NUM_DDR_CONTROLLERS 1 426 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 427 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 428 #define CONFIG_SYS_FSL_TBCLK_DIV 32 429 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 430 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 431 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 432 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 433 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 434 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 435 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 436 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 437 #define CONFIG_SYS_FSL_ERRATUM_USB14 438 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 439 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 440 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 441 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 442 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 443 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 444 #define CONFIG_SYS_FSL_ERRATUM_A004510 445 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 446 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 447 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 448 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 449 #define CONFIG_SYS_FSL_ERRATUM_A004849 450 #define CONFIG_SYS_FSL_ERRATUM_A005812 451 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 452 #define CONFIG_SYS_FSL_ERRATUM_A006261 453 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 454 455 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 456 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 457 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 458 #define CONFIG_MAX_CPUS 8 459 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 460 #define CONFIG_SYS_FSL_NUM_LAWS 32 461 #define CONFIG_SYS_FSL_SEC_COMPAT 4 462 #define CONFIG_SYS_NUM_FMAN 2 463 #define CONFIG_SYS_NUM_FM1_DTSEC 4 464 #define CONFIG_SYS_NUM_FM2_DTSEC 4 465 #define CONFIG_SYS_NUM_FM1_10GEC 1 466 #define CONFIG_SYS_NUM_FM2_10GEC 1 467 #define CONFIG_NUM_DDR_CONTROLLERS 2 468 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 469 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 470 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 471 #define CONFIG_SYS_FSL_TBCLK_DIV 16 472 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 473 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 474 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 475 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 476 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 477 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 478 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 479 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 480 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 481 #define CONFIG_SYS_P4080_ERRATUM_CPU22 482 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 483 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 484 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 485 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 486 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 487 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 488 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 489 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 490 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 491 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 492 #define CONFIG_SYS_FSL_RMU 493 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 494 #define CONFIG_SYS_FSL_ERRATUM_A004510 495 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 496 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 497 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 498 #define CONFIG_SYS_FSL_ERRATUM_A004849 499 #define CONFIG_SYS_FSL_ERRATUM_A004580 500 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 501 #define CONFIG_SYS_FSL_ERRATUM_A005812 502 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 503 #define CONFIG_SYS_FSL_ERRATUM_A007075 504 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 505 506 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 507 #define CONFIG_SYS_PPC64 /* 64-bit core */ 508 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 509 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 510 #define CONFIG_MAX_CPUS 2 511 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 512 #define CONFIG_SYS_FSL_NUM_LAWS 32 513 #define CONFIG_SYS_FSL_SEC_COMPAT 4 514 #define CONFIG_SYS_NUM_FMAN 1 515 #define CONFIG_SYS_NUM_FM1_DTSEC 5 516 #define CONFIG_SYS_NUM_FM1_10GEC 1 517 #define CONFIG_NUM_DDR_CONTROLLERS 2 518 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 519 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 520 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 521 #define CONFIG_SYS_FSL_TBCLK_DIV 32 522 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 523 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 524 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 525 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 526 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 527 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 528 #define CONFIG_SYS_FSL_ERRATUM_USB14 529 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 530 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 531 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 532 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 533 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 534 #define CONFIG_SYS_FSL_ERRATUM_A004510 535 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 536 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 537 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 538 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 539 #define CONFIG_SYS_FSL_ERRATUM_A006261 540 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 541 542 #elif defined(CONFIG_PPC_P5040) 543 #define CONFIG_SYS_PPC64 544 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 545 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 546 #define CONFIG_MAX_CPUS 4 547 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 548 #define CONFIG_SYS_FSL_NUM_LAWS 32 549 #define CONFIG_SYS_FSL_SEC_COMPAT 4 550 #define CONFIG_SYS_NUM_FMAN 2 551 #define CONFIG_SYS_NUM_FM1_DTSEC 5 552 #define CONFIG_SYS_NUM_FM1_10GEC 1 553 #define CONFIG_SYS_NUM_FM2_DTSEC 5 554 #define CONFIG_SYS_NUM_FM2_10GEC 1 555 #define CONFIG_NUM_DDR_CONTROLLERS 2 556 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 557 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 558 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 559 #define CONFIG_SYS_FSL_TBCLK_DIV 16 560 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 561 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 562 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 563 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 564 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 565 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 566 #define CONFIG_SYS_FSL_ERRATUM_USB14 567 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 568 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 569 #define CONFIG_SYS_FSL_ERRATUM_A004699 570 #define CONFIG_SYS_FSL_ERRATUM_A004510 571 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 572 #define CONFIG_SYS_FSL_ERRATUM_A006261 573 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 574 #define CONFIG_SYS_FSL_ERRATUM_A005812 575 576 #elif defined(CONFIG_BSC9131) 577 #define CONFIG_MAX_CPUS 1 578 #define CONFIG_FSL_SDHC_V2_3 579 #define CONFIG_SYS_FSL_NUM_LAWS 12 580 #define CONFIG_TSECV2 581 #define CONFIG_SYS_FSL_SEC_COMPAT 4 582 #define CONFIG_NUM_DDR_CONTROLLERS 1 583 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 584 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 585 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 586 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 587 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 588 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 589 #define CONFIG_NAND_FSL_IFC 590 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 591 #define CONFIG_SYS_FSL_ERRATUM_A005125 592 #define CONFIG_ESDHC_HC_BLK_ADDR 593 594 #elif defined(CONFIG_BSC9132) 595 #define CONFIG_MAX_CPUS 2 596 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 597 #define CONFIG_FSL_SDHC_V2_3 598 #define CONFIG_SYS_FSL_NUM_LAWS 12 599 #define CONFIG_TSECV2 600 #define CONFIG_SYS_FSL_SEC_COMPAT 4 601 #define CONFIG_NUM_DDR_CONTROLLERS 2 602 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 603 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 604 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 605 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 606 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 607 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 608 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 609 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 610 #define CONFIG_NAND_FSL_IFC 611 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 612 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 613 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 614 #define CONFIG_SYS_FSL_ERRATUM_A005125 615 #define CONFIG_SYS_FSL_ERRATUM_A005434 616 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 617 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 618 #define CONFIG_ESDHC_HC_BLK_ADDR 619 620 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ 621 defined(CONFIG_PPC_T4080) 622 #define CONFIG_E6500 623 #define CONFIG_SYS_PPC64 /* 64-bit core */ 624 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 625 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 626 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 627 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 628 #ifdef CONFIG_PPC_T4240 629 #define CONFIG_MAX_CPUS 12 630 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 631 #define CONFIG_SYS_NUM_FM1_DTSEC 8 632 #define CONFIG_SYS_NUM_FM1_10GEC 2 633 #define CONFIG_SYS_NUM_FM2_DTSEC 8 634 #define CONFIG_SYS_NUM_FM2_10GEC 2 635 #define CONFIG_NUM_DDR_CONTROLLERS 3 636 #else 637 #define CONFIG_SYS_NUM_FM1_DTSEC 6 638 #define CONFIG_SYS_NUM_FM1_10GEC 1 639 #define CONFIG_SYS_NUM_FM2_DTSEC 8 640 #define CONFIG_SYS_NUM_FM2_10GEC 1 641 #define CONFIG_NUM_DDR_CONTROLLERS 2 642 #if defined(CONFIG_PPC_T4160) 643 #define CONFIG_MAX_CPUS 8 644 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 645 #elif defined(CONFIG_PPC_T4080) 646 #define CONFIG_MAX_CPUS 4 647 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } 648 #endif 649 #endif 650 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 651 #define CONFIG_SYS_FSL_NUM_LAWS 32 652 #define CONFIG_SYS_FSL_SRDS_1 653 #define CONFIG_SYS_FSL_SRDS_2 654 #define CONFIG_SYS_FSL_SRDS_3 655 #define CONFIG_SYS_FSL_SRDS_4 656 #define CONFIG_SYS_FSL_SEC_COMPAT 4 657 #define CONFIG_SYS_NUM_FMAN 2 658 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 659 #define CONFIG_SYS_PME_CLK 0 660 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 661 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 662 #define CONFIG_SYS_FMAN_V3 663 #define CONFIG_SYS_FM1_CLK 3 664 #define CONFIG_SYS_FM2_CLK 3 665 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 666 #define CONFIG_SYS_FSL_TBCLK_DIV 16 667 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 668 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 669 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 670 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 671 #define CONFIG_SYS_FSL_SRIO_LIODN 672 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 673 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 674 #define CONFIG_SYS_FSL_ERRATUM_A004468 675 #define CONFIG_SYS_FSL_ERRATUM_A_004934 676 #define CONFIG_SYS_FSL_ERRATUM_A005871 677 #define CONFIG_SYS_FSL_ERRATUM_A006261 678 #define CONFIG_SYS_FSL_ERRATUM_A006379 679 #define CONFIG_SYS_FSL_ERRATUM_A007186 680 #define CONFIG_SYS_FSL_ERRATUM_A006593 681 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 682 #define CONFIG_SYS_FSL_SFP_VER_3_0 683 #define CONFIG_SYS_FSL_PCI_VER_3_X 684 685 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 686 #define CONFIG_E6500 687 #define CONFIG_SYS_PPC64 /* 64-bit core */ 688 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 689 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 690 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 691 #define CONFIG_SYS_FSL_NUM_LAWS 32 692 #define CONFIG_SYS_FSL_SRDS_1 693 #define CONFIG_SYS_FSL_SRDS_2 694 #define CONFIG_SYS_FSL_SEC_COMPAT 4 695 #define CONFIG_SYS_NUM_FMAN 1 696 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 697 #define CONFIG_SYS_FM1_CLK 0 698 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 699 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 700 #define CONFIG_SYS_FMAN_V3 701 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 702 #define CONFIG_SYS_FSL_TBCLK_DIV 16 703 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 704 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 705 #define CONFIG_SYS_FSL_ERRATUM_A_004934 706 #define CONFIG_SYS_FSL_ERRATUM_A005871 707 #define CONFIG_SYS_FSL_ERRATUM_A006379 708 #define CONFIG_SYS_FSL_ERRATUM_A007186 709 #define CONFIG_SYS_FSL_ERRATUM_A006593 710 #define CONFIG_SYS_FSL_ERRATUM_A007075 711 #define CONFIG_SYS_FSL_ERRATUM_A006475 712 #define CONFIG_SYS_FSL_ERRATUM_A006384 713 #define CONFIG_SYS_FSL_ERRATUM_A007212 714 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 715 #define CONFIG_SYS_FSL_SFP_VER_3_0 716 717 #ifdef CONFIG_PPC_B4860 718 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 719 #define CONFIG_MAX_CPUS 4 720 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 721 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 722 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 723 #define CONFIG_SYS_NUM_FM1_DTSEC 6 724 #define CONFIG_SYS_NUM_FM1_10GEC 2 725 #define CONFIG_NUM_DDR_CONTROLLERS 2 726 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 727 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 728 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 729 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 730 #define CONFIG_SYS_FSL_SRIO_LIODN 731 #else 732 #define CONFIG_MAX_CPUS 2 733 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 734 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 735 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 736 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 737 #define CONFIG_SYS_NUM_FM1_DTSEC 4 738 #define CONFIG_SYS_NUM_FM1_10GEC 0 739 #define CONFIG_NUM_DDR_CONTROLLERS 1 740 #endif 741 742 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 743 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 744 #define CONFIG_E5500 745 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 746 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 747 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 748 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 749 #ifdef CONFIG_SYS_FSL_DDR4 750 #define CONFIG_SYS_FSL_DDRC_GEN4 751 #endif 752 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 753 #define CONFIG_MAX_CPUS 4 754 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 755 #define CONFIG_MAX_CPUS 2 756 #endif 757 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 758 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 759 #define CONFIG_SYS_SDHC_CLOCK 0 760 #define CONFIG_SYS_FSL_NUM_LAWS 16 761 #define CONFIG_SYS_FSL_SRDS_1 762 #define CONFIG_SYS_FSL_SEC_COMPAT 5 763 #define CONFIG_SYS_NUM_FMAN 1 764 #define CONFIG_SYS_NUM_FM1_DTSEC 5 765 #define CONFIG_NUM_DDR_CONTROLLERS 1 766 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 767 #define CONFIG_PME_PLAT_CLK_DIV 2 768 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 769 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 770 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 771 #define CONFIG_SYS_FMAN_V3 772 #define CONFIG_FM_PLAT_CLK_DIV 1 773 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 774 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 775 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 776 #define CONFIG_SYS_FSL_TBCLK_DIV 16 777 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 778 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 779 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 780 #define CONFIG_SYS_FSL_ERRATUM_A006261 781 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 782 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 783 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 784 #define QE_MURAM_SIZE 0x6000UL 785 #define MAX_QE_RISC 1 786 #define QE_NUM_OF_SNUM 28 787 788 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 789 #define CONFIG_E6500 790 #define CONFIG_SYS_PPC64 /* 64-bit core */ 791 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 792 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 793 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 794 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 795 #define CONFIG_SYS_FSL_QMAN_V3 796 #define CONFIG_MAX_CPUS 4 797 #define CONFIG_SYS_FSL_NUM_LAWS 32 798 #define CONFIG_SYS_FSL_SEC_COMPAT 4 799 #define CONFIG_SYS_NUM_FMAN 1 800 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 801 #define CONFIG_SYS_FSL_SRDS_1 802 #define CONFIG_SYS_FSL_PCI_VER_3_X 803 #if defined(CONFIG_PPC_T2080) 804 #define CONFIG_SYS_NUM_FM1_DTSEC 8 805 #define CONFIG_SYS_NUM_FM1_10GEC 4 806 #define CONFIG_SYS_FSL_SRDS_2 807 #define CONFIG_SYS_FSL_SRIO_LIODN 808 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 809 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 810 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 811 #elif defined(CONFIG_PPC_T2081) 812 #define CONFIG_SYS_NUM_FM1_DTSEC 6 813 #define CONFIG_SYS_NUM_FM1_10GEC 2 814 #endif 815 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 816 #define CONFIG_NUM_DDR_CONTROLLERS 1 817 #define CONFIG_PME_PLAT_CLK_DIV 1 818 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 819 #define CONFIG_SYS_FM1_CLK 0 820 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 821 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 822 #define CONFIG_SYS_FMAN_V3 823 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 824 #define CONFIG_SYS_FSL_TBCLK_DIV 16 825 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 826 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 827 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 828 #define CONFIG_SYS_FSL_ERRATUM_A007212 829 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 830 #define CONFIG_SYS_FSL_SFP_VER_3_0 831 #define CONFIG_SYS_FSL_ISBC_VER 2 832 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 833 #define CONFIG_SYS_FSL_ERRATUM_A006261 834 #define CONFIG_SYS_FSL_ERRATUM_A006593 835 #define CONFIG_SYS_FSL_ERRATUM_A007186 836 #define CONFIG_SYS_FSL_ERRATUM_A006379 837 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 838 #define CONFIG_SYS_FSL_SFP_VER_3_0 839 840 841 #elif defined(CONFIG_PPC_C29X) 842 #define CONFIG_MAX_CPUS 1 843 #define CONFIG_FSL_SDHC_V2_3 844 #define CONFIG_SYS_FSL_NUM_LAWS 12 845 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 846 #define CONFIG_TSECV2_1 847 #define CONFIG_SYS_FSL_SEC_COMPAT 6 848 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 849 #define CONFIG_NUM_DDR_CONTROLLERS 1 850 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 851 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 852 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 853 #define CONFIG_SYS_FSL_ERRATUM_A005125 854 855 #elif defined(CONFIG_QEMU_E500) 856 #define CONFIG_MAX_CPUS 1 857 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 858 859 #else 860 #error Processor type not defined for this platform 861 #endif 862 863 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 864 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 865 #endif 866 867 #ifdef CONFIG_E6500 868 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 869 #else 870 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 871 #endif 872 873 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 874 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 875 !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ 876 !defined(CONFIG_SYS_FSL_DDRC_GEN4) 877 #define CONFIG_SYS_FSL_DDRC_GEN3 878 #endif 879 880 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 881