1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_CONFIG_H_ 22 #define _ASM_CONFIG_H_ 23 24 #ifdef CONFIG_MPC85xx 25 #include <asm/config_mpc85xx.h> 26 #endif 27 28 #ifdef CONFIG_MPC86xx 29 #include <asm/config_mpc86xx.h> 30 #endif 31 32 #define CONFIG_LMB 33 #define CONFIG_SYS_BOOT_RAMDISK_HIGH 34 #define CONFIG_SYS_BOOT_GET_CMDLINE 35 #define CONFIG_SYS_BOOT_GET_KBD 36 37 #ifndef CONFIG_MAX_MEM_MAPPED 38 #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 39 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 40 #else 41 #define CONFIG_MAX_MEM_MAPPED (256 << 20) 42 #endif 43 #endif 44 45 /* Check if boards need to enable FSL DMA engine for SDRAM init */ 46 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 47 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 48 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 49 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 50 #define CONFIG_FSL_DMA 51 #endif 52 #endif 53 54 #ifndef CONFIG_MAX_CPUS 55 #define CONFIG_MAX_CPUS 1 56 #endif 57 58 /* 59 * Provide a default boot page translation virtual address that lines up with 60 * Freescale's default e500 reset page. 61 */ 62 #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 63 #ifndef CONFIG_BPTR_VIRT_ADDR 64 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 65 #endif 66 #endif 67 68 /* 69 * SEC (crypto unit) major compatible version determination 70 */ 71 #if defined(CONFIG_MPC83xx) 72 #define CONFIG_SYS_FSL_SEC_COMPAT 2 73 #endif 74 75 /* Since so many PPC SOCs have a semi-common LBC, define this here */ 76 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 77 defined(CONFIG_MPC83xx) 78 #if !defined(CONFIG_FSL_IFC) 79 #define CONFIG_FSL_LBC 80 #endif 81 #endif 82 83 /* All PPC boards must swap IDE bytes */ 84 #define CONFIG_IDE_SWAP_IO 85 86 #endif /* _ASM_CONFIG_H_ */ 87