xref: /openbmc/u-boot/arch/powerpc/include/asm/config.h (revision d66ff4ba)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef _ASM_CONFIG_H_
7 #define _ASM_CONFIG_H_
8 
9 #ifdef CONFIG_MPC85xx
10 #include <asm/config_mpc85xx.h>
11 #endif
12 
13 #ifdef CONFIG_MPC86xx
14 #include <asm/config_mpc86xx.h>
15 #endif
16 
17 #ifndef HWCONFIG_BUFFER_SIZE
18   #define HWCONFIG_BUFFER_SIZE 256
19 #endif
20 
21 #define CONFIG_LMB
22 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
23 
24 #ifndef CONFIG_MAX_MEM_MAPPED
25 #if	defined(CONFIG_E500)		|| \
26 	defined(CONFIG_MPC86xx)		|| \
27 	defined(CONFIG_E300)
28 #define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
29 #else
30 #define CONFIG_MAX_MEM_MAPPED	(256 << 20)
31 #endif
32 #endif
33 
34 /* Check if boards need to enable FSL DMA engine for SDRAM init */
35 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
36 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
37 	((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
38 	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
39 #define CONFIG_FSL_DMA
40 #endif
41 #endif
42 
43 /*
44  * Provide a default boot page translation virtual address that lines up with
45  * Freescale's default e500 reset page.
46  */
47 #if (defined(CONFIG_E500) && defined(CONFIG_MP))
48 #ifndef CONFIG_BPTR_VIRT_ADDR
49 #define CONFIG_BPTR_VIRT_ADDR	0xfffff000
50 #endif
51 #endif
52 
53 /* Since so many PPC SOCs have a semi-common LBC, define this here */
54 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
55 	defined(CONFIG_MPC83xx)
56 #if !defined(CONFIG_FSL_IFC)
57 #define CONFIG_FSL_LBC
58 #endif
59 #endif
60 
61 /* The TSEC driver uses the PHYLIB infrastructure */
62 #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
63 #include <config_phylib_all_drivers.h>
64 #endif /* TSEC_ENET */
65 
66 /* The FMAN driver uses the PHYLIB infrastructure */
67 
68 /* All PPC boards must swap IDE bytes */
69 #define CONFIG_IDE_SWAP_IO
70 
71 #if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
72 /*
73  * TODO: Convert this to a clock driver exists that can give us the UART
74  * clock here.
75  */
76 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()
77 #endif
78 
79 #endif /* _ASM_CONFIG_H_ */
80