1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_CONFIG_H_ 8 #define _ASM_CONFIG_H_ 9 10 #ifdef CONFIG_MPC85xx 11 #include <asm/config_mpc85xx.h> 12 #endif 13 14 #ifdef CONFIG_MPC86xx 15 #include <asm/config_mpc86xx.h> 16 #endif 17 18 #ifdef CONFIG_MPC83xx 19 #endif 20 21 #ifndef HWCONFIG_BUFFER_SIZE 22 #define HWCONFIG_BUFFER_SIZE 256 23 #endif 24 25 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 26 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 27 # ifndef CONFIG_HARD_SPI 28 # define CONFIG_HARD_SPI 29 # endif 30 #endif 31 32 #define CONFIG_LMB 33 #define CONFIG_SYS_BOOT_RAMDISK_HIGH 34 #define CONFIG_SYS_BOOT_GET_CMDLINE 35 #define CONFIG_SYS_BOOT_GET_KBD 36 37 #ifndef CONFIG_MAX_MEM_MAPPED 38 #if defined(CONFIG_4xx) || \ 39 defined(CONFIG_E500) || \ 40 defined(CONFIG_MPC86xx) || \ 41 defined(CONFIG_E300) 42 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 43 #else 44 #define CONFIG_MAX_MEM_MAPPED (256 << 20) 45 #endif 46 #endif 47 48 /* Check if boards need to enable FSL DMA engine for SDRAM init */ 49 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 50 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 51 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 52 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 53 #define CONFIG_FSL_DMA 54 #endif 55 #endif 56 57 /* 58 * Provide a default boot page translation virtual address that lines up with 59 * Freescale's default e500 reset page. 60 */ 61 #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 62 #ifndef CONFIG_BPTR_VIRT_ADDR 63 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 64 #endif 65 #endif 66 67 /* Since so many PPC SOCs have a semi-common LBC, define this here */ 68 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 69 defined(CONFIG_MPC83xx) 70 #if !defined(CONFIG_FSL_IFC) 71 #define CONFIG_FSL_LBC 72 #endif 73 #endif 74 75 /* The TSEC driver uses the PHYLIB infrastructure */ 76 #ifndef CONFIG_PHYLIB 77 #if defined(CONFIG_TSEC_ENET) 78 #define CONFIG_PHYLIB 79 80 #include <config_phylib_all_drivers.h> 81 #endif /* TSEC_ENET */ 82 #endif /* !CONFIG_PHYLIB */ 83 84 /* The FMAN driver uses the PHYLIB infrastructure */ 85 #if defined(CONFIG_FMAN_ENET) 86 #define CONFIG_PHYLIB 87 #endif 88 89 /* All PPC boards must swap IDE bytes */ 90 #define CONFIG_IDE_SWAP_IO 91 92 #if defined(CONFIG_DM_SERIAL) 93 /* 94 * TODO: Convert this to a clock driver exists that can give us the UART 95 * clock here. 96 */ 97 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 98 #endif 99 100 #endif /* _ASM_CONFIG_H_ */ 101