1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 */ 20 21 #ifndef _ASM_CONFIG_H_ 22 #define _ASM_CONFIG_H_ 23 24 #ifdef CONFIG_MPC85xx 25 #include <asm/config_mpc85xx.h> 26 #endif 27 28 #ifdef CONFIG_MPC86xx 29 #include <asm/config_mpc86xx.h> 30 #endif 31 32 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 33 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 34 # ifndef CONFIG_HARD_SPI 35 # define CONFIG_HARD_SPI 36 # endif 37 #endif 38 39 #define CONFIG_LMB 40 #define CONFIG_SYS_BOOT_RAMDISK_HIGH 41 #define CONFIG_SYS_BOOT_GET_CMDLINE 42 #define CONFIG_SYS_BOOT_GET_KBD 43 44 #ifndef CONFIG_MAX_MEM_MAPPED 45 #if defined(CONFIG_4xx) || \ 46 defined(CONFIG_E500) || \ 47 defined(CONFIG_MPC86xx) || \ 48 defined(CONFIG_E300) 49 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 50 #else 51 #define CONFIG_MAX_MEM_MAPPED (256 << 20) 52 #endif 53 #endif 54 55 /* Check if boards need to enable FSL DMA engine for SDRAM init */ 56 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 57 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 58 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 59 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 60 #define CONFIG_FSL_DMA 61 #endif 62 #endif 63 64 #ifndef CONFIG_MAX_CPUS 65 #define CONFIG_MAX_CPUS 1 66 #endif 67 68 /* 69 * Provide a default boot page translation virtual address that lines up with 70 * Freescale's default e500 reset page. 71 */ 72 #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 73 #ifndef CONFIG_BPTR_VIRT_ADDR 74 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 75 #endif 76 #endif 77 78 /* 79 * SEC (crypto unit) major compatible version determination 80 */ 81 #if defined(CONFIG_MPC83xx) 82 #define CONFIG_SYS_FSL_SEC_COMPAT 2 83 #endif 84 85 /* Since so many PPC SOCs have a semi-common LBC, define this here */ 86 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 87 defined(CONFIG_MPC83xx) 88 #if !defined(CONFIG_FSL_IFC) 89 #define CONFIG_FSL_LBC 90 #endif 91 #endif 92 93 /* The TSEC driver uses the PHYLIB infrastructure */ 94 #ifndef CONFIG_PHYLIB 95 #if defined(CONFIG_TSEC_ENET) 96 #define CONFIG_PHYLIB 97 98 #include <config_phylib_all_drivers.h> 99 #endif /* TSEC_ENET */ 100 #endif /* !CONFIG_PHYLIB */ 101 102 /* The FMAN driver uses the PHYLIB infrastructure */ 103 #if defined(CONFIG_FMAN_ENET) 104 #define CONFIG_PHYLIB 105 #endif 106 107 /* All PPC boards must swap IDE bytes */ 108 #define CONFIG_IDE_SWAP_IO 109 110 #endif /* _ASM_CONFIG_H_ */ 111