1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_CONFIG_H_ 8 #define _ASM_CONFIG_H_ 9 10 #ifdef CONFIG_MPC85xx 11 #include <asm/config_mpc85xx.h> 12 #endif 13 14 #ifdef CONFIG_MPC86xx 15 #include <asm/config_mpc86xx.h> 16 #endif 17 18 #ifndef HWCONFIG_BUFFER_SIZE 19 #define HWCONFIG_BUFFER_SIZE 256 20 #endif 21 22 /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ 23 #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) 24 # ifndef CONFIG_HARD_SPI 25 # define CONFIG_HARD_SPI 26 # endif 27 #endif 28 29 #define CONFIG_LMB 30 #define CONFIG_SYS_BOOT_RAMDISK_HIGH 31 #define CONFIG_SYS_BOOT_GET_CMDLINE 32 #define CONFIG_SYS_BOOT_GET_KBD 33 34 #ifndef CONFIG_MAX_MEM_MAPPED 35 #if defined(CONFIG_4xx) || \ 36 defined(CONFIG_E500) || \ 37 defined(CONFIG_MPC86xx) || \ 38 defined(CONFIG_E300) 39 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 40 #else 41 #define CONFIG_MAX_MEM_MAPPED (256 << 20) 42 #endif 43 #endif 44 45 /* Check if boards need to enable FSL DMA engine for SDRAM init */ 46 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) 47 #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ 48 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ 49 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) 50 #define CONFIG_FSL_DMA 51 #endif 52 #endif 53 54 #ifndef CONFIG_MAX_CPUS 55 #define CONFIG_MAX_CPUS 1 56 #endif 57 58 /* 59 * Provide a default boot page translation virtual address that lines up with 60 * Freescale's default e500 reset page. 61 */ 62 #if (defined(CONFIG_E500) && defined(CONFIG_MP)) 63 #ifndef CONFIG_BPTR_VIRT_ADDR 64 #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 65 #endif 66 #endif 67 68 /* 69 * SEC (crypto unit) major compatible version determination 70 */ 71 #if defined(CONFIG_MPC83xx) 72 #define CONFIG_SYS_FSL_SEC_COMPAT 2 73 #endif 74 75 /* Since so many PPC SOCs have a semi-common LBC, define this here */ 76 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ 77 defined(CONFIG_MPC83xx) 78 #if !defined(CONFIG_FSL_IFC) 79 #define CONFIG_FSL_LBC 80 #endif 81 #endif 82 83 /* The TSEC driver uses the PHYLIB infrastructure */ 84 #ifndef CONFIG_PHYLIB 85 #if defined(CONFIG_TSEC_ENET) 86 #define CONFIG_PHYLIB 87 88 #include <config_phylib_all_drivers.h> 89 #endif /* TSEC_ENET */ 90 #endif /* !CONFIG_PHYLIB */ 91 92 /* The FMAN driver uses the PHYLIB infrastructure */ 93 #if defined(CONFIG_FMAN_ENET) 94 #define CONFIG_PHYLIB 95 #endif 96 97 /* All PPC boards must swap IDE bytes */ 98 #define CONFIG_IDE_SWAP_IO 99 100 #endif /* _ASM_CONFIG_H_ */ 101