1 /* 2 * include/asm-ppc/cache.h 3 */ 4 #ifndef __ARCH_PPC_CACHE_H 5 #define __ARCH_PPC_CACHE_H 6 7 #include <linux/config.h> 8 #include <asm/processor.h> 9 10 /* bytes per L1 cache line */ 11 #if defined(CONFIG_8xx) || defined(CONFIG_IOP480) 12 #define L1_CACHE_SHIFT 4 13 #elif defined(CONFIG_PPC64BRIDGE) 14 #define L1_CACHE_SHIFT 7 15 #elif defined(CONFIG_E500MC) 16 #define L1_CACHE_SHIFT 6 17 #else 18 #define L1_CACHE_SHIFT 5 19 #endif 20 21 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 22 23 /* 24 * Use the L1 data cache line size value for the minimum DMA buffer alignment 25 * on PowerPC. 26 */ 27 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 28 29 /* 30 * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too 31 */ 32 #ifndef CONFIG_SYS_CACHELINE_SIZE 33 #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES 34 #endif 35 36 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) 37 #define L1_CACHE_PAGES 8 38 39 #define SMP_CACHE_BYTES L1_CACHE_BYTES 40 41 #ifdef MODULE 42 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) 43 #else 44 #define __cacheline_aligned \ 45 __attribute__((__aligned__(L1_CACHE_BYTES), \ 46 __section__(".data.cacheline_aligned"))) 47 #endif 48 49 #if defined(__KERNEL__) && !defined(__ASSEMBLY__) 50 extern void flush_dcache_range(unsigned long start, unsigned long stop); 51 extern void clean_dcache_range(unsigned long start, unsigned long stop); 52 extern void invalidate_dcache_range(unsigned long start, unsigned long stop); 53 extern void flush_dcache(void); 54 extern void invalidate_dcache(void); 55 extern void invalidate_icache(void); 56 #ifdef CONFIG_SYS_INIT_RAM_LOCK 57 extern void unlock_ram_in_cache(void); 58 #endif /* CONFIG_SYS_INIT_RAM_LOCK */ 59 #endif /* __ASSEMBLY__ */ 60 61 /* prep registers for L2 */ 62 #define CACHECRBA 0x80000823 /* Cache configuration register address */ 63 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ 64 #define L2CACHE_512KB 0x00 /* 512KB */ 65 #define L2CACHE_256KB 0x01 /* 256KB */ 66 #define L2CACHE_1MB 0x02 /* 1MB */ 67 #define L2CACHE_NONE 0x03 /* NONE */ 68 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ 69 70 #ifdef CONFIG_8xx 71 /* Cache control on the MPC8xx is provided through some additional 72 * special purpose registers. 73 */ 74 #define IC_CST 560 /* Instruction cache control/status */ 75 #define IC_ADR 561 /* Address needed for some commands */ 76 #define IC_DAT 562 /* Read-only data register */ 77 #define DC_CST 568 /* Data cache control/status */ 78 #define DC_ADR 569 /* Address needed for some commands */ 79 #define DC_DAT 570 /* Read-only data register */ 80 81 /* Commands. Only the first few are available to the instruction cache. 82 */ 83 #define IDC_ENABLE 0x02000000 /* Cache enable */ 84 #define IDC_DISABLE 0x04000000 /* Cache disable */ 85 #define IDC_LDLCK 0x06000000 /* Load and lock */ 86 #define IDC_UNLINE 0x08000000 /* Unlock line */ 87 #define IDC_UNALL 0x0a000000 /* Unlock all */ 88 #define IDC_INVALL 0x0c000000 /* Invalidate all */ 89 90 #define DC_FLINE 0x0e000000 /* Flush data cache line */ 91 #define DC_SFWT 0x01000000 /* Set forced writethrough mode */ 92 #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ 93 #define DC_SLES 0x05000000 /* Set little endian swap mode */ 94 #define DC_CLES 0x07000000 /* Clear little endian swap mode */ 95 96 /* Status. 97 */ 98 #define IDC_ENABLED 0x80000000 /* Cache is enabled */ 99 #define IDC_CERR1 0x00200000 /* Cache error 1 */ 100 #define IDC_CERR2 0x00100000 /* Cache error 2 */ 101 #define IDC_CERR3 0x00080000 /* Cache error 3 */ 102 103 #define DC_DFWT 0x40000000 /* Data cache is forced write through */ 104 #define DC_LES 0x20000000 /* Caches are little endian mode */ 105 #endif /* CONFIG_8xx */ 106 107 #endif 108