1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * T2080/T2081 Silicon/SoC Device Tree Source (pre include) 4 * 5 * Copyright 2013 Freescale Semiconductor Inc. 6 * Copyright 2018 NXP 7 */ 8 9/dts-v1/; 10 11/include/ "e6500_power_isa.dtsi" 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&mpic>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: PowerPC,e6500@0 { 23 device_type = "cpu"; 24 reg = <0 1>; 25 fsl,portid-mapping = <0x80000000>; 26 }; 27 cpu1: PowerPC,e6500@2 { 28 device_type = "cpu"; 29 reg = <2 3>; 30 fsl,portid-mapping = <0x80000000>; 31 }; 32 cpu2: PowerPC,e6500@4 { 33 device_type = "cpu"; 34 reg = <4 5>; 35 fsl,portid-mapping = <0x80000000>; 36 }; 37 cpu3: PowerPC,e6500@6 { 38 device_type = "cpu"; 39 reg = <6 7>; 40 fsl,portid-mapping = <0x80000000>; 41 }; 42 }; 43 44 soc: soc@ffe000000 { 45 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 46 reg = <0xf 0xfe000000 0 0x00001000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 device_type = "soc"; 50 compatible = "simple-bus"; 51 52 mpic: pic@40000 { 53 interrupt-controller; 54 #address-cells = <0>; 55 #interrupt-cells = <4>; 56 reg = <0x40000 0x40000>; 57 compatible = "fsl,mpic"; 58 device_type = "open-pic"; 59 clock-frequency = <0x0>; 60 }; 61 }; 62}; 63