1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20 #include <common.h> 21 #include <config.h> 22 #include <asm/fsl_law.h> 23 #include <asm/fsl_serdes.h> 24 #include <asm/fsl_srio.h> 25 #include <asm/errno.h> 26 27 #define SRIO_PORT_ACCEPT_ALL 0x10000001 28 #define SRIO_IB_ATMU_AR 0x80f55000 29 #define SRIO_OB_ATMU_AR_MAINT 0x80077000 30 #define SRIO_OB_ATMU_AR_RW 0x80045000 31 #define SRIO_LCSBA1CSR_OFFSET 0x5c 32 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ 33 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ 34 #define SRIO_LCSBA1CSR 0x60000000 35 36 #if defined(CONFIG_FSL_CORENET) 37 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 38 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1 39 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2 40 #else 41 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 42 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 43 #endif 44 #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU 45 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 46 #elif defined(CONFIG_MPC85xx) 47 #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO 48 #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO 49 #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG 50 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR 51 #elif defined(CONFIG_MPC86xx) 52 #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO 53 #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO 54 #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG 55 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ 56 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) 57 #else 58 #error "No defines for DEVDISR_SRIO" 59 #endif 60 61 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 62 /* 63 * Erratum A-004034 64 * Affects: SRIO 65 * Description: During port initialization, the SRIO port performs 66 * lane synchronization (detecting valid symbols on a lane) and 67 * lane alignment (coordinating multiple lanes to receive valid data 68 * across lanes). Internal errors in lane synchronization and lane 69 * alignment may cause failure to achieve link initialization at 70 * the configured port width. 71 * An SRIO port configured as a 4x port may see one of these scenarios: 72 * 1. One or more lanes fails to achieve lane synchronization. Depending 73 * on which lanes fail, this may result in downtraining from 4x to 1x 74 * on lane 0, 4x to 1x on lane R (redundant lane). 75 * 2. The link may fail to achieve lane alignment as a 4x, even though 76 * all 4 lanes achieve lane synchronization, and downtrain to a 1x. 77 * An SRIO port configured as a 1x port may fail to complete port 78 * initialization (PnESCSR[PU] never deasserts) because of scenario 1. 79 * Impact: SRIO port may downtrain to 1x, or may fail to complete 80 * link initialization. Once a port completes link initialization 81 * successfully, it will operate normally. 82 */ 83 static int srio_erratum_a004034(u8 port) 84 { 85 serdes_corenet_t *srds_regs; 86 u32 conf_lane; 87 u32 init_lane; 88 int idx, first, last; 89 u32 i; 90 unsigned long long end_tick; 91 struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR; 92 93 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); 94 conf_lane = (in_be32((void *)&srds_regs->srdspccr0) 95 >> (12 - port * 4)) & 0x3; 96 init_lane = (in_be32((void *)&srio_regs->lp_serial 97 .port[port].pccsr) >> 27) & 0x7; 98 99 /* 100 * Start a counter set to ~2 ms after the SERDES reset is 101 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n 102 * corresponding to the SERDES bank/PLL for the SRIO port). 103 */ 104 if (in_be32((void *)&srds_regs->bank[0].rstctl) 105 & SRDS_RSTCTL_RSTDONE) { 106 /* 107 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until 108 * PO=1 or the counter expires. If the counter expires, the 109 * port has failed initialization: go to recover steps. If PO=1 110 * and the desired port width is 1x, go to normal steps. If 111 * PO = 1 and the desired port width is 4x, go to recover steps. 112 */ 113 end_tick = usec2ticks(2000) + get_ticks(); 114 do { 115 if (in_be32((void *)&srio_regs->lp_serial 116 .port[port].pescsr) & 0x2) { 117 if (conf_lane == 0x1) 118 goto host_ok; 119 else { 120 if (init_lane == 0x2) 121 goto host_ok; 122 else 123 break; 124 } 125 } 126 } while (end_tick > get_ticks()); 127 128 /* recover at most 3 times */ 129 for (i = 0; i < 3; i++) { 130 /* Set SRIO PnCCSR[PD]=1 */ 131 setbits_be32((void *)&srio_regs->lp_serial 132 .port[port].pccsr, 133 0x800000); 134 /* 135 * Set SRIO PnPCR[OBDEN] on the host to 136 * enable the discarding of any pending packets. 137 */ 138 setbits_be32((void *)&srio_regs->impl.port[port].pcr, 139 0x04); 140 /* Wait 50 us */ 141 udelay(50); 142 /* Run sync command */ 143 isync(); 144 145 if (port) 146 first = serdes_get_first_lane(SRIO2); 147 else 148 first = serdes_get_first_lane(SRIO1); 149 if (unlikely(first < 0)) 150 return -ENODEV; 151 if (conf_lane == 0x1) 152 last = first; 153 else 154 last = first + 3; 155 /* 156 * Set SERDES BnGCRm0[RRST]=0 for each SRIO 157 * bank n and lane m. 158 */ 159 for (idx = first; idx <= last; idx++) 160 clrbits_be32(&srds_regs->lane[idx].gcr0, 161 SRDS_GCR0_RRST); 162 /* 163 * Read SERDES BnGCRm0 for each SRIO 164 * bank n and lane m 165 */ 166 for (idx = first; idx <= last; idx++) 167 in_be32(&srds_regs->lane[idx].gcr0); 168 /* Run sync command */ 169 isync(); 170 /* Wait >= 100 ns */ 171 udelay(1); 172 /* 173 * Set SERDES BnGCRm0[RRST]=1 for each SRIO 174 * bank n and lane m. 175 */ 176 for (idx = first; idx <= last; idx++) 177 setbits_be32(&srds_regs->lane[idx].gcr0, 178 SRDS_GCR0_RRST); 179 /* 180 * Read SERDES BnGCRm0 for each SRIO 181 * bank n and lane m 182 */ 183 for (idx = first; idx <= last; idx++) 184 in_be32(&srds_regs->lane[idx].gcr0); 185 /* Run sync command */ 186 isync(); 187 /* Wait >= 300 ns */ 188 udelay(1); 189 190 /* Write 1 to clear all bits in SRIO PnSLCSR */ 191 out_be32((void *)&srio_regs->impl.port[port].slcsr, 192 0xffffffff); 193 /* Clear SRIO PnPCR[OBDEN] on the host */ 194 clrbits_be32((void *)&srio_regs->impl.port[port].pcr, 195 0x04); 196 /* Set SRIO PnCCSR[PD]=0 */ 197 clrbits_be32((void *)&srio_regs->lp_serial 198 .port[port].pccsr, 199 0x800000); 200 /* Wait >= 24 ms */ 201 udelay(24000); 202 /* Poll the state of the port again */ 203 init_lane = 204 (in_be32((void *)&srio_regs->lp_serial 205 .port[port].pccsr) >> 27) & 0x7; 206 if (in_be32((void *)&srio_regs->lp_serial 207 .port[port].pescsr) & 0x2) { 208 if (conf_lane == 0x1) 209 goto host_ok; 210 else { 211 if (init_lane == 0x2) 212 goto host_ok; 213 } 214 } 215 if (i == 2) 216 return -ENODEV; 217 } 218 } else 219 return -ENODEV; 220 221 host_ok: 222 /* Poll PnESCSR[OES] on the host until it is clear */ 223 end_tick = usec2ticks(1000000) + get_ticks(); 224 do { 225 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr) 226 & 0x10000)) { 227 out_be32(((void *)&srio_regs->lp_serial 228 .port[port].pescsr), 0xffffffff); 229 out_be32(((void *)&srio_regs->phys_err 230 .port[port].edcsr), 0); 231 out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0); 232 return 0; 233 } 234 } while (end_tick > get_ticks()); 235 236 return -ENODEV; 237 } 238 #endif 239 240 void srio_init(void) 241 { 242 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; 243 int srio1_used = 0, srio2_used = 0; 244 u32 *devdisr; 245 246 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 247 devdisr = &gur->devdisr3; 248 #else 249 devdisr = &gur->devdisr; 250 #endif 251 if (is_serdes_configured(SRIO1)) { 252 set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, 253 law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), 254 LAW_TRGT_IF_RIO_1); 255 srio1_used = 1; 256 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 257 if (srio_erratum_a004034(0) < 0) 258 printf("SRIO1: enabled but port error\n"); 259 else 260 #endif 261 printf("SRIO1: enabled\n"); 262 } else { 263 printf("SRIO1: disabled\n"); 264 } 265 266 #ifdef CONFIG_SRIO2 267 if (is_serdes_configured(SRIO2)) { 268 set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, 269 law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), 270 LAW_TRGT_IF_RIO_2); 271 srio2_used = 1; 272 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 273 if (srio_erratum_a004034(1) < 0) 274 printf("SRIO2: enabled but port error\n"); 275 else 276 #endif 277 printf("SRIO2: enabled\n"); 278 279 } else { 280 printf("SRIO2: disabled\n"); 281 } 282 #endif 283 284 #ifdef CONFIG_FSL_CORENET 285 /* On FSL_CORENET devices we can disable individual ports */ 286 if (!srio1_used) 287 setbits_be32(devdisr, _DEVDISR_SRIO1); 288 if (!srio2_used) 289 setbits_be32(devdisr, _DEVDISR_SRIO2); 290 #endif 291 292 /* neither port is used - disable everything */ 293 if (!srio1_used && !srio2_used) { 294 setbits_be32(devdisr, _DEVDISR_SRIO1); 295 setbits_be32(devdisr, _DEVDISR_SRIO2); 296 setbits_be32(devdisr, _DEVDISR_RMU); 297 } 298 } 299 300 #ifdef CONFIG_FSL_CORENET 301 void srio_boot_master(int port) 302 { 303 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; 304 305 /* set port accept-all */ 306 out_be32((void *)&srio->impl.port[port - 1].ptaacr, 307 SRIO_PORT_ACCEPT_ALL); 308 309 debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port); 310 /* configure inbound window for slave's u-boot image */ 311 debug("SRIOBOOT - MASTER: Inbound window for slave's image; " 312 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", 313 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 314 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, 315 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 316 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, 317 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); 318 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, 319 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); 320 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, 321 SRIO_IB_ATMU_AR 322 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); 323 324 /* configure inbound window for slave's u-boot image */ 325 debug("SRIOBOOT - MASTER: Inbound window for slave's image; " 326 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", 327 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, 328 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, 329 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); 330 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, 331 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); 332 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, 333 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); 334 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar, 335 SRIO_IB_ATMU_AR 336 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); 337 338 /* configure inbound window for slave's ucode and ENV */ 339 debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; " 340 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", 341 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, 342 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, 343 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); 344 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar, 345 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); 346 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar, 347 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); 348 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar, 349 SRIO_IB_ATMU_AR 350 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); 351 } 352 353 void srio_boot_master_release_slave(int port) 354 { 355 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; 356 u32 escsr; 357 debug("SRIOBOOT - MASTER: " 358 "Check the port status and release slave core ...\n"); 359 360 escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr); 361 if (escsr & 0x2) { 362 if (escsr & 0x10100) { 363 debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n", 364 port); 365 } else { 366 debug("SRIOBOOT - MASTER: " 367 "Port [ %d ] is ready, now release slave's core ...\n", 368 port); 369 /* 370 * configure outbound window 371 * with maintenance attribute to set slave's LCSBA1CSR 372 */ 373 out_be32((void *)&srio->atmu.port[port - 1] 374 .outbw[1].rowtar, 0); 375 out_be32((void *)&srio->atmu.port[port - 1] 376 .outbw[1].rowtear, 0); 377 if (port - 1) 378 out_be32((void *)&srio->atmu.port[port - 1] 379 .outbw[1].rowbar, 380 CONFIG_SYS_SRIO2_MEM_PHYS >> 12); 381 else 382 out_be32((void *)&srio->atmu.port[port - 1] 383 .outbw[1].rowbar, 384 CONFIG_SYS_SRIO1_MEM_PHYS >> 12); 385 out_be32((void *)&srio->atmu.port[port - 1] 386 .outbw[1].rowar, 387 SRIO_OB_ATMU_AR_MAINT 388 | atmu_size_mask(SRIO_MAINT_WIN_SIZE)); 389 390 /* 391 * configure outbound window 392 * with R/W attribute to set slave's BRR 393 */ 394 out_be32((void *)&srio->atmu.port[port - 1] 395 .outbw[2].rowtar, 396 SRIO_LCSBA1CSR >> 9); 397 out_be32((void *)&srio->atmu.port[port - 1] 398 .outbw[2].rowtear, 0); 399 if (port - 1) 400 out_be32((void *)&srio->atmu.port[port - 1] 401 .outbw[2].rowbar, 402 (CONFIG_SYS_SRIO2_MEM_PHYS 403 + SRIO_MAINT_WIN_SIZE) >> 12); 404 else 405 out_be32((void *)&srio->atmu.port[port - 1] 406 .outbw[2].rowbar, 407 (CONFIG_SYS_SRIO1_MEM_PHYS 408 + SRIO_MAINT_WIN_SIZE) >> 12); 409 out_be32((void *)&srio->atmu.port[port - 1] 410 .outbw[2].rowar, 411 SRIO_OB_ATMU_AR_RW 412 | atmu_size_mask(SRIO_RW_WIN_SIZE)); 413 414 /* 415 * Set the LCSBA1CSR register in slave 416 * by the maint-outbound window 417 */ 418 if (port - 1) { 419 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT 420 + SRIO_LCSBA1CSR_OFFSET, 421 SRIO_LCSBA1CSR); 422 while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT 423 + SRIO_LCSBA1CSR_OFFSET) 424 != SRIO_LCSBA1CSR) 425 ; 426 /* 427 * And then set the BRR register 428 * to release slave core 429 */ 430 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT 431 + SRIO_MAINT_WIN_SIZE 432 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, 433 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); 434 } else { 435 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT 436 + SRIO_LCSBA1CSR_OFFSET, 437 SRIO_LCSBA1CSR); 438 while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT 439 + SRIO_LCSBA1CSR_OFFSET) 440 != SRIO_LCSBA1CSR) 441 ; 442 /* 443 * And then set the BRR register 444 * to release slave core 445 */ 446 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT 447 + SRIO_MAINT_WIN_SIZE 448 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, 449 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); 450 } 451 debug("SRIOBOOT - MASTER: " 452 "Release slave successfully! Now the slave should start up!\n"); 453 } 454 } else 455 debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port); 456 } 457 #endif 458