1 /* 2 * Copyright 2008-2011 Freescale Semiconductor, Inc. 3 * 4 * (C) Copyright 2000 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <linux/compiler.h> 28 #include <asm/fsl_law.h> 29 #include <asm/io.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS 34 35 #ifdef CONFIG_FSL_CORENET 36 #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR) 37 #define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar) 38 #define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh) 39 #define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl) 40 #define LAWBAR_SHIFT 0 41 #else 42 #define LAW_BASE (CONFIG_SYS_IMMR + 0xc08) 43 #define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2) 44 #define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x) 45 #define LAWBAR_SHIFT 12 46 #endif 47 48 49 static inline phys_addr_t get_law_base_addr(int idx) 50 { 51 #ifdef CONFIG_FSL_CORENET 52 return (phys_addr_t) 53 ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) | 54 in_be32(LAWBARL_ADDR(idx)); 55 #else 56 return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT; 57 #endif 58 } 59 60 static inline void set_law_base_addr(int idx, phys_addr_t addr) 61 { 62 #ifdef CONFIG_FSL_CORENET 63 out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff); 64 out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32); 65 #else 66 out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT); 67 #endif 68 } 69 70 void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) 71 { 72 gd->arch.used_laws |= (1 << idx); 73 74 out_be32(LAWAR_ADDR(idx), 0); 75 set_law_base_addr(idx, addr); 76 out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz); 77 78 /* Read back so that we sync the writes */ 79 in_be32(LAWAR_ADDR(idx)); 80 } 81 82 void disable_law(u8 idx) 83 { 84 gd->arch.used_laws &= ~(1 << idx); 85 86 out_be32(LAWAR_ADDR(idx), 0); 87 set_law_base_addr(idx, 0); 88 89 /* Read back so that we sync the writes */ 90 in_be32(LAWAR_ADDR(idx)); 91 92 return; 93 } 94 95 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) 96 static int get_law_entry(u8 i, struct law_entry *e) 97 { 98 u32 lawar; 99 100 lawar = in_be32(LAWAR_ADDR(i)); 101 102 if (!(lawar & LAW_EN)) 103 return 0; 104 105 e->addr = get_law_base_addr(i); 106 e->size = lawar & 0x3f; 107 e->trgt_id = (lawar >> 20) & 0xff; 108 109 return 1; 110 } 111 #endif 112 113 int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) 114 { 115 u32 idx = ffz(gd->arch.used_laws); 116 117 if (idx >= FSL_HW_NUM_LAWS) 118 return -1; 119 120 set_law(idx, addr, sz, id); 121 122 return idx; 123 } 124 125 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) 126 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) 127 { 128 u32 idx; 129 130 /* we have no LAWs free */ 131 if (gd->arch.used_laws == -1) 132 return -1; 133 134 /* grab the last free law */ 135 idx = __ilog2(~(gd->arch.used_laws)); 136 137 if (idx >= FSL_HW_NUM_LAWS) 138 return -1; 139 140 set_law(idx, addr, sz, id); 141 142 return idx; 143 } 144 145 struct law_entry find_law(phys_addr_t addr) 146 { 147 struct law_entry entry; 148 int i; 149 150 entry.index = -1; 151 entry.addr = 0; 152 entry.size = 0; 153 entry.trgt_id = 0; 154 155 for (i = 0; i < FSL_HW_NUM_LAWS; i++) { 156 u64 upper; 157 158 if (!get_law_entry(i, &entry)) 159 continue; 160 161 upper = entry.addr + (2ull << entry.size); 162 if ((addr >= entry.addr) && (addr < upper)) { 163 entry.index = i; 164 break; 165 } 166 } 167 168 return entry; 169 } 170 171 void print_laws(void) 172 { 173 int i; 174 u32 lawar; 175 176 printf("\nLocal Access Window Configuration\n"); 177 for (i = 0; i < FSL_HW_NUM_LAWS; i++) { 178 lawar = in_be32(LAWAR_ADDR(i)); 179 #ifdef CONFIG_FSL_CORENET 180 printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x", 181 i, in_be32(LAWBARH_ADDR(i)), 182 i, in_be32(LAWBARL_ADDR(i))); 183 #else 184 printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i))); 185 #endif 186 printf(" LAWAR%02d: 0x%08x\n", i, lawar); 187 printf("\t(EN: %d TGT: 0x%02x SIZE: ", 188 (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff); 189 print_size(lawar_size(lawar), ")\n"); 190 } 191 192 return; 193 } 194 195 /* use up to 2 LAWs for DDR, used the last available LAWs */ 196 int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) 197 { 198 u64 start_align, law_sz; 199 int law_sz_enc; 200 201 if (start == 0) 202 start_align = 1ull << (LAW_SIZE_32G + 1); 203 else 204 start_align = 1ull << (ffs64(start) - 1); 205 law_sz = min(start_align, sz); 206 law_sz_enc = __ilog2_u64(law_sz) - 1; 207 208 if (set_last_law(start, law_sz_enc, id) < 0) 209 return -1; 210 211 /* recalculate size based on what was actually covered by the law */ 212 law_sz = 1ull << __ilog2_u64(law_sz); 213 214 /* do we still have anything to map */ 215 sz = sz - law_sz; 216 if (sz) { 217 start += law_sz; 218 219 start_align = 1ull << (ffs64(start) - 1); 220 law_sz = min(start_align, sz); 221 law_sz_enc = __ilog2_u64(law_sz) - 1; 222 223 if (set_last_law(start, law_sz_enc, id) < 0) 224 return -1; 225 } else { 226 return 0; 227 } 228 229 /* do we still have anything to map */ 230 sz = sz - law_sz; 231 if (sz) 232 return 1; 233 234 return 0; 235 } 236 #endif /* not SPL */ 237 238 void init_laws(void) 239 { 240 int i; 241 242 #if FSL_HW_NUM_LAWS < 32 243 gd->arch.used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); 244 #elif FSL_HW_NUM_LAWS == 32 245 gd->arch.used_laws = 0; 246 #else 247 #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes 248 #endif 249 250 /* 251 * Any LAWs that were set up before we booted assume they are meant to 252 * be around and mark them used. 253 */ 254 for (i = 0; i < FSL_HW_NUM_LAWS; i++) { 255 u32 lawar = in_be32(LAWAR_ADDR(i)); 256 257 if (lawar & LAW_EN) 258 gd->arch.used_laws |= (1 << i); 259 } 260 261 #if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ 262 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) 263 /* 264 * in SPL boot we've already parsed the law_table and setup those LAWs 265 * so don't do it again. 266 */ 267 return; 268 #endif 269 270 for (i = 0; i < num_law_entries; i++) { 271 if (law_table[i].index == -1) 272 set_next_law(law_table[i].addr, law_table[i].size, 273 law_table[i].trgt_id); 274 else 275 set_law(law_table[i].index, law_table[i].addr, 276 law_table[i].size, law_table[i].trgt_id); 277 } 278 279 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 280 /* check RCW to get which port is used for boot */ 281 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 282 u32 bootloc = in_be32(&gur->rcwsr[6]); 283 /* 284 * in SRIO or PCIE boot we need to set specail LAWs for 285 * SRIO or PCIE interfaces. 286 */ 287 switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { 288 case 0x0: /* boot from PCIE1 */ 289 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 290 LAW_SIZE_1M, 291 LAW_TRGT_IF_PCIE_1); 292 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 293 LAW_SIZE_1M, 294 LAW_TRGT_IF_PCIE_1); 295 break; 296 case 0x1: /* boot from PCIE2 */ 297 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 298 LAW_SIZE_1M, 299 LAW_TRGT_IF_PCIE_2); 300 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 301 LAW_SIZE_1M, 302 LAW_TRGT_IF_PCIE_2); 303 break; 304 case 0x2: /* boot from PCIE3 */ 305 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 306 LAW_SIZE_1M, 307 LAW_TRGT_IF_PCIE_3); 308 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 309 LAW_SIZE_1M, 310 LAW_TRGT_IF_PCIE_3); 311 break; 312 case 0x8: /* boot from SRIO1 */ 313 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 314 LAW_SIZE_1M, 315 LAW_TRGT_IF_RIO_1); 316 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 317 LAW_SIZE_1M, 318 LAW_TRGT_IF_RIO_1); 319 break; 320 case 0x9: /* boot from SRIO2 */ 321 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, 322 LAW_SIZE_1M, 323 LAW_TRGT_IF_RIO_2); 324 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, 325 LAW_SIZE_1M, 326 LAW_TRGT_IF_RIO_2); 327 break; 328 default: 329 break; 330 } 331 #endif 332 333 return ; 334 } 335