1 /*
2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 #include <common.h>
10 #include <asm/fsl_lbc.h>
11 
12 #ifdef CONFIG_MPC85xx
13 /* Boards should provide their own version of this if they use lbc sdram */
14 void __lbc_sdram_init(void)
15 {
16 	/* Do nothing */
17 }
18 void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init")));
19 #endif
20 
21 
22 void print_lbc_regs(void)
23 {
24 	int i;
25 
26 	printf("\nLocal Bus Controller Registers\n");
27 	for (i = 0; i < 8; i++) {
28 		printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
29 		       i, get_lbc_br(i), i, get_lbc_or(i));
30 	}
31 }
32 
33 void init_early_memctl_regs(void)
34 {
35 	uint init_br1 = 1;
36 
37 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
38 	/* Set the local bus monitor timeout value to the maximum */
39 	clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf);
40 #endif
41 
42 #ifdef CONFIG_MPC85xx
43 	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
44 	if (get_lbc_br(1) & BR_V)
45 		init_br1 = 0;
46 #endif
47 
48 	/*
49 	 * Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
50 	 * preliminary addresses - these have to be modified later
51 	 * when FLASH size has been determined
52 	 */
53 #if defined(CONFIG_SYS_OR0_REMAP)
54 	set_lbc_or(0, CONFIG_SYS_OR0_REMAP);
55 #endif
56 #if defined(CONFIG_SYS_OR1_REMAP)
57 	set_lbc_or(1, CONFIG_SYS_OR1_REMAP);
58 #endif
59 	/* now restrict to preliminary range */
60 	if (init_br1) {
61 		set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
62 		set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
63 
64 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
65 		set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
66 		set_lbc_br(1, CONFIG_SYS_BR1_PRELIM);
67 #endif
68 	}
69 
70 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
71 	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
72 	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
73 #endif
74 
75 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
76 	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
77 	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
78 #endif
79 
80 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
81 	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
82 	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
83 #endif
84 
85 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
86 	set_lbc_or(5, CONFIG_SYS_OR5_PRELIM);
87 	set_lbc_br(5, CONFIG_SYS_BR5_PRELIM);
88 #endif
89 
90 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
91 	set_lbc_or(6, CONFIG_SYS_OR6_PRELIM);
92 	set_lbc_br(6, CONFIG_SYS_BR6_PRELIM);
93 #endif
94 
95 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
96 	set_lbc_or(7, CONFIG_SYS_OR7_PRELIM);
97 	set_lbc_br(7, CONFIG_SYS_BR7_PRELIM);
98 #endif
99 }
100 
101 /*
102  * Configures a UPM. The function requires the respective MxMR to be set
103  * before calling this function. "size" is the number or entries, not a sizeof.
104  */
105 void upmconfig(uint upm, uint *table, uint size)
106 {
107 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
108 	int i, mdr, mad, old_mad = 0;
109 	u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
110 	u32 msel = BR_UPMx_TO_MSEL(upm);
111 	u32 *mxmr = &lbc->mamr + upm;
112 	volatile u8 *dummy = NULL;
113 
114 	if (upm < UPMA || upm > UPMC) {
115 		printf("Error: %s() Bad UPM index %d\n", __func__, upm);
116 		hang();
117 	}
118 
119 	/*
120 	 * Find the address for the dummy write - scan all of the BRs until we
121 	 * find one matching the UPM and extract the base address bits from it.
122 	 */
123 	for (i = 0; i < 8; i++) {
124 		if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | msel)) {
125 			dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
126 			break;
127 		}
128 	}
129 
130 	if (!dummy) {
131 		printf("Error: %s() No matching BR\n", __func__);
132 		hang();
133 	}
134 
135 	/* Program UPM using steps outlined by the reference manual */
136 	for (i = 0; i < size; i++) {
137 		out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
138 		out_be32(&lbc->mdr, table[i]);
139 		mdr = in_be32(&lbc->mdr);
140 		*dummy = 0;
141 		do {
142 			mad = in_be32(mxmr) & MxMR_MAD_MSK;
143 		} while (mad <= old_mad && !(!mad && i == (size-1)));
144 		old_mad = mad;
145 	}
146 
147 	/* Return to normal operation */
148 	out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_NORM);
149 }
150